Anyone knows if FET gm tracks Id over temperature?

[magic]

Question as in the title: can I expect a lightly/not degenerated MOSFET or JFET common source amplifier to maintain roughly constant transconductance over temperature provided that drain current is regulated?

I suppose it would work for BJT if one can live with the minor variation resulting from thermal voltage, but I have little idea how FETs behave. I think the subthreshold region looks particularly promising because supposedly Id is exponential with Vgs so gm ought to be proportional to Id, but how does temperature factor into it?

I know that there are "feedforward" biasing tricks which stabilize gm itself but that looks like no fun given all the thermally coupled parts required.

[T3sl4co1l]

Offhand, Vgs(th) and gm fall with rising temp, so that Rds(on) and Id tend to rise.  Not sure offhand if Id falls, or rises relatively faster, in subthreshold.

Tim

[Wimberleytech]

Question as in the title: can I expect a lightly/not degenerated MOSFET or JFET common source amplifier to maintain roughly constant transconductance over temperature provided that drain current is regulated?

Not sure what you mean by "degenerated."
For a MOSFET configured as a common-source amplifier with a current source bias and operating in strong-inversion, saturated region, the gm is given by (2 K' W/L I)^1/2
K' = u₀ C_OX
We can say that the C_OX and W/L terms are not temperature dependent to the first order at least.
The mobility term is very dependent on temperature: T ^-1.5
So if you design a temperature independent bias current (easy to do), the gm will vary according to the mobility term.  Plug it in and do the derivative.

The above analysis is based on the simple Schichman-Hodges model.

--update--
Pondering this further, the answer above is correct, but may not really be useful in your circuit configuration.  For example, if you are making a single stage ac-coupled amplifier with a MOSFET biased with resistors and a resistor load, the analysis has to be done differently.  However, if you are considering a common-source amplifier with a current-source load as part of an opamp design (integrated) then the above analysis applies.

So, to zoom in on your answer, the circuit topology would be useful.

[magic]

Basically, what happened is that I found some pretty low capacitance / highish transconductance jellybean MOSFET (or so the datasheet says) and I'm wondering how fast of an amp it could do.

So, discrete and single stage

Degeneration = source degeneration = resistor in the source circuit to set bias current and control effective transconductance.
But it's a gain killer, so the idea is to keep constant current by shifting gate bias (has to be done anyway to prevent thermal runaway) and pray that gm won't go off the charts. I guess I should pull out a breadboard and try it with some 2n7000 but I have a mess now, don't ask , so I wondered if perhaps there is any known theory of that.

[Wimberleytech]

Basically, what happened is that I found some pretty low capacitance / highish transconductance jellybean MOSFET (or so the datasheet says) and I'm wondering how fast of an amp it could do.

So, discrete and single stage

Degeneration = source degeneration = resistor in the source circuit to set bias current and control effective transconductance.
But it's a gain killer, so the idea is to keep constant current by shifting gate bias (has to be done anyway to prevent thermal runaway) and pray that gm won't go off the charts. I guess I should pull out a breadboard and try it with some 2n7000 but I have a mess now, don't ask , so I wondered if perhaps there is any known theory of that.

Ahhh...source degeneration--got it.

[Gerhard_dk4xp]

I found for JFETs in simulation, that gain changed by 0.8 dB / 10 °C between
0 and 60°C when the source current was enforced with a current source.
The FET sources were deblocked with large electrolytics so they were at AC GND.
The noise was very sensitive to cap leakage in real life.

cheers, Gerhard

[muawiya]

the threshold voltage is proportional to kT/q*ln(NBody/ni) -> kT/q*ln(NBody) - kT/q*ln(ni) = A*T - B*T*f(T)

f(T) = ln(ni(T)) function of temperature, where ni the intrinsic concentration of carriers in the body increases

dVth/dT = A - B*f(T) -B*T*f'(T).

Vth decreases with temperature.

I find this easier to remember from device physics we know that Vth is proportional to Ei(bulk)-Ef as temperature increases the intrinsic carrier concentration in the bulk increases causing the Ei(bulk)-Ef to decrease as the device begins to look more and more like an undoped silicone when temperature. Thus for both NMOS & PMOS |Vth| decreases with temperature

However it seems that the effect due to a decrease in mobility at higher temperature has a stronger effect (more scattering) and the observed IDS decreases with temperature.

As far as in the sub threshold regime Id tends to increase exponential with temperature as you have increased intrinsic carriers at higher temperatures.

[Kevin.D]

In a  power MOSFET data sheet you should see a plot of transfer characteristics
like this typical example here from a IRFP250 which plot's Id versus Vgs characteristics at two different junction temperatures.
Notice the important point where the two plots crossover (this point can be referred to as the the Zero temp co 'ztc' point),
The reason For the crossover is that there are two competing temperature coefficients.



When the MOSFET is operating (in saturation) below that ztc point (Id <25A and VGS < ~ 6.3V for the IRfP250) then Vgs will dominate the size of drain current (Id=kn/2*(Vgs^2)), but since Vgs=VGS(total)-Vgs(threshold) and the important bit here is thatVgs(threshold) has a neg temp coeff (reduces with temp) it will create an increase in Vgs and so increase Id for a fixed VGS when the junction temp increases.
But When operating in the region above that ztc point at higher saturation currents (or in the triode 'hard on' switching region) then channel resistance (carrier mobility,and other resistances) will become the dominant limitation on drain current rather than the Vgs value. And these have a POSITVE temp coeff (channel resistance increases with temp) and so cause Id reduction with increasing temperature.
So to answer the opener MOSFET Vgs(th) variation (both initial and temp driven) would be his main interest.

[Wimberleytech]

In a  power MOSFET data sheet you should see a plot of transfer characteristics
like this typical example here from a IRFP250 which plot's Id versus Vgs characteristics at two different junction temperatures.
Notice the important point where the two plots crossover (this point can be referred to as the the Zero temp co 'ztc' point),
The reason For the crossover is that there are two competing temperature coefficients.



When the MOSFET is operating (in saturation) below that ztc point (Id <25A and Vgs < ~ 6.3V for the IRfP250) then Vgs will dominate the size of drain current (Id=kn/2*(Vgs^2)), but since Vgs=VGS(total)-Vgs(threshold) and the important bit here is thatVgs(threshold) has a neg temp coeff (reduces with temp) it will create an increase in Vgs and so increase Id for a fixed VGS when the junction temp increases.
But When operating in the region above that ztc point at higher saturation currents (or in the triode 'hard on' switching region) then channel resistance (carrier mobility,and other resistances) will become the dominant limitation on drain current rather than the Vgs value. And these have a POSITVE temp coeff (channel resistance increases with temp) and so cause Id reduction with increasing temperature.
So to answer the opener MOSFET Vgs(th) variation (both initial and temp driven) would be his main interest.

Agree...and stated more simply: di/dT due to mobility alone is negative and di/dT due to V_T alone is positive.  For a given transistor (a unique transistor...not just a part number), you can dial up a V_GS such that the mobility term and the V_T term cancel, yielding di/dT = 0.

However, the original question deals with transconductance, gm.  This magic point (above) does not yeild ztc gm.

[magic]

Actually, I think this plot does hold the answer to my original question.

We can look at the slopes at 25°C and 150°C for any given drain current and it is apparent that below the zero tempco point they are always converging with increasing Id, so transconductance at 25°C must be consistently higher than at 150°C, and above that point they are always diverging, and again, 25°C transconductance is the higher one. So at any given drain current, transconductance is never stable; otherwise the lines would be parallel.

At the same time, if temperature appears as a factor of sqrt(T^-1.5) where T is the absolute temperature on the order of 300K, it probably isn't too bad in practice and Gerhard's simulation seems to confirm.

[T3sl4co1l]

A correction, that's at V_DS = 50V so it should be well above the triode region.

It doesn't look like the slopes ever match, along any given horizontal pair of points; they approach each other at very high currents, but that may be as much visual (semilog plot) as due to gm simply running out of steam at high currents.

So it would seem a one-to-one function should solve it, i.e., I_D decreasing with T, at whatever exact rate happens to fit (exp(-T^1.5)??).

Which also means, the maximum power point, or distortion-free class A dynamic range (or anything related, like IP3), will vary, so keep that in mind as far as guard-banding the design.

Tim