EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: tigrou on November 06, 2021, 07:38:52 pm
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Could someone explain me what the "X" character or a line centered vertically (not a 0 or not a 1) means in a logic analyzer, as seen at 0ns in this image ?
(https://i.imgur.com/isG5LnN.png)
Does it means there is no clearly defined signal at that time ? (eg: invalid state)
In a logic analyzer, when validating some module against a unit test, how does it tell the user that the signal can be "whatever, we don't care" ?
For example when a flip flop is not initialized yet the Q0 and Q1 can be anything (until it's cleared out). How is this indicated ? (I ask because I'm a beginner and have very little experience with logic analyzers)
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That's exactly how undefined state is indicated. This will only happen in behavioral simulation where rules of the language (Verilog/VHDL) are applied literally.
Another thing you may see there is Z for high impedance state, but again, this is something that can only happen in simulation in practice, since there are no high-impedance elements inside the FPGAs. It is only possible in I./O buffers.
In real life all those elements will default to some defined values. But it is useful to see them in simulation so that you know what is going on logically.
There is no "don't care" in simulation. Simulation shows the factual behaviour, it is up to you to interpret if something is acceptable or not. Often having red stuff after a reset signal is a bad sign. In this case you can see that all the signals got initialized on the same cycle as the release of the "areset" signal. This is a very typical behaviour.
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Thank you for your answer, it's pretty clear ;)