Vbc actually has very little to do with it. Most saturate at positive Vbc, some at negative (particularly power transistors, particularly high voltage ones).
Saturation might better be defined by the increase in h_oe, or the decrease in h_fe, following some threshold (e.g. a change of 2x or 10x or whatever).
(Look up the definitions for h-parameters, if needed. They're ratios of device input and output voltages and currents, specifically, the changes in them around a center bias level.)
This is reflected by the design process, where we might use a BJT as a saturated switch at some forced hFE(sat). That is, the base is driven with Ib, the collector has a load current less than Ib * hFE(sat), and the collector voltage will pull down to whatever it saturates to.
The fact that the collector voltage has a low impedance, is another way of saying "large h_oe". That is, the output conductance, it looks conductive, like, y'know, a switch -- in contrast to the off state (no current flow, or dynamic resistance), or the linear range (current flow, but high dynamic resistance).
Tim