555 Input Impedance

[eev_carl]

Hi,

I'm using a pull-up resistor and a switch to trigger a monostable multivibrator circuit made with a 555.  I read that this resistor value ought to be 10% of the input impedance.  I'm using 10k which is working fine.

What is the input impedance of the 555?  I have both the BJT and CMOS versions but didn't see any explicit value given in the datasheet.  Is it just general "high impedance" and not something I should care about?

Thanks,
Carl

[Zero999]

The input impedance is irrelevant.

The NE555 timer has small input bias current from the input transistor in the trigger comparator. According to the internal schematic on Wikipedia, the input has a PNP transistor, so the bias current will be positive, i.e. a current source. The data sheet says it's 2μA worst case. This means if you're using a switch between the trigger and 0V, you'll probably find it work without a pull-up resistor though it's a good idea to have one to improve noise immunity and 10k is a reasonable value.
https://en.wikipedia.org/wiki/555_timer_IC#Internal_schematic
http://www.ti.com/lit/ds/symlink/na555.pdf

The CMOS variants will have an extremely high input impedance and much lower bias current. The 7555 datasheet says 50nA maximum, but it could be as low as 20pA. A pull-up resistor is required for noise immunity.
https://www.renesas.com/eu/en/www/doc/datasheet/icm7555-56.pdf

[T3sl4co1l]

The input impedance is irrelevant.
...
The CMOS variants will have an extremely high input impedance...

Which one is it?

The quirk is this: the input bias current isn't always drawn, it varies with voltage; and it doesn't vary like a resistor, it varies inconsistently.  Usually for something like a 555, I think it should be stepwise, the current turning on/off around the threshold voltage?  So, there are multiple ways you could define an impedance here.

If we just take the average, that's roughly Rin ~= Vcc/Ibb.  This is most reasonable for purposes of designing a pull-up resistor, and so we should make the resistor < 1/10th of this.

For CMOS, the input bias current is dominated by the ESD protection diodes, which are pretty small, and which leak exponentially more at elevated temperature.  The actual leakage at room temperature may be quite small indeed, but they simply don't bother taking the time to measure it -- it's slow to measure nanoamperes -- so they give a maximum which is considerably higher than the typical value.

As it happens, they do rate the 7555 in nA, so they did take the time to test it, and this allows you to use MΩ resistors and long time constants, which is nice.

Tim

[Zero999]

The input impedance is irrelevant.
...
The CMOS variants will have an extremely high input impedance...

Which one is it?

Yes, you're right, the input impedance isn't important, so I shouldn't have gone on to mention it. I did think about an edit, but decided it wasn't worth it.

The quirk is this: the input bias current isn't always drawn, it varies with voltage; and it doesn't vary like a resistor, it varies inconsistently.  Usually for something like a 555, I think it should be stepwise, the current turning on/off around the threshold voltage?  So, there are multiple ways you could define an impedance here.

If we just take the average, that's roughly Rin ~= Vcc/Ibb.  This is most reasonable for purposes of designing a pull-up resistor, and so we should make the resistor < 1/10th of this.

For CMOS, the input bias current is dominated by the ESD protection diodes, which are pretty small, and which leak exponentially more at elevated temperature.  The actual leakage at room temperature may be quite small indeed, but they simply don't bother taking the time to measure it -- it's slow to measure nanoamperes -- so they give a maximum which is considerably higher than the typical value.

As it happens, they do rate the 7555 in nA, so they did take the time to test it, and this allows you to use MΩ resistors and long time constants, which is nice.

Tim

Yes, the CMOS versions' bias currents have a positive temperature coefficient, as leakage is proportional to the temperature, but the bipolar version has a negative temperature coefficient, as the h_FE of the transistors increases with temperature. I wouldn't expect the bias currents to be anywhere near the stated maximum at room temperature, only at extremes of the temperature rating.

[T3sl4co1l]

More just that, there are more general ways to apply the concept of impedance, and it's not that it's completely inapplicable, but that it's still just as useful, as long as the different assumptions (that apply to those generalizations) are understood.

Speaking of, CMOS leakage typically comes from ESD diodes, and because of this, one or the other may dominate, so the current may be positive (into the pin) or negative.  It generally varies in a Is * tanh(V - Vo) sort of way, reaching a maximum value (positive or negative) at each rail.  Because the voltage drop of one diode is zero and so is its current flow, and the input leakage is entirely the other diode.  So, for Vin = Vss, it's the Vdd diode's leakage, and at Vin = Vdd, it's the Vss diode's leakage, and inbetween, the current changes from one to the other with a zero point somewhere in the middle, but not necessarily at a voltage of (Vdd+Vss)/2.

Which is also another reason why CMOS inputs should not be left open circuit: the leakage can be up or down, or somewhere in the middle, biasing it to be extremely sensitive to noise (and drawing a lot of supply current, or making it prone to oscillation).  In short, they're completely undefined, and very sensitive -- a bad idea to leave open.

And for the same reason, TTL inputs...can...be left open circuit (they go default high), because their input bias current is higher, and negative (for Vin < 3.5V or so).  That is, they tend to pull up to logic high.  They're still vulnerable to noise though, and so should be pulled high or low by default (which, I guess if you want to save a few mA here and there, high is the preferred option).

Tim