More just that, there are more general ways to apply the concept of impedance, and it's not that it's completely inapplicable, but that it's still just as useful, as long as the different assumptions (that apply to those generalizations) are understood.
Speaking of, CMOS leakage typically comes from ESD diodes, and because of this, one or the other may dominate, so the current may be positive (into the pin) or negative. It generally varies in a Is * tanh(V - Vo) sort of way, reaching a maximum value (positive or negative) at each rail. Because the voltage drop of one diode is zero and so is its current flow, and the input leakage is entirely the other diode. So, for Vin = Vss, it's the Vdd diode's leakage, and at Vin = Vdd, it's the Vss diode's leakage, and inbetween, the current changes from one to the other with a zero point somewhere in the middle, but not necessarily at a voltage of (Vdd+Vss)/2.
Which is also another reason why CMOS inputs should not be left open circuit: the leakage can be up or down, or somewhere in the middle, biasing it to be extremely sensitive to noise (and drawing a lot of supply current, or making it prone to oscillation). In short, they're completely undefined, and very sensitive -- a bad idea to leave open.
And for the same reason, TTL inputs...can...be left open circuit (they go default high), because their input bias current is higher, and negative (for Vin < 3.5V or so). That is, they tend to pull up to logic high. They're still vulnerable to noise though, and so should be pulled high or low by default (which, I guess if you want to save a few mA here and there, high is the preferred option).
Tim