who uses fpga's

[Capernicus]

I'm just a GPU nut, I've doing it with direct compute ever since I was 21 doing direct x 6 win32 tutorials watching Martin Short on tv back in the olden days possibly 10 years after inner-space came out.  I loved that movie, it was absolute magic and the robot suit's were fricken amazing! and as I think back terrify the absolute shit out of me now if it ever became a reality. curse the singularity.

So the biggest mystery to me now is, now I'm old,40 sick still feel and look like an immature teenager and just about carked it in the head, what the hell are FPGA's and who uses them -and what do they use them for?

They seem to be a step up from GPU's in what I imagine about them, but thats only a fantasy because I never got the guts to work on them.
One thing that put me off was the cheap ones seem to only go to a megahert for some reason and that ruins the performance interest somewhat of what I thought they could do for me, so I put them off and just kept going with GPUs because they apparently hert quicker. and whats the difference between any type of physical parallelization, isnt it all equally as good as itself? 

But has anyone here got some real experience with them - is there any forums to go to get tips off guys that have been doing it for ages?

The only implementations I've scarcely heard about is people use them to emulate old computers perfectly,  but that is to me so uncreative and not even capitalizing on the power to do some original logic with them, at a modern performance,    as long as it fit on the FPGA, isnt it as good as an ASIC - its just with a little wasted space here and there - that seems more like what I'd like to do with it.

GPU's are what I know, and they are good for AI because you can do lots of brute forcing with them,  when it comes to FPGA's is the brute forcing ability higher than a GPU?

[agehall]

FPGAs can be anything you want them to be. They are programmable logic, on a large scale. They are very different from GPUs and I don't really think you can compare the two in any meaningful way.

There is a whole section on this forum dedicated to FPGAs where you can see what people are doing with them. I've used them for custom I/O bridges myself where I need to work with a parallel interface and turn it into a serialized form or vice versa but that is a very trivial usecase.

[mvs]

GPU's are what I know, and they are good for AI because you can do lots of brute forcing with them,  when it comes to FPGA's is the brute forcing ability higher than a GPU?

AI and neuronal networks are based matrix multiplication. You do not need any flexibility of a FPGA hier.
An ASIC with a large amount of matrix multiplier units, like nVidia A100 GPU, will do the job better then any FPGA existent on the market today.

[SilverSolder]

Crypto mining is apparently a popular application...

[CaptDon]

Most of my applications for programmable logic were small enough that I preferred to use CPLD's instead of FPGA's. The biggest difference for me was that a CPLD 'is what it is' directly on power up. An FPGA generally requires some time to 'get educated' from a serial eprom and with EMI glitches an FPGA can suddenly go stupid and lose its programming. A CPLD is more robust and they both can usually use a similar JTAG programming device. FPGA's can be huge and a real workhorse, CPLD's tend to be much smaller in flop capacity and are more for simple logic steering, lookup matix 'corn cob' lookup tables or simple clock signal buffering, steering and dividing.

[rstofer]

You can think of an FPGA as a dumpster-full of unconnected logic chips.  Connect them up to do what you want!

I tend to think in terms of CPUs.  I used the Z80 core from OpenCores.org to recreate a Z80 system complete with a Compact Flash disk drive and the CP/M operating system.  I extended the idea and recreated an IBM 1130 minicomputer that runs all of the factory software unchanged.  I use it as a computing platform from time to time where Fortran and/or plotting is required.

I have also created a version of the LC3 CPU that is so popular at universities for an undergraduate course in computer architecture.

[rstofer]

In terms of raw computing, I would expect the GPUs to win.  Easily... 

I have a Jetson Nano and it's spec'd at about 472 GFlops and TFlop versions are readily available.  It would take a heck of an FPGA to keep up with something like that.  OTOH, my FPGA can have a half dozen SPI channels or any other interface I want.  I can add parallel channels and talk to multiple devices concurrently.  FPGAs are a great deal more flexible but in terms of raw compute power, I don't think they can win.

When we went to the Moon the CDC 6400 was good for a MFlop or so.  The modern Jetson Nano GPU is about 150,000 times faster.

I'm just getting started with the Nano and haven't even a clue about what I'm going to do with it.  I don't tend to have a lot of math problems waiting for a parallel solution.

[SilverSolder]

[...] I don't tend to have a lot of math problems waiting for a parallel solution.

Give your daughter a credit card? 

[Siwastaja]

All those application-specific digital, computationally heavy integrated circuits, but in cases when you can't sell millions of units so can't warrant ASIC design. You only sell from one unit to maybe hundred thousand, so you use FPGA.

Image processing, audio processing, communication, non-trivial cases of power conversion, crypto applications, ...

I have made film scanner control / image processing, and some motor controllers on FPGAs.

Widely used in network routers as well whenever the router is either too new, or too unique of an snowflake professional piece, so it can't include the ASIC which takes a year more development than the FPGA and requires sales in millions.

I'm also quite sure an MRI machine contains a metric shitload of FPGAs.

[rstofer]

But has anyone here got some real experience with them - is there any forums to go to get tips off guys that have been doing it for ages?

VHDLwhiz.com nandland.com and likely a couple of hundred others.  I highly recommend VHDLwhiz

The only implementations I've scarcely heard about is people use them to emulate old computers perfectly,  but that is to me so uncreative and not even capitalizing on the power to do some original logic with them, at a modern performance,    as long as it fit on the FPGA, isnt it as good as an ASIC - its just with a little wasted space here and there - that seems more like what I'd like to do with it.

Uncreative?  Perhaps...

The thing is, back in early 1970, I was introduced to the IBM 1130 computer system and began using one extensively.  Almost all day, every day.  Sometimes for company work, sometimes for college work (Bode' Plots weren't easy back in 1970).  I loved that machine!

And, like all loves, I was disappointed when we were separated.  I wanted to use the identical software in 2005 that I used in 1970.  So I built one!  Every line of IBM code works including the 27 pass FORTRAN compiler.

I had made another attempt to build the machine using with TTL, microprogramming and blown-link PROMS back around '75 or so but the 2102 static ram wasn't readily available.  And, really, I would need 512 of them to create a 32kx16bit memory.  That's a LOT of wire-wrap.

I put the project on back-burner for 30 years and finally got what I wanted with a Spartan III FPGA.  I did the Z80 CP/M project with a Spartan II (a 5V device which I still have).

Everybody remembers their first love.  I got mine back!

FWIW, you probably get higher speeds and lower power with ASIC versus FPGA.  Or so sayeth Google.

http://ibm1130.org/

[JohnnyMalaria]

I'm only in the early stages of FPGA application development but here's what I can already do with a $100 FPGA chip:

1. Capture an I-Q pair of analog signals (FPGA controls the SPI communication etc) typically at 16-bit/32kHz
2. Calculate the amplitude and phase
3. Modify the phase according to my patent
4. Calculate a modified I-Q pair
5. Decimate all IQ data to 1kHz through a suitable IIR filter
6. Calculate Fourier transform of both IQ pairs (1024 point)
7. Do some other calculations based on phase.
8. Average and store data in local block RAM
9. Every second, raise an interrupt for a processor to copy the data for subsequent processing. Because I'm using a Zynq SoC, the FPGA and a dual-core ARM processor are built into the same physical chip.

For every one-second of data I capture, the FFTs are ready within 50 microseconds of arrival of the last data. No software required.

[fourfathom]

Here's my latest FPGA design, using a $5.00 Lattice MachX02 device:
A four-channel event timestamper, using an external 10 MHz clock (or an on-board TCXO), driving the FPGA internal PLL at 100 MHz.  This gives me 10ns timstamp resolution, selectable rising/falling edge detection, selectable prescalers and dividers for each channel, a 48-bit wide timestamp FIFO with SPI interface for the whole thing, as well as miscellaneous logic functions.  I have the FPGA connected to a ATSAMD21 uController.
The entire board, with input signal-conditioning, termination selection, AC/DC coupling selection, and display, is powered from the USB interface.  The uController processes these timestamps for frequency/period/duty-cycle measurements, and event tagging. This handles input frequencies up to 200+ MHz and events many weeks apart, four independent channels.

[Kerlin]

In my experience the biggest use of FPGAs has been clearly where the designer wants to hide the design secrets of a piece of equipment.
I have seen them used most extensively in military and avionics equipment.
The other applications have been where speed and a cheap price is a requirement, like the dash cam I fitted to my car.

[Capernicus]

Thanks for all the replys,  sorry I was sick and I to sleep for a day.

In terms of raw computing, I would expect the GPUs to win.  Easily... 

I have a Jetson Nano and it's spec'd at about 472 GFlops and TFlop versions are readily available.  It would take a heck of an FPGA to keep up with something like that.  OTOH, my FPGA can have a half dozen SPI channels or any other interface I want.  I can add parallel channels and talk to multiple devices concurrently.  FPGAs are a great deal more flexible but in terms of raw compute power, I don't think they can win.

When we went to the Moon the CDC 6400 was good for a MFlop or so.  The modern Jetson Nano GPU is about 150,000 times faster.

I'm just getting started with the Nano and haven't even a clue about what I'm going to do with it.  I don't tend to have a lot of math problems waiting for a parallel solution.

A Jetson Nano is a tiny GPU,   and if that can already beat an FPGA,  FPGAs are useless!!

I'm only in the early stages of FPGA application development but here's what I can already do with a $100 FPGA chip:

1. Capture an I-Q pair of analog signals (FPGA controls the SPI communication etc) typically at 16-bit/32kHz
2. Calculate the amplitude and phase
3. Modify the phase according to my patent
4. Calculate a modified I-Q pair
5. Decimate all IQ data to 1kHz through a suitable IIR filter
6. Calculate Fourier transform of both IQ pairs (1024 point)
7. Do some other calculations based on phase.
8. Average and store data in local block RAM
9. Every second, raise an interrupt for a processor to copy the data for subsequent processing. Because I'm using a Zynq SoC, the FPGA and a dual-core ARM processor are built into the same physical chip.

For every one-second of data I capture, the FFTs are ready within 50 microseconds of arrival of the last data. No software required.

Yes I realize you put in a method,   and to get parallel power, you just put the same method repeated in more than once. Did that use up all the resources of the FPGA?
How many times you put that code into the FPGA to run it more than once in parallel?    Isnt the more expensive the FPGA the more gates it has?

[JohnnyMalaria]

Yes I realize you put in a method,   and to get parallel power, you just put the same method repeated in more than once. Did that use up all the resources of the FPGA?
How many times you put that code into the FPGA to run it more than once in parallel?    Isnt the more expensive the FPGA the more gates it has?

That's not how it works. You don't put multiple copies of the methods in parallel. You exploit the fact that every flip-flop etc in the logic is clocked and simply responds every clock cycle to whatever it's connected to. So, one area of the FPGA logic could be doing an FFT and another creating a MIDI stream of Happy Birthday. And another could implement an HDMI interface to drive a display. The power comes from the speed. In my case, for example, new analog data arrive every 30 microseconds. With the chip running at 100 MHz, that's 30,000 clock cycles between new data. In my current design, the FFT uses about 3% of the FPGA's resources.

[joeqsmith]

So the biggest mystery to me now is, now I'm old,40 sick still feel and look like an immature teenager and just about carked it in the head, what the hell are FPGA's and who uses them -and what do they use them for?

I have very limited experience using GPUs.   For most things I do, they are a poor choice.   In most cases, they wouldn't even be an option as I tend to work more on the hardware side of things.   More often than not, I will use an FPGA in cases where I require critical timing.   Sorry, I can't provide you with too many examples and sadly, nothing recent.    Shown below is my Hayabusa hardware in the loop simulator.  The simulator starts around 37:00 in.   Because Windows doesn't make for a great realtime OS, most of the heavy lifting is done in an FPGA.       


Here are some very old boards I built back in the 90s to play around with my own CPU designs.   




Here is a reverse print server I built using an FPGA and Motorola 6811.  The FPGA handles the DRAM, DMA, printer port.  The CPU handles the high level  Ethernet stack (I wrote in assembler).   


Today, even the smallest parts would out perform anything I have shown in these videos.   About 4 years ago I purchased a cheap Xilinx eval board and had some fun with it.  I could clock that part in excess of 700MHz.   Here you can see it generating pseudo random patterns on the scope.   
https://www.eevblog.com/forum/microcontrollers/typical-speed-of-fpgas/msg1274875/#msg1274875

[jmelson]

A Jetson Nano is a tiny GPU,   and if that can already beat an FPGA,  FPGAs are useless!!

I make a line of products that all use FPGAs or CPLDs.  The FPGA does many things at the same time.  On one device it watches quadrature encoders for any transitions, performing digital filtering from 1 to 10 MHz, so it can count up to 5 million quadrature transitions a second with a guarantee to not miss any.  It does that on 4 encoders in parallel.  It also generates 4 PWM signals with a 40 MHz clock, so you have 25 ns steps of pulse width.  And, it also communicates with a host CPU and some digital I/O.  While that can be done with a CPU, a CPU only does ONE THING at a time.  Guarantees to not miss any encoder counts or to give very precise PWM timing become difficult.  This is all done in ONE $10 chip with a $0.69 serial EPROM to store the configuration.

For massive number crunching, CPUs and GPUs have an advantage.  For interfacing to real-world events and doing many things at once, FPGAs really can show an advantage.

Jon

[rstofer]

I built the IBM1130 around a Spartan 3 1200k device which has 1.2 million system gates.  That's a fairly large chip as things go.

The system includes a CPU plus emulations for the card reader, line printer, keyboard, typewriter (all wind up as serial ports) plus a Compact Flash and an SPI channel delivering plotter step commands to an LPC1768 ARM chip that converts the steps to HPGL sentences and sends plots to my networked LaserJet.  It's not a drum plotter but it works pretty well.  See attached PlotArea.png -- yes, I get carried away sometimes.

This easily fits in the device and, in fact, uses just 25% of the LUTs (Look Up Tables) - see attached summary.

These days, the hot setup is the Artix 7 and I prefer the 100T variant and my project would use on the order of 17% of the available slices.  Maybe less because the Artix uses 6 input LUTs and the Spartan 3 only used 4 input LUTs.  And I wouldn't have to go off-chip to create the RAM.  The system maximum is 32k x 16bits.  Fits pretty easy in the massive BlockRAM of the 100T.

That 100T device is like a virtual dumpster full of logic and it's reasonably priced on Digilent boards.  See page 3 of the attached .pdf

https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/

[rstofer]

A Jetson Nano is a tiny GPU,   and if that can already beat an FPGA,  FPGAs are useless!!

I'm just starting with GPUs so I know exactly nothing. 

One question though:  How do I use a GPU to create that PlotArea graph I posted above.  It has to start out using an obsolete version of FORTRAN and wind up as step pulses sent over SPI to an off-board gadget that converts them to HPGL sentences and forwards them to a LaserJet over TCP/IP.  Let's just omit that part, it could still be external to the GPU.

I'm not betting that the GPU is any part of the solution to that requirement.  Maybe it could compute the points for the graph but that's about it.  Math isn't the big part of this project.

[Capernicus]

joeqsmith!   thats amazing stuff,  so u build your own computers from scratch.  I loved the pong game,  it was so cool watching that old computer go faster than our computers today even with gigahert clock speeds!!   Things have gone backwards somewhat.

Thanks for the videos, really fun educational stuff.    Things seem a little decietful with this computer stuff (but maybe its just nonsense in my head), I'll eventually work it out tho, just have to keep seeing things here and there and thinking.

This easily fits in the device and, in fact, uses just 25% of the LUTs (Look Up Tables) - see attached summary.

So u can build a computer from scratch too - Thats majorly cool.
If u took up 25% of the FPGA with a cpu - Couldn't you put 4 of them on the chip then and run em asynch?   Im a little confused,  its what your like when your just started at the bum of the mountain ready to shoot past the apex and fly like an eagle.

One question though:  How do I use a GPU to create that PlotArea graph I posted above.  It has to start out using an obsolete version of FORTRAN and wind up as step pulses sent over SPI to an off-board gadget that converts them to HPGL sentences and forwards them to a LaserJet over TCP/IP.  Let's just omit that part, it could still be external to the GPU.

Just do the function range in parallel,  just make sure you are using at least as much threads as cuda cores on your machine and then its saturated and should be 99% efficiency.  Another thing that affects efficiency (alot) is accessing less video ram in the code, the more ram that is repeat accessed the more u get the memory lookup for free.  (Thats even between all of the cuda cores)  doing maths functions slows you down, it actually goes worse than what I was expecting it too, u go fast for accessing small lookup tables than doing maths functions (as long as there is alot of repeat reads), unexpectedly.



I'm gathering all the information, which I thank everyone for. 

The best idea I have right now,  about these FPGA's even tho I dont know much about them (Im a programmer, not a hardware guy) Is if you put in a simpler computer, it means that you get more repeats of it than a complex computer,   so if its a frogger computer, you get to run more at once than if its a doom computer.  (More effective framerate.) 

Even tho that rings true to just running software as a programmer as well,  its the same.


Ill definitely try an FPGA forum next time, instead of in the beginners section,  thanks everyone for the replys.

[crossroad]

If u took up 25% of the FPGA with a cpu - Couldn't you put 4 of them on the chip then and run em asynch?

Glue logic to make multiple cores work together efficiently is non trivial.

I notice that you seem to focus on "how much you can pack into and FPGA" and comparing them to modern CPUs and GPUs solely by numerical performance metrics. A big part of what makes FPGAs so useful for certain applications is their ability to perform parallel operations with guaranteed latency. They can do that while often having lower power consumption and heat output and program complexity, which are desirable in embedded real time designs.

I'm working on an FMCW radar that uses a Zynq to do some DSP preprocessing/filtering that cannot be matched by microcontrollers (example 50 Msps and 1 GHz clock = 20 cycles between each sample, which is absolutely not enough. 1 GHz in microcontrollers is pretty rare too, though NXP i.MX can reach that) while the FPGA can do it easily. Of course, it's very possible to use a much more powerful modern CPU for this but it would be inefficient and a downright awful engineering decision

[rstofer]

So u can build a computer from scratch too - Thats majorly cool.
If u took up 25% of the FPGA with a cpu - Couldn't you put 4 of them on the chip then and run em asynch?   Im a little confused,  its what your like when your just started at the bum of the mountain ready to shoot past the apex and fly like an eagle.

Sure and with an amazing amount of effort, multiple CPUs could share the RAM in some way.  But since the OS doesn't understand such mechanizations, and the OS is cast in stone,  I'm not sure of the utility.  But, yes, multiple cores would work.  In a more general case, of course they would work.

ETA:  The IBM 1130 came with various hardware devices.  I chose to implement the devices that used DMA transfer versus character interrupt transfer.  I just implemented a DMA channel  and hooked up all the devices (CPU, Card Reader, Line Printer, Disk, Keyboard, Typewriter, Plotter) with a priority scheme.  I was using off-chip memory so I couldn't take advantage of the DualPort BlockRAM.  FWIW, the CPU must have the lowest priority or no other device will ever get a cycle.

I never finished working on the problem but microMouse maze solvers usually use a flood-fill algorithm.  I decided to create a single universal cell (tile) that computed it's value based on the neighbors and then replicating that tile for the entire matrix of 256 cells.  The idea was to get some parallelism in computing the path.  It still winds up being a serial operation but not for the entire matrix of 256 entries.  There's an opportunity for some parallelism.

Once the solution is found, the second pass is easily taken using the value in the computed cells.

https://en.wikipedia.org/wiki/Micromouse
https://en.wikipedia.org/wiki/Flood_fill

There is also the possibility of creating CPUs that don't exist.  I worked at using the output of Niklaus Wirth's P4 Pascal Compiler project as native instructions.  It's not hard, the entire code is just stack operations.  I got hung up when I had to implement complex instructions like floating point multiply and, later, I came to the conclusion that I could take them out of the main state machine or even implement a system call of some kind.  In the real world, the output code ran on an interpreter on a CDC 6400.

http://pascal.hansotten.com/niklaus-wirth/px-compilers/p4-compiler/

Back around 1980, the UCSD variant of the P4 project was very popular on small computers.  I did a lot of work adding IO devices to UCSD Pascal.  I truly enjoyed using the language.

Who wouldn't want an Apollo Guidance Computer?

https://github.com/rzinkstok/fpga_agc
https://github.com/virtualagc/agc_simulation

No, I haven't pursued these.

One more thing:  PacMan!  The OpenCores T80 (Z80) core will run PacMan with the original ROMs.  There is nothing quite so iconic as PacMan.  I mean Galaga is great but PacMan is historic.  Yes, I have the electronics (Digilent Nexys 2 board), I just don't have room for the bar table.  I do have room for a full size arcade cabinet running MAME (PC based but another way to get PacMan).

https://www.mamedev.org/

This system plays a LOT of the old arcade games - probably more than a thousand by now.  I built my cabinet after I retired back in '03.

There are a number of sites dealing with vintage games.  Here is one:

https://www.fpgaarcade.com/

[SilverSolder]

[...]

Back around 1980, the UCSD variant of the P4 project was very popular on small computers.  I did a lot of work adding IO devices to UCSD Pascal.  I truly enjoyed using the language.

[...]

Ha, that's funny - I learned to program on an Apple ][e using UCSD Pascal...  and even used it on early PCs.  Very cool environment! 

An FPGA P-machine would be an awesome thing! 

These days I use Delphi when I can, and find it more enjoyable than other environments.

[rstofer]

An FPGA P-machine would be an awesome thing! 

It would be smokin' fast!

UCSD Pascal was fast even on 6 MHz Z80s and an interpreter.  Imagine native P code at 100 MHz (or more).

I really like Wirth's book "Algorithms Plus Data Structures = Programs".  It is my favorite text on data structures and traversing.  I have implemented that P0 compiler from the last chapter several times.  I actually think I understand recursive descent compilers.

https://www.alibris.com/booksearch?mtype=B&keyword=niklaus+wirth

Our local community college has a Pascal course as one of the very first in the sequence of computer science.  I doubt that anybody is still using it but it remains my favorite language.  I haven't worked with Delphi but I know I would like it.  Today we can use Astrobe on ARMs and FPGAs.  Astrobe is a variant of Oberon which is an upgrade from Modula which is an upgrade from Pascal which is an upgrade from Algol.  Or something like that...

https://www.astrobe.com/

I would still like Algol.  In school I had to write a compiler for a tiny version of Algol using, of all things, Basic.  It was UGLY!  Had I thought through it, I would have written a very tiny version and then bootstrapped up to something workable.  Kind of like that P0 compiler.  It would be possible to use that to write the P4 compiler in some series of steps.

[mvs]

If u took up 25% of the FPGA with a cpu - Couldn't you put 4 of them on the chip then and run em asynch?   Im a little confused,  its what your like when your just started at the bum of the mountain ready to shoot past the apex and fly like an eagle.

Yes, you can, but this is not the best way to increase performance. The funny thing about FPGA is that you can build a CPU that is designed/optimized for the task. For instance if you have a need to do crypto - you can implement instructions for modular and big integer arythmetic, crypto functions or even whole algorithms in hardware. 
You are also not restricted with word length in any way. It does not need to be even a power of 2.