I think it's getting somewhere now. Good job!
Now, I think you can keep the net ties, if they help you staying close to the the sample schematic and if they don't confuse you, just keep in mind to treat them as a sub-part of the mosfets they're attached to and keep them close together.
On the question of thermal vias - yes, you need them. And you need to keep a considerable area of copper below the IC so that the heat can go somewhere. Also, the power pad seems to be the main ground connection, you'll need to keep that in mind.
There's a few other things to consider:
- the VOUT portion is the main power rail for the USB connectors. You need a quite beefy connection there, placing the capacitors on the opposite side of the PCB needs some care taken. I don't know how many amps you plan to source simultaneously, but keep in mind that you need a significant trace width. If the capacitors are supposed to stay on the bottom side, you'll need plenty of vias to keep the inductance low.
- I didn't see straight and suggested to keep J3 where it is, but if you look at the ratsnets, it'll be even easier if you swap J3 and J4.
- Around the switching part of the boost converter, you'll need to think about keeping ground loops very tight. The copper area of the SW node should be kept small. Place L1 close to the IC pins and on the top side. The thing looks _huge_. Which component did you choose? Maybe you can find a different type that exchanges PCB area with height? But I'm not sure about the overall dimensions. Also, treat this area with care while routing traces on the bottom side, make sure to not cut or obstruct the ground loop of the boost converter part. There'll be high switching currents flowing, you need as low an impedance as you can get. It's a shame the chip vendor doesn't provide a layout suggestion.