Author Topic: Why am not able to get a grasp of PCB designing?  (Read 15761 times)

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Offline Rerouter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #125 on: December 05, 2019, 10:09:51 am »
left hand side, click the green filled in copper pour option,

right hand side, click essentially the same icon, go to the pcb and click, will ask you to select a layer, a net and edit any settings, once pressing OK

Continue drawing the shape of the pour (would recommend a course grid for this to make things easier), then either get to clicking on the starting point, or right click and select "close zone outline", once done it should auto-fill the pour.
 

Offline redgearTopic starter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #126 on: December 05, 2019, 10:21:46 am »
left hand side, click the green filled in copper pour option,

right hand side, click essentially the same icon, go to the pcb and click, will ask you to select a layer, a net and edit any settings, once pressing OK

Continue drawing the shape of the pour (would recommend a course grid for this to make things easier), then either get to clicking on the starting point, or right click and select "close zone outline", once done it should auto-fill the pour.
Thank You!
I followed exactly the same steps but, its still hatched.
 

Offline Rerouter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #127 on: December 05, 2019, 10:29:21 am »
And the files I sent you, does that have copper pours showing up correctly?
 

Offline redgearTopic starter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #128 on: December 05, 2019, 10:35:23 am »
And the files I sent you, does that have copper pours showing up correctly?
Yes! They show up correctly. I tried moving the TH components and refilling, it works too.
 

Offline jhpadjustable

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Re: Why am not able to get a grasp of PCB designing?
« Reply #129 on: December 05, 2019, 11:22:36 am »
to change how the pour appears, there is a green button on the left hand toolbar, it and the 2 beneath it control what a copper pour looks like, as its easier to lay things out with it hidden sometimes
I rarely do this unless I need to find some segment that got lost and is interfering with routing some other trace. For 2 layer layouts, usually I just set the transparency of my layers appropriately so that I can see enough of what's happening on the other side.
(Thanks for the left-drag vs. right drag thing. I never knew that. :) )

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edit: you can also change your trace width and grid while routing by right clicking
You can also use W/w and N/n once you have set trace widths, or q to enter trace/space numerically. It's a major lost opportunity that the "List hotkeys..." window is modal.

I followed exactly the same steps but, its still hatched.
If it's hatched, it's not connected to the net. If you're sure there are pads etc. centered in the polygon, open the polygon editor and make sure it's on the correct net.
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Offline redgearTopic starter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #130 on: December 06, 2019, 09:36:18 am »
@Rerouter thanks a lot for taking the time to design the layout.

I have few questions:

1) The design recommendation says the BAT+ and BAT- should be on the opposite ends of the PCB. You have them placed very close to each other.
Can I move the BAT- pad to the right side of the PCB and flip the Batter Protection circuit(they recommend the battery protection to be close to the BAT- to reduce copper impedance from BAT- to GND) to the bottom side? Can they be on different layers? Will punching 12 vias be enough? Do the traces connecting the R1 to BAT+ be fat?

2) Can I route all differential pairs(except j5), mosfet current sensing and low current traces to the back side? If it's ok to do that, I can place the mosfets near the usb ports.

3) What should be the width of traces that connect to VOUT of mosfets?

4) They recommend atleast 12 vias to be punched on VOUT, SW, B+, B-. Do vias on VOUT (A,B,C) connecting to mosfets count? Can I use free space on the board to punch vias for GND?

5) Do I need copper pour on top of the BAT+ and BAT- pads, shouldn't pads themselves be enough?

Thanks

EDIT: Added the layout by Rerouter
« Last Edit: December 06, 2019, 09:46:08 am by redgear »
 

Offline thinkfat

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Re: Why am not able to get a grasp of PCB designing?
« Reply #131 on: December 06, 2019, 10:31:05 am »
@Rerouter thanks a lot for taking the time to design the layout.

I have few questions:

1) The design recommendation says the BAT+ and BAT- should be on the opposite ends of the PCB. You have them placed very close to each other.
Can I move the BAT- pad to the right side of the PCB and flip the Batter Protection circuit(they recommend the battery protection to be close to the BAT- to reduce copper impedance from BAT- to GND) to the bottom side? Can they be on different layers? Will punching 12 vias be enough? Do the traces connecting the R1 to BAT+ be fat?
That is a safety measure if you plan to use bare Li-Ion or Li-Po battery cells without built-in protection circuit. Imagine the spark if the wires touch each other while you solder them to the board. Imagine you short the battery terminals with a solder blob.

What batteries were you planning to use, 18650 cells? If you use cells with built-in protection, you can put the BAT+/- where you want and you can also drop the protection circuit completely. If you plan to use bare cells, follow their advice for your own safety and of those who will use the device.

2) Can I route all differential pairs(except j5), mosfet current sensing and low current traces to the back side? If it's ok to do that, I can place the mosfets near the usb ports.
I'd keep the differential pairs where they are and only drop the mosfet current sensing and gate traces to the back side.

3) What should be the width of traces that connect to VOUT of mosfets?
That depends on what you want each individual port to source. The main VOUT trace should be at least 2mm (80mil) for your 4A maximum current. The traces from there to each mosfet could be weaker, depends on what the maximum current there will be. BTW, KiCAD has a built-in PCB calculator that can do trace width calculations.

4) They recommend atleast 12 vias to be punched on VOUT, SW, B+, B-. Do vias on VOUT (A,B,C) connecting to mosfets count? Can I use free space on the board to punch vias for GND?
That depends on how much current will flow through these vias. My own rule-of-thumb says 500mA is the maximum allowance for a single via. If you want to push 1A, put two.
Everybody likes gadgets. Until they try to make them.
 
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Offline thinkfat

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Re: Why am not able to get a grasp of PCB designing?
« Reply #132 on: December 06, 2019, 10:39:36 am »
BTW, how do you intend to charge the battery?
Everybody likes gadgets. Until they try to make them.
 

Offline redgearTopic starter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #133 on: December 06, 2019, 10:56:49 am »
What batteries were you planning to use, 18650 cells? If you use cells with built-in protection, you can put the BAT+/- where you want and you can also drop the protection circuit completely. If you plan to use bare cells, follow their advice for your own safety and of those who will use the device.
Yes, I am planning to use 18650s. And they don't come with built-in protection. Can I  flip the Battery Protection circuit(they recommend the battery protection to be close to the BAT- to reduce copper impedance from BAT- to GND) to the bottom side? Can they be on different layers? Will punching 12 vias be enough? Do the traces connecting the R1 to BAT+ need to be >80mils?

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I'd keep the differential pairs where they are and only drop the mosfet current sensing and gate traces to the back side.
Ok, but I still have to place 4 mosfets on the top layer, I got no space for them. Can I flip the mosfets to the bottom layer?

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That depends on what you want each individual port to source. The main VOUT trace should be at least 2mm (80mil) for your 4A maximum current. The traces from there to each mosfet could be weaker, depends on what the maximum current there will be. BTW, KiCAD has a built-in PCB calculator that can do trace width calculations.
The combined max output current will 4A  either through a single port(except micro USB) or all outputs combined. Low Voltage Direct charge mode is at 5V. From their datasheet:
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In non low voltage direct charge mode, when output voltage is lower than 6V, its current is up to 3A; When output voltage is higher than 6V, its power output is limited to 18W; When output voltage is 9V, its current is up to 2A; When output voltage is 12V, its current is up to 1.5A. In low voltage direct charge mode, its power outputisupto22.5W.

The max charging current will be 5A. This is what their datasheet says, but I cannot understand it. Idk what do they mean by charge current in input current and battery current.
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The charge current in input current varies with input voltage, while battery current is up to 5A. When input voltage is 5V, input charge current is set to 2Afor Micro-B and Lightning port, and 3Afor Type-C port. When input voltage is 9V, input charge current is set to 2A. When input voltage is 12V, input charge current is set to 1.5A.


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That depends on how much current will flow through these vias. My own rule-of-thumb says 500mA is the maximum allowance for a single via. If you want to push 1A, put two.
Ok, Say I need 6 vias on vout, placing vias any net that connects to vout is fine,right?

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BTW, how do you intend to charge the battery?
The USB connectors are bi-directional, acts as a source when sink is detected or acts as a sink when source is connected.

Thanks
« Last Edit: December 06, 2019, 10:59:49 am by redgear »
 

Offline Rerouter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #134 on: December 06, 2019, 11:54:55 am »
you can put the mosfets wherever you like, they don't even need to be next to the port, they can be closer to the micro,

As per Vias, just throw down as many as your compfortable with, the 500mA per via is not a bad rule of thumb,

As per exactly how to run the traces to the ports, get creative, same with the battery connection terminals, I just followed that as the files you gave me had them close to each other,
 

Offline redgearTopic starter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #135 on: December 10, 2019, 07:50:15 am »
UPDATE:

I have managed to route most of the components. I have also followed the recommendations given by the chip manufacturer. The only things left to route now are the GATE pads and VBUS pads from mosfets to ICs. I am not able to figure out a way to route it. :-BROKE

I am attaching the image.


Thanks

EDIT:

Managed to connect VCC network. Updating the image.
« Last Edit: December 10, 2019, 09:03:48 am by redgear »
 

Offline jhpadjustable

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Re: Why am not able to get a grasp of PCB designing?
« Reply #136 on: December 10, 2019, 07:19:25 pm »
Not intended to be an exhaustive review :) , but I see some variations on a couple of themes you might want to fix:

1. Use wide traces to carry appreciable current.
  • The #5 pins on the USB A ports need to carry current. Widen those traces up. Or better yet, move your vias closer to the ground pin. The shield pins don't need nearly as many vias as you are giving them, as they will not carry appreciable current. (Nor do you want them to. Should a shield pin/foot come loose due to wear and tear, it will play merry hell with your device.)
  • Likewise, the source leads on your MOSFETs are carrying the entire output current. Use a wide enough trace to handle it. The same goes for the VBUS caps. (VBUSB is good. Do this. But maybe turn VBUSB the other way to reduce distance and inductance to the absolute minimum.)
  • The runt traces to the vias on the VOUT caps look bad and increase EMI slightly. You can put the vias in the fill using the via tool instead of the route tool.
2. Low-current, low-speed traces can be routed together to reduce the fracturing of the ground plane. Try to keep the ground plane open and solid.
  • On port C, pins 3 and 9 (counting from the left) appear to be also quite low-speed enough to travel together. Route them on top to somewhere near pin 3, just to the left of the VBUSC trace, then drop them and take them over to the IC. Maybe you could even keep them on the top layer, or sink them all and bring its MOSFET to the top side.
  • The KEY nets are non-critical. They appear to be just dc logic input nets. You can route their traces closer together to keep the ground plane consolidated and gain more room to route other things. You can also take some of the vias off of the switch since they too will be carrying no appreciable current.
  • Don't interrupt the ground plane between the northmost VOUT-GND cap and the southerly ones.
  • The vias on DA2_(N|P) are poorly placed. Run the traces on the top layer alongside the DA1_(N|P) traces until you get to the connector, then sink them.
  • Consider bringing the VBUS cap for port A1 to the top. You can squeeze the KEY trace between the pads.
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Offline redgearTopic starter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #137 on: December 11, 2019, 06:03:11 am »
Not intended to be an exhaustive review :) , but I see some variations on a couple of themes you might want to fix:

1. Use wide traces to carry appreciable current.
  • The #5 pins on the USB A ports need to carry current. Widen those traces up. Or better yet, move your vias closer to the ground pin. The shield pins don't need nearly as many vias as you are giving them, as they will not carry appreciable current. (Nor do you want them to. Should a shield pin/foot come loose due to wear and tear, it will play merry hell with your device.)
The #5 pins are GND pins on USB A. Do I need to beef up the GND traces connecting them? I am removing the vias now.
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  • Likewise, the source leads on your MOSFETs are carrying the entire output current. Use a wide enough trace to handle it. The same goes for the VBUS caps. (VBUSB is good. Do this. But maybe turn VBUSB the other way to reduce distance and inductance to the absolute minimum.)
  • The runt traces to the vias on the VOUT caps look bad and increase EMI slightly. You can put the vias in the fill using the via tool instead of the route tool.
I am using a 2mm(78.74mils) trace for the source leads on MOSFETs, aren't they enough? I removed the traces on VOUT caps, instead I used a zone fill and punched vias directly on them. Do I need to follow the same for GND vias in all caps?
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2. Low-current, low-speed traces can be routed together to reduce the fracturing of the ground plane. Try to keep the ground plane open and solid.
But their recommendation say to punch vias on free space to strengthen the connection between the layers and to help in heat dissipation. By routing together, Do you mean reducing the clearance between adjacent traces and routing them as close as possible?
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  • On port C, pins 3 and 9 (counting from the left) appear to be also quite low-speed enough to travel together. Route them on top to somewhere near pin 3, just to the left of the VBUSC trace, then drop them and take them over to the IC. Maybe you could even keep them on the top layer, or sink them all and bring its MOSFET to the top side.
Ok, will try this.
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  • The KEY nets are non-critical. They appear to be just dc logic input nets. You can route their traces closer together to keep the ground plane consolidated and gain more room to route other things. You can also take some of the vias off of the switch since they too will be carrying no appreciable current.
Ok.
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  • Don't interrupt the ground plane between the northmost VOUT-GND cap and the southerly ones.
Can you name the caps?
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  • The vias on DA2_(N|P) are poorly placed. Run the traces on the top layer alongside the DA1_(N|P) traces until you get to the connector, then sink them.
  • Consider bringing the VBUS cap for port A1 to the top. You can squeeze the KEY trace between the pads.
Ok. Let me try.

Thanks.

@Rerouter Where you able to download the zip that I sent you over PM?
 

Offline jhpadjustable

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Re: Why am not able to get a grasp of PCB designing?
« Reply #138 on: December 11, 2019, 07:34:07 am »
The #5 pins are GND pins on USB A. Do I need to beef up the GND traces connecting them? I am removing the vias now.
Beefier and shorter. They're the return for the current flowing through the device and need to be at least as wide as the traces on the #1 pins. What you did for the #6 shield pins, you should be doing for the #5 pins instead. The shield pins are a much lesser concern.
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I am using a 2mm(78.74mils) trace for the source leads on MOSFETs, aren't they enough?
Looking at the MOSFET connected to VBUSA1 at the left, I see the drain trace is wide, which is good. The source trace connecting the two then heading east, which I presume is the big VOUTP bus, is still tiny.
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I removed the traces on VOUT caps, instead I used a zone fill and punched vias directly on them. Do I need to follow the same for GND vias in all caps?
It would be wise to connect all the power caps solidly to ground, as you have done for the four BAT-GND caps by the inductor.
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But their recommendation say to punch vias on free space to strengthen the connection between the layers and to help in heat dissipation. By routing together, Do you mean reducing the clearance between adjacent traces and routing them as close as possible?
Vias will help thermally just by being some metal, but would only help electrically if there's a ground fill on each layer to connect to, perhaps one that I'm not seeing because you turned it off for clarity for posting? (Aside, did you try setting the transparency of the copper layers to about 60%? I find that really helps me get a better idea of what's happening while laying out.)
Not necessarily reducing clearance, in the design rule sense, but yes, I suggest you run them closer together to keep the ground fill "traces" fat.
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Can you name the caps?
C9,C7,C11, I think, where the concern is that trace looping nearly to the right edge of the board and dividing the ground plane between as it comes back toward the chip and passes between two caps. The top silk got a bit muddy in the JPEG compression, and to be completely honest I didn't see it at first, sorry. :)
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Offline redgearTopic starter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #139 on: December 11, 2019, 10:44:37 am »
Beefier and shorter. They're the return for the current flowing through the device and need to be at least as wide as the traces on the #1 pins. What you did for the #6 shield pins, you should be doing for the #5 pins instead. The shield pins are a much lesser concern.
Ok.
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Looking at the MOSFET connected to VBUSA1 at the left, I see the drain trace is wide, which is good. The source trace connecting the two then heading east, which I presume is the big VOUTP bus, is still tiny.
VBUSA1 is connected to the source of Q4. The connection on drain is VOUTA1. They are connected to the sense resistors.
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It would be wise to connect all the power caps solidly to ground, as you have done for the four BAT-GND caps by the inductor.
They still have traces connecting the vias to GND pad.
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Vias will help thermally just by being some metal, but would only help electrically if there's a ground fill on each layer to connect to, perhaps one that I'm not seeing because you turned it off for clarity for posting? (Aside, did you try setting the transparency of the copper layers to about 60%? I find that really helps me get a better idea of what's happening while laying out.)
Yes, I have GND fill on the entire B.cu layer. I have made the layer transparent now.
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Not necessarily reducing clearance, in the design rule sense, but yes, I suggest you run them closer together to keep the ground fill "traces" fat.
Ok
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C9,C7,C11, I think, where the concern is that trace looping nearly to the right edge of the board and dividing the ground plane between as it comes back toward the chip and passes between two caps. The top silk got a bit muddy in the JPEG compression, and to be completely honest I didn't see it at first, sorry. :)
No prob. I don't get you. What do you mean by don't interrupt the ground plane between caps? Should I not run any traces under them on?

Thanks
 

Offline jhpadjustable

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Re: Why am not able to get a grasp of PCB designing?
« Reply #140 on: December 11, 2019, 07:29:53 pm »
VBUSA1 is connected to the source of Q4. The connection on drain is VOUTA1. They are connected to the sense resistors.
Okay, I was reading the board backwards, and/or these are weird MOSFETs with the source on the one-pin side where the drain customarily lives. Disregard.
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They still have traces connecting the vias to GND pad.
Probably fine, as long as they're wide.
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Yes, I have GND fill on the entire B.cu layer. I have made the layer transparent now.
I meant F.Cu, the red layer. If so, you're probably okay but it's a bit hard to visualize on the images.
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No prob. I don't get you. What do you mean by don't interrupt the ground plane between caps? Should I not run any traces under them on?
Light blue here:

Even if there's a ground fill on F.Cu that I'm not seeing on the image, the vias just north of the blue-marked area wouldn't be connected to much in your screencap. I've sketched an alternate route for the port C pins to the chip which keeps the B.Cu fill more intact. You could bump C7 and friends a bit further down to make room if you like.

Cheers!
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Offline redgearTopic starter

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Re: Why am not able to get a grasp of PCB designing?
« Reply #141 on: December 14, 2019, 05:07:59 am »
Do I need to connect both VBUSC or is it enough if I just run power through one? I couldn't find a way to connect the VOUT and GATE nets ona  2-layer board. So, I switched to a 4 layer design.
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