Electronics > Beginners
Why am not able to get a grasp of PCB designing?
redgear:
UPDATE:
I have managed to route most of the components. I have also followed the recommendations given by the chip manufacturer. The only things left to route now are the GATE pads and VBUS pads from mosfets to ICs. I am not able to figure out a way to route it. :-BROKE
I am attaching the image.
Thanks
EDIT:
Managed to connect VCC network. Updating the image.
jhpadjustable:
Not intended to be an exhaustive review :) , but I see some variations on a couple of themes you might want to fix:
1. Use wide traces to carry appreciable current.
* The #5 pins on the USB A ports need to carry current. Widen those traces up. Or better yet, move your vias closer to the ground pin. The shield pins don't need nearly as many vias as you are giving them, as they will not carry appreciable current. (Nor do you want them to. Should a shield pin/foot come loose due to wear and tear, it will play merry hell with your device.)
* Likewise, the source leads on your MOSFETs are carrying the entire output current. Use a wide enough trace to handle it. The same goes for the VBUS caps. (VBUSB is good. Do this. But maybe turn VBUSB the other way to reduce distance and inductance to the absolute minimum.)
* The runt traces to the vias on the VOUT caps look bad and increase EMI slightly. You can put the vias in the fill using the via tool instead of the route tool.2. Low-current, low-speed traces can be routed together to reduce the fracturing of the ground plane. Try to keep the ground plane open and solid.
* On port C, pins 3 and 9 (counting from the left) appear to be also quite low-speed enough to travel together. Route them on top to somewhere near pin 3, just to the left of the VBUSC trace, then drop them and take them over to the IC. Maybe you could even keep them on the top layer, or sink them all and bring its MOSFET to the top side.
* The KEY nets are non-critical. They appear to be just dc logic input nets. You can route their traces closer together to keep the ground plane consolidated and gain more room to route other things. You can also take some of the vias off of the switch since they too will be carrying no appreciable current.
* Don't interrupt the ground plane between the northmost VOUT-GND cap and the southerly ones.
* The vias on DA2_(N|P) are poorly placed. Run the traces on the top layer alongside the DA1_(N|P) traces until you get to the connector, then sink them.
* Consider bringing the VBUS cap for port A1 to the top. You can squeeze the KEY trace between the pads.
redgear:
--- Quote from: jhpadjustable on December 10, 2019, 07:19:25 pm ---Not intended to be an exhaustive review :) , but I see some variations on a couple of themes you might want to fix:
1. Use wide traces to carry appreciable current.
* The #5 pins on the USB A ports need to carry current. Widen those traces up. Or better yet, move your vias closer to the ground pin. The shield pins don't need nearly as many vias as you are giving them, as they will not carry appreciable current. (Nor do you want them to. Should a shield pin/foot come loose due to wear and tear, it will play merry hell with your device.)
--- End quote ---
The #5 pins are GND pins on USB A. Do I need to beef up the GND traces connecting them? I am removing the vias now.
--- Quote ---
* Likewise, the source leads on your MOSFETs are carrying the entire output current. Use a wide enough trace to handle it. The same goes for the VBUS caps. (VBUSB is good. Do this. But maybe turn VBUSB the other way to reduce distance and inductance to the absolute minimum.)
* The runt traces to the vias on the VOUT caps look bad and increase EMI slightly. You can put the vias in the fill using the via tool instead of the route tool.
--- End quote ---
I am using a 2mm(78.74mils) trace for the source leads on MOSFETs, aren't they enough? I removed the traces on VOUT caps, instead I used a zone fill and punched vias directly on them. Do I need to follow the same for GND vias in all caps?
--- Quote ---2. Low-current, low-speed traces can be routed together to reduce the fracturing of the ground plane. Try to keep the ground plane open and solid.
--- End quote ---
But their recommendation say to punch vias on free space to strengthen the connection between the layers and to help in heat dissipation. By routing together, Do you mean reducing the clearance between adjacent traces and routing them as close as possible?
--- Quote ---
* On port C, pins 3 and 9 (counting from the left) appear to be also quite low-speed enough to travel together. Route them on top to somewhere near pin 3, just to the left of the VBUSC trace, then drop them and take them over to the IC. Maybe you could even keep them on the top layer, or sink them all and bring its MOSFET to the top side.
--- End quote ---
Ok, will try this.
--- Quote ---
* The KEY nets are non-critical. They appear to be just dc logic input nets. You can route their traces closer together to keep the ground plane consolidated and gain more room to route other things. You can also take some of the vias off of the switch since they too will be carrying no appreciable current.
--- End quote ---
Ok.
--- Quote ---
* Don't interrupt the ground plane between the northmost VOUT-GND cap and the southerly ones.
--- End quote ---
Can you name the caps?
--- Quote ---
* The vias on DA2_(N|P) are poorly placed. Run the traces on the top layer alongside the DA1_(N|P) traces until you get to the connector, then sink them.
* Consider bringing the VBUS cap for port A1 to the top. You can squeeze the KEY trace between the pads.
--- End quote ---
Ok. Let me try.
Thanks.
@Rerouter Where you able to download the zip that I sent you over PM?
jhpadjustable:
--- Quote from: redgear on December 11, 2019, 06:03:11 am ---The #5 pins are GND pins on USB A. Do I need to beef up the GND traces connecting them? I am removing the vias now.
--- End quote ---
Beefier and shorter. They're the return for the current flowing through the device and need to be at least as wide as the traces on the #1 pins. What you did for the #6 shield pins, you should be doing for the #5 pins instead. The shield pins are a much lesser concern.
--- Quote ---I am using a 2mm(78.74mils) trace for the source leads on MOSFETs, aren't they enough?
--- End quote ---
Looking at the MOSFET connected to VBUSA1 at the left, I see the drain trace is wide, which is good. The source trace connecting the two then heading east, which I presume is the big VOUTP bus, is still tiny.
--- Quote ---I removed the traces on VOUT caps, instead I used a zone fill and punched vias directly on them. Do I need to follow the same for GND vias in all caps?
--- End quote ---
It would be wise to connect all the power caps solidly to ground, as you have done for the four BAT-GND caps by the inductor.
--- Quote ---But their recommendation say to punch vias on free space to strengthen the connection between the layers and to help in heat dissipation. By routing together, Do you mean reducing the clearance between adjacent traces and routing them as close as possible?
--- End quote ---
Vias will help thermally just by being some metal, but would only help electrically if there's a ground fill on each layer to connect to, perhaps one that I'm not seeing because you turned it off for clarity for posting? (Aside, did you try setting the transparency of the copper layers to about 60%? I find that really helps me get a better idea of what's happening while laying out.)
Not necessarily reducing clearance, in the design rule sense, but yes, I suggest you run them closer together to keep the ground fill "traces" fat.
--- Quote ---Can you name the caps?
--- End quote ---
C9,C7,C11, I think, where the concern is that trace looping nearly to the right edge of the board and dividing the ground plane between as it comes back toward the chip and passes between two caps. The top silk got a bit muddy in the JPEG compression, and to be completely honest I didn't see it at first, sorry. :)
redgear:
--- Quote from: jhpadjustable on December 11, 2019, 07:34:07 am ---Beefier and shorter. They're the return for the current flowing through the device and need to be at least as wide as the traces on the #1 pins. What you did for the #6 shield pins, you should be doing for the #5 pins instead. The shield pins are a much lesser concern.
--- End quote ---
Ok.
--- Quote ---Looking at the MOSFET connected to VBUSA1 at the left, I see the drain trace is wide, which is good. The source trace connecting the two then heading east, which I presume is the big VOUTP bus, is still tiny.
--- End quote ---
VBUSA1 is connected to the source of Q4. The connection on drain is VOUTA1. They are connected to the sense resistors.
--- Quote ---It would be wise to connect all the power caps solidly to ground, as you have done for the four BAT-GND caps by the inductor.
--- End quote ---
They still have traces connecting the vias to GND pad.
--- Quote ---Vias will help thermally just by being some metal, but would only help electrically if there's a ground fill on each layer to connect to, perhaps one that I'm not seeing because you turned it off for clarity for posting? (Aside, did you try setting the transparency of the copper layers to about 60%? I find that really helps me get a better idea of what's happening while laying out.)
--- End quote ---
Yes, I have GND fill on the entire B.cu layer. I have made the layer transparent now.
--- Quote ---Not necessarily reducing clearance, in the design rule sense, but yes, I suggest you run them closer together to keep the ground fill "traces" fat.
--- End quote ---
Ok
--- Quote ---C9,C7,C11, I think, where the concern is that trace looping nearly to the right edge of the board and dividing the ground plane between as it comes back toward the chip and passes between two caps. The top silk got a bit muddy in the JPEG compression, and to be completely honest I didn't see it at first, sorry. :)
--- End quote ---
No prob. I don't get you. What do you mean by don't interrupt the ground plane between caps? Should I not run any traces under them on?
Thanks
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