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Why am not able to get a grasp of PCB designing?

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jhpadjustable:

--- Quote from: redgear on December 11, 2019, 10:44:37 am ---VBUSA1 is connected to the source of Q4. The connection on drain is VOUTA1. They are connected to the sense resistors.

--- End quote ---
Okay, I was reading the board backwards, and/or these are weird MOSFETs with the source on the one-pin side where the drain customarily lives. Disregard.

--- Quote ---They still have traces connecting the vias to GND pad.

--- End quote ---
Probably fine, as long as they're wide.

--- Quote ---Yes, I have GND fill on the entire B.cu layer. I have made the layer transparent now.

--- End quote ---
I meant F.Cu, the red layer. If so, you're probably okay but it's a bit hard to visualize on the images.

--- Quote ---No prob. I don't get you. What do you mean by don't interrupt the ground plane between caps? Should I not run any traces under them on?

--- End quote ---
Light blue here:

Even if there's a ground fill on F.Cu that I'm not seeing on the image, the vias just north of the blue-marked area wouldn't be connected to much in your screencap. I've sketched an alternate route for the port C pins to the chip which keeps the B.Cu fill more intact. You could bump C7 and friends a bit further down to make room if you like.

Cheers!

redgear:
Do I need to connect both VBUSC or is it enough if I just run power through one? I couldn't find a way to connect the VOUT and GATE nets ona  2-layer board. So, I switched to a 4 layer design.

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