Electronics > Beginners

Why am not able to get a grasp of PCB designing?

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redgear:

--- Quote from: tautech on November 13, 2019, 10:14:19 am ---:)
It always is !
More layers if there is no other way but there are tricks like using bigger passives so to be able to route traces under them. Jumper wires and zero ohm links are other tricks.

Show us your efforts.

--- End quote ---

Thanks... Will see if I can use any of these.

NivagSwerdna:
I am assuming to you are using both sides of the board for traces?  Show us what you have got so far. From the datasheet it looks quite do-able with 2 layers.

redgear:

--- Quote from: NivagSwerdna on November 13, 2019, 12:21:25 pm ---I am assuming to you are using both sides of the board for traces?  Show us what you have got so far. From the datasheet it looks quite do-able with 2 layers.

--- End quote ---

Guess I made some progress. I have completely ignored the layout rules on the datasheet but it's now better than before. 



Here are the rules from the datasheet:

--- Quote ---The power and current of the chip work are relatively large, and the position of the capacitor on the VSYS network will affect the stability of the DCDC operation. Capacitors on the VSYS network need to be as close as possible to the IC's VSYS pin and EPAD, and copper is spread over a large area, adding more vias to reduce the current loop area between the capacitor and the IC, reducing parasitic parameters. The VSYS pins are distributed on both sides of the chip, requiring capacitors to be placed on the adjacent pins on both sides, and the VSYS pins on both sides are connected together by a wider (not less than 100 mil) copper on the PCB.

10mOhm sampling resistor:
The chip samples the current flowing through the 10mOhm resistor through the VSN and VSP pins to control the input charging current, output overcurrent protection, and output light-load shutdown. Therefore, when drawing the PCB, the wiring requirements for the VSN and VSP pins are relatively high. It is necessary to avoid the signals with large interference, and separately route to the inside of the two pads of the 10mOhm sampling resistor, which cannot be combined with VSYS and other currents. The path that flows through has any coincident traces. Although VSP and VSYS are the same network on the PCB, the traces of the pins must be separated separately. A 100nF filter capacitor is required on the VSN and VSP pins, respectively, as close as possible to the IC pin to enhance the immunity of the sampled signal.

Trace from 10mOhm sampling resistor to input and output MOS tube Application example:
VOUT1 is equipped with a mobile phone that does not support fast charging. The VOUT2 port is equipped with a mobile phone that supports fast charging. Since multiple ports are simultaneously output, the system can only output 5V and charge two mobile phones at the same time. When the mobile phone on VOUT1 is pulled out, or the power consumption is less than the set value, the system will close the VOUT1 output port and then only keep the VOUT2 port output. In this case, the system can automatically restore the VOUT2 port fast charge function to the mobile phone on the VOUT2 port. Perform fast charging. To achieve the above automatic recovery fast charge function, it is necessary to accurately detect the output current on the VOUT1 port. The output current on the VOUT1 port is implemented by detecting the voltage difference between the VSN and VOUT1 pins. The threshold condition for turning off the VOUT1 port is a voltage difference of less than 1.8mV. Therefore, when there is no current on VOUT1, no other current can flow through any trace from VSN to VOUT1. Otherwise, if a current flows, a voltage difference will be formed, which will be misjudged as the current flowing out of VOUT1. The same principle is used for other outputs. In summary, the PCB traces from 10mOhm to VOUT1, from 10mOhm to VOUT2, from 10mOhm to VIN. There are separate traces at 10mOhm, and any two currents that flow in the same direction cannot overlap. Otherwise, the auto-recovery fast charge function described on the “Application Example” will be invalid, and may sometimes be absent.

If the wrong layout causes the output current of VOUT1 and VOUT2 to have a 1 milliohm coincident trace, when there is a 2A current output on VOUT2, a 2mV differential will be generated on the coincident 1 milliohm trace. In this case, even if it is pulled out When the device on VOUT1 is removed, it is impossible to judge that the device on VOUT1 is unplugged, and the fast charge function of the VOUT2 output port cannot be restored. The current required to be connected to the VOUT2 output is less than 1.8A, and the voltage difference generated on the coincident 1mohm trace is less than 1.8mV for 16ms to automatically restore the fast charge function of the VOUT2 output.

--- End quote ---

What should be the trace length? For VSYS, VBAT, VOUT  and GND it should be more than 100 mils. What about the other traces? What should be the gap between them?

redgear:

--- Quote from: redgear on November 13, 2019, 02:45:50 pm --- (Attachment Link)

--- End quote ---

I feel routing this layout would be very difficult. What capacitors need to be really close to the IC? What capacitors can I afford to move to the other layer of the PCB(it's mostly unused). How do I create a pad to solder the battery connections?

The components with a NC flag is also populated on the board, I don't really want to use them should I remove them from the schematic or just leave the component unsoldered?

NivagSwerdna:
I'm not sure you are listening to the advice being given to you... for example if you rotated the chip 90 clockwise the lines would be better organised radially.

Start drawing some traces and see what happens.

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