Mmm, sorry, that circuit is pretty ugly and I don't mean the diode version.
What it is is a divide-by-6 counter with carry out.
What it's doing is detecting the counter is 6 (that means Q4 high and Q2 high) then sending a reset to the counter.
The CD4510B has an asynchronous reset.
That means that when the reset (or parallel load) happens it immediately jumps.
That means that the time when the counter is 6 is just a fraction of a second.
It counts: zero ..... one ..... two ..... three ..... four ..... five ..... six-oh-no-six-is-bad!-reset-quickly-zero ..... one
The problem is, when it gets the reset command what if Q2 resets before Q4?
Then the logic that is driving the reset will relax and Q4 might not get reset.
Who knows how well/reliably this circuit will work.
In ye olde days when we did this kind of thing we used a monostable (one-shot) to make sure that the reset pulse was long enough.
Also, the carry out on your circuit goes low on the counter=5.
U2.4 is not doing anything useful since it inhibits only on counter=6 which means the counter=5 condition is already failed.
In any case, with the asynchronous reset, who can know exactly how this circuit reacts.
The thing to do is to use something modern with a synchronous reset (maybe a 74HCT163?).
Then you can detect counter=5 (Q4 is high, Q1 is high) and use that as both your carry out and your synchronous reset.