Why is mosfet turning off slowly?

[T3sl4co1l]

I'm just trying to understand is if the mosfet is taking time to charge the Cds is is actually in the linear region during that point of time?

The MOSFET is off and not conducting.

However, the fact that current is still flowing into the drain terminal (charging the capacitance), does mean energy is being transferred.

Where does it go?

When the transistor later turns on, that energy is burned by the transistor.  This gives "hard" switching loss (i.e., when it turns on, the transistor has to discharge capacitances in the circuit).

If you had something else discharge the drain voltage down to zero, then turn on the transistor, there would be no energy loss.  Well, unless the thing doing the discharge is lossy -- but the point is, it wouldn't be lost in the transistor itself!

An example of this would be a resonant load, like a class E amplifier: when you turn off the transistor, the inductive load causes the voltage to swing high, well above the supply voltage.  It swings up too far, and then it swings back down too far as well.  When the drain voltage swings all the way back down below GND, the MOSFET body diode turns on, clamping it.  The transistor can then be turned on again, with zero switching loss.  (The transistor can be turned on any time the drain voltage remains low.  A class E converter for switching supply duty might be designed to have a 20% "dwell" time, so the timing can be quite relaxed.  An RF amplifier, in class E, would simply be adjusted for best results; there's no time to really think about voltages and currents, from moment to moment, in an RF amplifier.)

Tim

[ZeroResistance]

I'm just trying to understand is if the mosfet is taking time to charge the Cds is is actually in the linear region during that point of time?

The MOSFET is off and not conducting.

However, the fact that current is still flowing into the drain terminal (charging the capacitance), does mean energy is being transferred.

Where does it go?

When the transistor later turns on, that energy is burned by the transistor.  This gives "hard" switching loss (i.e., when it turns on, the transistor has to discharge capacitances in the circuit).

If you had something else discharge the drain voltage down to zero, then turn on the transistor, there would be no energy loss.  Well, unless the thing doing the discharge is lossy -- but the point is, it wouldn't be lost in the transistor itself!

An example of this would be a resonant load, like a class E amplifier: when you turn off the transistor, the inductive load causes the voltage to swing high, well above the supply voltage.  It swings up too far, and then it swings back down too far as well.  When the drain voltage swings all the way back down below GND, the MOSFET body diode turns on, clamping it.  The transistor can then be turned on again, with zero switching loss.  (The transistor can be turned on any time the drain voltage remains low.  A class E converter for switching supply duty might be designed to have a 20% "dwell" time, so the timing can be quite relaxed.  An RF amplifier, in class E, would simply be adjusted for best results; there's no time to really think about voltages and currents, from moment to moment, in an RF amplifier.)

Tim

Excellent post Tim!!
Looks like you know The mosfet inside out...
Just to sum it up when I give a adequate voltage to the gate, a current starts flowing into the drain, but the mosfet is still in the off state, now this current charges the Cds capacitor, after the capacitor is full charged, the mosfet now starts switching on I mean the drain source resistor will now be set by the Vgs voltage and that amount of current will be flowing into the drain only limited by the load.

I know it may not be as simple as that but is the the way things go inside the mosfet...

[HackedFridgeMagnet]

This app note is quite useful.

Design And Application Guide
For High Speed MOSFET Gate Drive Circuits
By Laszlo Balogh

[suicidaleggroll]

Excellent post Tim!!
Looks like you know The mosfet inside out...
Just to sum it up when I give a adequate voltage to the gate, a current starts flowing into the drain, but the mosfet is still in the off state, now this current charges the Cds capacitor, after the capacitor is full charged, the mosfet now starts switching on I mean the drain source resistor will now be set by the Vgs voltage and that amount of current will be flowing into the drain only limited by the load.

I know it may not be as simple as that but is the the way things go inside the mosfet...

Your gate driver is not the one charging up Cds, the 1k (now 100R) "load" resistor is.  Just look at the name, "Cds", that is the capacitance between the drain and source, the gate has nothing to do with it.  When your gate goes low and the transistor turns off, the 100R load resistor wants to raise the drain voltage up to Vcc immediately, but it can't, because there's essentially a capacitor sitting between the mosfet's drain and source (ground) that is currently discharged.  It takes time for your load resistor to charge up that capacitance and bring the drain up to Vcc.  The smaller the load resistance, the more current can flow into the drain and charge it up, and the faster the drain voltage will rise after the mosfet has been turned off.

[TheoB]

Since you want to drive an inductive load, make sure you add a diode over the inductor! Switching on will be easy as the current will increase with a rate of Vbat/L until is stabilizes at Vbat/Rl (the resistance of the coil). When you switch off, the current needs to continue and will go via the diode. The current will lower at a rate of Vdiode/L until it reaches zero. Your drain voltage will switch very fast from 0V to Vbat+Vdiode and might show some ringing as the diode might not be fast enough to start conducting etc. This can potentially destroy your mos.

[T3sl4co1l]

Excellent post Tim!!
Looks like you know The mosfet inside out...
Just to sum it up when I give a adequate voltage to the gate, a current starts flowing into the drain, but the mosfet is still in the off state, now this current charges the Cds capacitor, after the capacitor is full charged, the mosfet now starts switching on I mean the drain source resistor will now be set by the Vgs voltage and that amount of current will be flowing into the drain only limited by the load.

The MOSFET is "on" whenever the (internal) gate voltage is "on": above Vgs(th).

(The internal gate voltage isn't exactly the pin voltage, because there is some delay, on account of the internal gate resistance, and gate capacitances.)

As soon as you see Vds begin to drop, is when the transistor is "on", at least somewhat.

Remember that "on-ness" is kind of a dubious thing, because it's not a binary case.  There are varying degrees of "on".  When Vds > Rds(on) * I_L (i.e., above the resistive saturation region), more gate voltage simply draws causes more Id!  This is why the drain voltage bends downward, on the falling edge: the gate voltage is still rising, so the rate at which the drain voltage falls, increases, discharging that capacitance faster and faster.  Until it can't discharge any more, and the switch is saturated.

In saturation, "on-ness" is a bit easier to define: the relationship between Vgs and Id no longer holds, so as long as Vgs is more than enough to do the job, it can be said to be "on" or "fully saturated".

Tim

[ZeroResistance]

Your gate driver is not the one charging up Cds, the 1k (now 100R) "load" resistor is.  Just look at the name, "Cds", that is the capacitance between the drain and source, the gate has nothing to do with it.  When your gate goes low and the transistor turns off, the 100R load resistor wants to raise the drain voltage up to Vcc immediately, but it can't, because there's essentially a capacitor sitting between the mosfet's drain and source (ground) that is currently discharged.  It takes time for your load resistor to charge up that capacitance and bring the drain up to Vcc.  The smaller the load resistance, the more current can flow into the drain and charge it up, and the faster the drain voltage will rise after the mosfet has been turned off.

Well said suicidaleggroll!! what an amazing explanation, after reading your answer I can probably understand what was going on in the cirucuit!!

Since you want to drive an inductive load, make sure you add a diode over the inductor! Switching on will be easy as the current will increase with a rate of Vbat/L until is stabilizes at Vbat/Rl (the resistance of the coil). When you switch off, the current needs to continue and will go via the diode. The current will lower at a rate of Vdiode/L until it reaches zero. Your drain voltage will switch very fast from 0V to Vbat+Vdiode and might show some ringing as the diode might not be fast enough to start conducting etc. This can potentially destroy your mos.

Good point you make there Theob, I will be surely following your advice.


Finally can anyone explain what are those tiny negative going valleys that show up in Hero999's simulation and in some oscillograms that I posted earlier.

[T3sl4co1l]

Finally can anyone explain what are those tiny negative going valleys that show up in Hero999's simulation and in some oscillograms that I posted earlier.

Consider the effect of Cgd

Tim

[TheoB]

Finally can anyone explain what are those tiny negative going valleys that show up in Hero999's simulation and in some oscillograms that I posted earlier.

Indeed the Cgd. Your gate is being discharged to remove the channel (and switch off the device). As soon as the gate voltage reaches Vth (the threshold) the impedance on the drain increases from Rds(=fraction of a Ohm) to Rload. But you keep discharging the gate to zero volt. The voltage ramp from Vth to zero volt (while the mos is off) is simply seen at the drain because of the gate drain capacitance. The peak value thus never exceeds Vth. But it can be lower as there is normally also some capacitance on the drain from the load. So you get capacitive division.

[Zero999]

Reading again: I understand it was the MOSFET's drain-source capacitance which was holding the charge when it it went open circuit, which was responsible for the slow rise time.

You could use the most perfect drive circuit in the world, but it won't discharge the MOSFET's internal drain-source capacitance, if the impedance of the load is too high. See simulation attached, which shows the MOSFET driven with a 10V square wave with 1ns rise/fall times and a 10R gate resistor.

Excellent deduction and simulation Hero999 

What would those small negative going sections be caused by?!

The datasheet states that the Vgs Threshold of the IRF540 is 4V max for (Vds = Vgs) and Id = 250uA so probably I'm too close to that region since finally I want to use the mosfet with Id of between 1A to 2A.

I'm just trying to understand is if the mosfet is taking time to charge the Cds is is actually in the linear region during that point of time?

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. In real life there will also be inductance in the wiring but it isn't simulated.

And I made a mistake in my wording of my previous post. It's the drain source capacitance being charged via the load, not holding the charge. As others have said above, when the MOSFET switches off, the tiny capacitance in parallel with the drain and source charges up, thus passing current and causing a voltage drop across the load resistor. The lower the value of the load resistor, the faster the drain-source capacitor will charge and the sharper the rising edge will be.

[TheoB]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

[HackedFridgeMagnet]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

But doesn't overshoot imply a 2nd order system, therefore with inductance as well as capacitance?

[T3sl4co1l]

It's preshoot, not overshoot.  And it's in the wrong direction!  Take a closer look, check the time scale, and waggle your glasses. 

Tim

[suicidaleggroll]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

But doesn't overshoot imply a 2nd order system, therefore with inductance as well as capacitance?

Think of it like this:

The FET is on, source is 0V, drain is shorted to the source at ~0V, gate is 5V (or whatever it is).  Now you go to turn the FET off, so you start lowering the gate voltage, and therefore Vgs.  As Vgs drops, Rds starts to rise, but slowly at first...the drain will stay shorted to the source for a while.  A bit later, now your gate is down close to Vgs(th), and Rds starts to rapidly rise.  The drain is being cut off from the source, but due to Cds its voltage doesn't rise immediately.  The drain is still ~0V, but it's pretty much cut off from the source now and is just waiting for the load to charge it up.  BUT you're not done with the gate, you're only at ~Vgs(th) and are still dropping, you still have another 2-3V to go.  Cgd (the capacitance between gate and drain) wants to keep the drain the same ~3V below the gate that it already is, so as you continue to lower the gate voltage, Cgd tries to drag the drain down with it.  It's fighting against Cds (trying to hold the drain at ~0V) AND the load (trying to charge the drain up to Vcc), but if the conditions are right Cgd can somewhat overpower them and cause the drain to dip slightly below 0V before you're done lowering the gate voltage and the load finally gets to work charging up Cds.

Of course the same thing can happen when you go to turn on the FET as well.  The drain is up at Vcc, say 10V, the gate is at 0V, the source is at 0V.  Cds is charged up to 10V and Cgd is charged up to 10V.  Now you start to lift the gate.  Until the gate hits Vgs(th) and the drain starts to conduct to the source, the drain is still isolated, so Cgd tries to push the drain to track the gate.  Raise the gate 1V, Cgd wants to push the drain up 1V to maintain the same 10V it's been charged to.  Of course Cds is trying to keep it steady, and the load is trying to keep it at Vcc, but the end result is you can get a small spike in drain voltage before the gate hits Vgs(th) and the drain starts to conduct to the source.

[xavier60]

While the Gate voltage is dropping below 4V, drive current through the Gate/Drain capacitance exceeds the current through the 1K load resistor causing the brief negative voltage pulse at the Drain.

[tatus1969]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

+1. The gate driver pulls down the gate, and the gate capacitance is abruptly discharged. The other side of that gate capacitor is tied to the drainsource, which "sees" this abrupt discharge current. Impedance plays a role here, which means, yes, inductance, plus resistance. You need a thick short GND connection to the DC bus capacitor(s) to minimize this. The second capacitor, the Miller capacitance, goes from gate to sourcedrain. This is second effect responsible for the negative going dip, this capacitor "copies" the negative gate voltage transition to the source as soon as the transistor goes into high impedance state. Probably the dominant effect.
EDIT: wtf? still mixing this up after 30 years

[tatus1969]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

But doesn't overshoot imply a 2nd order system, therefore with inductance as well as capacitance?

Think of it like this:

The FET is on, source is 0V, drain is shorted to the source at ~0V, gate is 5V (or whatever it is).  Now you go to turn the FET off, so you start lowering the gate voltage, and therefore Vgs.  As Vgs drops, Rds starts to rise, but slowly at first...the drain will stay shorted to the source for a while.  A bit later, now your gate is down close to Vgs(th), and Rds starts to rapidly rise.  The drain is being cut off from the source, but due to Cds its voltage doesn't rise immediately.  The drain is still ~0V, but it's pretty much cut off from the source now and is just waiting for the load to charge it up.  BUT you're not done with the gate, you're only at ~Vgs(th) and are still dropping, you still have another 2-3V to go.  Cgd (the capacitance between gate and drain) wants to keep the drain the same ~3V below the gate that it already is, so as you continue to lower the gate voltage, Cgd tries to drag the drain down with it.  It's fighting against Cds (trying to hold the drain at ~0V) AND the load (trying to charge the drain up to Vcc), but if the conditions are right Cgd can somewhat overpower them and cause the drain to dip slightly below 0V before you're done lowering the gate voltage and the load finally gets to work charging up Cds.

Of course the same thing can happen when you go to turn on the FET as well.  The drain is up at Vcc, say 10V, the gate is at 0V, the source is at 0V.  Cds is charged up to 10V and Cgd is charged up to 10V.  Now you start to lift the gate.  Until the gate hits Vgs(th) and the drain starts to conduct to the source, the drain is still isolated, so Cgd tries to push the drain to track the gate.  Raise the gate 1V, Cgd wants to push the drain up 1V to maintain the same 10V it's been charged to.  Of course Cds is trying to keep it steady, and the load is trying to keep it at Vcc, but the end result is you can get a small spike in drain voltage before the gate hits Vgs(th) and the drain starts to conduct to the source.

explaining what I meant in my last post in a much clearer way, I should have read to the end first...

[tatus1969]

your first post suggests that you want to drive a LED, this rises some questions for me
- what type of LED is it? Is it a simple combination of a resistor and the LED, or is it some integrated module?
- why do you need such a high PWM frequency?
- why is it a problem that the rise time is slow when you replace the LED with a 1k resistor?

[tehtehteh]

I don't want to hijack this thread, can some of you experts please also look at my thread, I think I am having a similar problem as here, but I don't have the luxury of lowering the resistor to drain to get a better signal

[ZeroResistance]

your first post suggests that you want to drive a LED, this rises some questions for me
- what type of LED is it? Is it a simple combination of a resistor and the LED, or is it some integrated module?
- why do you need such a high PWM frequency?
- why is it a problem that the rise time is slow when you replace the LED with a 1k resistor?

1. No I don't want to drive a LED it was just a reference circuit that I found on the web so I started testing the circuit with a 1K load.
2. My first reaction to the mosfet switching off slowly was it is spending too much time in the linear region and I wanted to put that right before I loaded the mosfet with some amps. I didn't know these capacitance business at that time.

[Zero999]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

But doesn't overshoot imply a 2nd order system, therefore with inductance as well as capacitance?

Think of it like this:

The FET is on, source is 0V, drain is shorted to the source at ~0V, gate is 5V (or whatever it is).  Now you go to turn the FET off, so you start lowering the gate voltage, and therefore Vgs.  As Vgs drops, Rds starts to rise, but slowly at first...the drain will stay shorted to the source for a while.  A bit later, now your gate is down close to Vgs(th), and Rds starts to rapidly rise.  The drain is being cut off from the source, but due to Cds its voltage doesn't rise immediately.  The drain is still ~0V, but it's pretty much cut off from the source now and is just waiting for the load to charge it up.  BUT you're not done with the gate, you're only at ~Vgs(th) and are still dropping, you still have another 2-3V to go.  Cgd (the capacitance between gate and drain) wants to keep the drain the same ~3V below the gate that it already is, so as you continue to lower the gate voltage, Cgd tries to drag the drain down with it.  It's fighting against Cds (trying to hold the drain at ~0V) AND the load (trying to charge the drain up to Vcc), but if the conditions are right Cgd can somewhat overpower them and cause the drain to dip slightly below 0V before you're done lowering the gate voltage and the load finally gets to work charging up Cds.

Of course the same thing can happen when you go to turn on the FET as well.  The drain is up at Vcc, say 10V, the gate is at 0V, the source is at 0V.  Cds is charged up to 10V and Cgd is charged up to 10V.  Now you start to lift the gate.  Until the gate hits Vgs(th) and the drain starts to conduct to the source, the drain is still isolated, so Cgd tries to push the drain to track the gate.  Raise the gate 1V, Cgd wants to push the drain up 1V to maintain the same 10V it's been charged to.  Of course Cds is trying to keep it steady, and the load is trying to keep it at Vcc, but the end result is you can get a small spike in drain voltage before the gate hits Vgs(th) and the drain starts to conduct to the source.

Oh, I understand now. I was too quick to blame the inductance. It's clearly the effect of the drain-gate capacitance being charged up and the positive side of the capacitor connected to 0V, when the MOSFET turns on. And of course, the reverse will happen when the MOSFET turns off, causing the spikes, above the positive supply.

[ZeroResistance]

Oh, I understand now. I was too quick to blame the inductance. It's clearly the effect of the drain-gate capacitance being charged up and the positive side of the capacitor connected to 0V, when the MOSFET turns on. And of course, the reverse will happen when the MOSFET turns off, causing the spikes, above the positive supply.

Can anything be done for these, I mean to prevent those spikes and the negative dips?

[tatus1969]

your first post suggests that you want to drive a LED, this rises some questions for me
- what type of LED is it? Is it a simple combination of a resistor and the LED, or is it some integrated module?
- why do you need such a high PWM frequency?
- why is it a problem that the rise time is slow when you replace the LED with a 1k resistor?

1. No I don't want to drive a LED it was just a reference circuit that I found on the web so I started testing the circuit with a 1K load.
2. My first reaction to the mosfet switching off slowly was it is spending too much time in the linear region and I wanted to put that right before I loaded the mosfet with some amps. I didn't know these capacitance business at that time.

ok. if your load is (even slightly) inductive, then you may run into problems with ringing. i have posted a tested circuit that switches a wirewound power resistor that is connected through a cable. i deliberately had to slow down switching speed to compensate for excessive ringing from lead and part inductance. pwm freq is 2khz here, it cannot go higher without excessive efficiency loss. go for push-pull config otherwise. heres the link, first picture on the right: https://www.eevblog.com/forum/projects/variable-frequency-drive-design/msg1087549/#msg1087549

[ZeroResistance]

ok. if your load is (even slightly) inductive, then you may run into problems with ringing. i have posted a tested circuit that switches a wirewound power resistor that is connected through a cable. i deliberately had to slow down switching speed to compensate for excessive ringing from lead and part inductance. pwm freq is 2khz here, it cannot go higher without excessive efficiency loss. go for push-pull config otherwise. heres the link, first picture on the right: https://www.eevblog.com/forum/projects/variable-frequency-drive-design/msg1087549/#msg1087549

Thanks for the tip tatus... are you referring to the totem-pole output that goes to 'U_INT" by any chance?

[Zero999]

Oh, I understand now. I was too quick to blame the inductance. It's clearly the effect of the drain-gate capacitance being charged up and the positive side of the capacitor connected to 0V, when the MOSFET turns on. And of course, the reverse will happen when the MOSFET turns off, causing the spikes, above the positive supply.

Can anything be done for these, I mean to prevent those spikes and the negative dips?

Yes. The easiest way to minimise them is to reduce the switching speed which can be done by increasing the gate resistor. A MOSFET with a lower gate charge will also help but the on resistance will quite likely be higher.