Why it is mush harder to start a low frequency crystal oscillating?

[ali6x944]

Hello everyone,
I was playing around with crystal oscillators lately and I observed something quite strange...
Low frequency crystals like 32.786khz crystals are much harder to get oscillating than higher frequency crystal 4Mhz< ...
So I want to know why it is so, and how to fix this problem...
Please help

[Rerouter]

To my knowledge a crystal will start sooner if there is A, a source of noise nearby, and B, there is a small mismatch between the capacitors,

Also you do need to respect the crystals drive level or your just saturating out the oscillations,

[danadak]

What circuit/schematic are you using ?


This might help -


http://www.generalplus.com/doc/an/AN0129-32768_Crystal_Oscillation_Application_Note-16.pdf


Regards, Dana.

[Audioguru]

Ali with the pi in the pie, how mush money do you have?

[Cervisia]

A low-frequency crystal is larger, and requires more energy to move. (As an analogy, compare a bass speaker and a tweeter.)

[Kleinstein]

The 32 kHz crystals are often quite tiny and thus have a relatively high impedance. This is because they are often used for low power application like a real time clock. In a relatively large circuit parasitic capacitance can be a problem, as this might already be too much. Common crystal circuits are often shown for the high frequencies - so they don't fit that well for the low frequency. Otherwise the 32 kHz crystal should not be more difficult in principle. If you only have jelly bean OP, it's likely much easier than with a 10 MHz one.

[ali6x944]

And why it is easier to use CMOS inverters compared to TTL inverters in use in pierce oscillators?
Dose it have to do the input current of the gate or something else?

[Gyro]

A low-frequency crystal is larger, and requires more energy to move. (As an analogy, compare a bass speaker and a tweeter.)

On the contrary, low frequency crystals tend to have much higher mechanical Q that high frequency ones, most 32kHz crystals are constructed as a quartz tuning fork. They can only safely handle much lower drive levels than high frequency ones, often in the uW range.

I suspect the reason that they start slower is simply that it takes more time for a given number of cycles of ramp-up that it would on a much higher frequency one (assuming they both need about the same number of cycles).

[Gyro]

And why it is easier to use CMOS inverters compared to TTL inverters in use in pierce oscillators?
Dose it have to do the input current of the gate or something else?

Yes, much higher input impedance means much lower loading (damping) of the crystal.

[David Hess]

Series resistance for tuning fork style 32kHz crystals is almost 3 orders magnitude higher (30 kilohms) than the series resistance for typical AT cut crystals (40 to 180 ohms).

[David Hess]

And why it is easier to use CMOS inverters compared to TTL inverters in use in pierce oscillators?
Dose it have to do the input current of the gate or something else?

I think this is just because CMOS gates have higher gain.  If you use higher gain TTL logic like AS (advanced schottky), then they work better in Pierce (parrallel resonant) oscillilators.

The converse can also be a problem.  Stacking two CMOS gates to make a series resonant oscillator is more difficult than with TTL because the extra gain makes the CMOS gates more difficult to bias into their linear region without spurious oscillation.

I think National Semiconductor had a good application note on the subject of gate oscillators but it might be difficult to find now.

Update: The lower input impedance of TTL gates probably figures into it by attenuating the input signal with the crystal's series resistance.  As a practical matter I think the issue is just lower gain for whatever reason.  If you want a reliable crystal oscillator, use a transistor instead of a gate.

[ali6x944]

Thanks everyone for all the help

[Benta]

One thing to be careful of with 32 kHz crystals is, that they are very easily overdriven.
They need much lower drive power than AT-cut crystals.

[ali6x944]

One thing to be careful of with 32 kHz crystals is, that they are very easily overdriven.
They need much lower drive power than AT-cut crystals.

Could this cause permanent damage to the crystal? As it not oscillating? dose it cause frequency drift due to internal loss?

[David Hess]

One thing to be careful of with 32 kHz crystals is, that they are very easily overdriven.
They need much lower drive power than AT-cut crystals.

Could this cause permanent damage to the crystal? As it not oscillating? dose it cause frequency drift due to internal loss?

It can cause both high drift and failure.

[amyk]

One thing to be careful of with 32 kHz crystals is, that they are very easily overdriven.
They need much lower drive power than AT-cut crystals.

Could this cause permanent damage to the crystal? As it not oscillating? dose it cause frequency drift due to internal loss?

Drive the crystal too hard and something like this happens.

[ali6x944]

Mmmm.....
This means when using the 32kHz crystal I should add a in series a resistor of around 1.5M to not overloaded the crystal?

[Benta]

I suggest you do a web search for RTC and see from the datasheets how the oscillator is made.

[ali6x944]

I suggest you do a web search for RTC and see from the datasheets how the oscillator is made.

I did for the DS1307 and Intersil X1243  , it dose show some interesting things... most of the RTC ic's use a Pierce oscillator, and contain internally 12pf, 68pf capacitors and a two high value resistors, one in series and the other in parallel...

[orolo]

The small signal model of a resonator is a series RLC circuit, shunted by a small (1-5pF) capacitance. The first thing to notice is that series resistance drastically decreases with frequency: a 10MHz crystal typically has a series resistance under 10 Ohms, while for a 32KHz crystal is on the order of 20-30K.

The first time I studied crystal resonators, these figures made wonder. I had experience trying to build inductors with a Q over 100, and it was a fight between getting very low series resistance (fractions of an ohm) and maximizing energy storage. How can a crystal have a Q>10000 with a series resistance of 20K or more  ? Energy storage must be huge!

Looking at the first crystal datasheet my search engine throws at me, we have a crystal with series resistance 35K max, and series (motional) capacitance 1-4fF. Let us assume C=2fF. Using the classic formula for series resonance, that means a series inductance of 11795 Henries. The Q factor at resonance is easy to compute, it's around Q=70000.

So, a low frequency crystal has a huge series resistance (\$ k\Omega\$) and, in order to keep tremendous selectivity, it also has huge reactances, both inductive (kH) and capacitive (fF). These things are hard to move. This means that a fast startup oscillator will need high gain.

High series resistance introduces another problem. Placing a low impedance near such a crystal will spoil the resonator: the loaded Q will sink. If you use bjts and want quality, you'll probably wind up with two stages, buffer + (inverting) amplifier. FETs won't need buffering, but they have lower gain, so with just one stage you may get a lazy oscillator.

That said, the king of low component count crystal oscillators is FET Colpitts. Pierce is better in all other respects, including drive level and easy control of load capacitance. So, how do you build a basic Colpitts circuit for testing?

Computing the small signal model for a FET, and then simulating, I found this to work:



The circuit has an aceptable load capacitance (should be around 10-12pF, considering parasitics), the crystal is driven under 1uW (about 850nW in simulation), and is pretty low power. However, in the transient simulation it takes about 300ms to start up. The 20MEG resistor is very important: if it's reduced below 10MEG, the oscillator starts to lose swing. The gain is also rather insensible to FET transconductance, but not so the load capacitance: for the values given, the FET and caps give a negative resistance of -250K and a load capacitance of 8.6pF for a transconductance of 100uS. If the transconductance rises to 1000uS, the negative resistance is -2.5MEG, but the load capacitance drops to 6.6pF. So to fine tune load capacitance, C3 should be a trimcap in the range 8-15pF or so.

A discrete Pierce is a serious project: the caps load the crystal (with little loss) quite a bit, so a lot of gain is needed. Maybe it's better to use ICs for a Pierce amp.