Why are we mixing data connections in SDRAM?

[Bat91]

Hello,

Recently, looking through the schematics of finished modules from ST, I noticed an interesting connection of data signals (DQx) between the microprocessor (STM32MP135) and SDRAM (MT41K512M16VRP-107 IT). I would like to find out why this was mixed up like this and how it affects the operation or configuration of the RAM.

[calmtron]

Probably done to simplify routing of the PCB. The SDRAM does not care about the order of the bits during normal use, it is possible one has to consider it during setup.

[ataradov]

It is absolutely for routing reasons. Just keep in mind that you can only mix them within the same byte (DQ0-DQ7 and DQ8-DQ15).

[mikeselectricstuff]

Probably done to simplify routing of the PCB. The SDRAM does not care about the order of the bits during normal use, it is possible one has to consider it during setup.

From memory, SDRAM only cares about some of the address lines during setup

[Bat91]

Thank you for all your responses. I couldn't find information anywhere regarding whether the order of the bits is important and whether this is configured in some way in STM32 (this is where I will have to read up)

[BrianHG]

Careful:  The first 8 bits, bits 0-7 can have swaps within themselves.  Same for the second 8 bits 8 through 15.  You cannot swap bits between the first and second 8 bit banks as there is a write mask for selectively writing individual bytes at each memory address.