Hey All,
Was looking into the MC14076B, a 4-Bit D-Type Register with Three-State Outputs.
Under the function table it states in clear text that if either one or both of the output disable pins is high, this puts the outputs into HighZ.
Yet, the logic diagram provided seems to contradict this:
Both inputs are hooked into a nor gate, which in tern is connected to a buffer with what seems like a inverted input. Two inversion would then put a high on the buffers if there is a high present on the data disable inputs?
Am I misreading something here? Is there an inconsistency in the data sheet?