Will this overvoltage circuit LATCH?

[LooseJunkHater]

Background: Refer to image 1: Essentially the MAX6397 is an overvoltage-protection I.C which DOES NOT offer latching options (and other I.C's that offer latching do not support a 72v input voltage; only lower). The REG pin provides a 3.3v @ 100ma output, no matter the input voltage. SET is used to set the overvoltage protection. When the overvoltage condition is triggered, the output FET is pulled LOW, stopping power from going to the power output. The SHDN pin when pulled low also pulls the FET low, HOWEVER the REG pin continues to output 3.3v.

The 74AUP2G132DC is a simple dual-NAND Gate I.C, which I configured into an S-R Latch.

The circuit: Refer to image 2: Switch-2 is used to enable/disable the "latching" function. The SR latch should be triggered when the MAX6397 Gate pin is pulled LOW. Q3 would pull the SHDN pin LOW.

Question: Does this circuit make sense? Will it work to essentially add a latching function to the MAX6397? I think if I used a simple dual-NOR gate I.C (again configured as an SR latch) then I could avoid using Q4?

Datasheets:
https://www.analog.com/media/en/technical-documentation/data-sheets/MAX6397-MAX6398.pdf
https://www.mouser.ca/datasheet/2/916/74AUP2G132-1541831.pdf

[LooseJunkHater]

So I've been trying to simulate the circuit in Falstad but I honestly can't tell if Falstad is messing up or if my "latching" circuit is the problem?

https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0l3BWK0BsB2AnADgEwI5gMw6SFZYQKUgKQ0CmAtGGAFBhUhqQAsIPGFCApCBQujho1WAdxAoedHljoI0olVHYJC4QijoocfMDzSSjfCVISsAZvISiwQlE-6aM4aEhiQcrITc-AoeqmCSynQQdJCsAEqOQvpYSSCE+lBZiuCxWTC2DhgYkcogxZLcfDlgPsj+rADmuZCpVS1tJPmBwWpC7QT9vODdAB7CWK7+5cMGSELGIACKrOMIWLooKKkomegQfIsATvQAzvQALqsTomh8GMNmaPwgiytrPLo8OjRoSN+iV58c5XACywhc8kWWEEUKsrx8rHBIn4sJholhEkRcna+Eqs1aWhxwwQODaJIiRIhQjxXBJZKpKMs1JoJUZkNJ5L4tLichRYhZnPZGKE-LKvJZPDKFX44tkNEpCnC+Ks8qoKt+Q1VABkQtVNJ9IppoiALkcAK70KRxU4Kiw5dpKrIQOwAQwANudWLb1WFNX6TW7PfRrk4vAK3NVii9KQBRAB2roARu76AB6AAiAEtTsnU960jxIW5kttnSAg16jna-b6ndF4NoII7ocXFtYkLZqywy1FwC4djkG3ACxFNH1wGTVAzAx6veMInhUbowIQwEpYSZJAm8+ns7mUyHbT3Un3VwYAyNK0f+2WnRFQvWr3OQ7qWF0z61T8aRmbLdb5RPOkt2IYCqSA+8BzAiVTHMWVUhcMopVSGCzEiWFYNKFDALQ1EhEwmgZxwuChXPVQ2VQuDmQInliMkWkyMI7C5EY0j9GVcD2NZSRGIMbDwQIgUOFJPCshwREBNw6iEBE5ksVsBdjGqGTJwIfh1heY4zkua4OB4SI7nAJwlDQZ5Dj4d49EgVw-j0Mh5DQU8gRAEFdIQfT5GmDgLzmeRnJWIJohwUD2hcELhhiLRmhcUJQq2PhzDyOIHEQ08ylSsCajqPwAkSMdpwQtd6JnbIG3yZBbEC-sP00ICz26FKp39fL5ByLxal8WAAhYrj72IQdYm0FcuKE3CBWsVRWG7Xqal6uDhxHYl9UMOC+xgnBYT6hl6yaPQfLg1d1AcyRBvGNBIVMuhHIStAvmcgA5ABBe6M10wgMCQdQIFMMp1GqB6AHl4lYIA

On the left is my NAND-based SR latch (which doesn't appear to ever latch). On the right is the NOR-based SR latch, which appears to work as expected?

[LooseJunkHater]

Here's only the working NOR variety of latch. Why is the 10k resistor at SET needed?? I have no idea.

https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0l3BWK0BsB2AnADgEwI5gMw6SFZYQKUgKQ0CmAtGGAFBgKHiEp0o4AWcALQ4Q-IXTFIErAE7gwKLCAFY6LZeIF0N8VgA9wOPKoxcwhMHQEYUq4yACiAOwCGAIwA29APQARAEsAZ08fVmDFLRQdYxjtXXAQADM3L2D6VgAZRRJVdXBIcnzEiAAXOQBXehooVgB3KJU0SCEwHGIQFskGpoS+7rrGsBExATVwGJVxlUhekdEzewWxibnh0aXhRYQcWfnN3ZVLXhoMMXXtsQkrs4uDnfPuU6Oh57pXk4-2t6+79-ERTqAFlbrZlghdlspNBZKCVuJBOBIdckTDZEZLJA0Ko0BA-iIhEIkXJ6BkyoZkQIxmg2ghTiIccShABFSmWKziU4nLgoFBcZkgcnshDUwFiDinXhIexItmEFrGTqDJTK1pJXSsADmk3iKr5QlEiTmyUmExmZua6tiYFhyEgOFYACVjAVPoIVK9EjbjchZAqNO0bAVNNMQ1A6qb2m60Ms9nwbeA7TAHfMeAmNMQVDFNRwLOmtgjwRGLjR5jg7P1LHt+nNMYQMEhY-iLbGiSAkQA5ADyTu13BrCFjA89p01Cmr2ZtWZow70+kioZKALUpRAFWqEVdHxr0Y+c4jqXSmSAA

[pqass]

A number of issues in no particular order WRT your 2.png schematic...

U4 GATE output is limited to IN+10V so Q4 gate could be destroyed if U4 IN is >20V over U4 REG output (3.3V).

Don't leave logic gate inputs "flapping in the breeze" (SPST switch open or FET in off position); should put a pullup/down to whichever is the idle state for the SR-latch.

SR-latches have an invalid state; both inputs are H, or both L for NOR-SR, NAND-SR, respectively. Make sure that never occurs by only ever triggering one SR-latch input at one time.

NAND SR-latch inputs use H as the idle state; whereby L will change its state.
NOR SR-latch inputs use L as the idle state; whereby H will change its state.
If Q4 is conducting (due to U4 GATE going to GND) then it tries to pull the NAND SR-latch to H (U4 REG through 10K) but this won't change anything for a NAND SR-latch.  If /SHDN is L then Q4 can never be on unless its gate is below GND.  Therefore, the NAND SR-latch can never be set.

How is Q4 ever on; ie. its gate grounded? Datasheet only says U4 "GATE falls to OUT within 100ns". I couldn't find a mention of the U4 GATE voltage WRT GND when chip is in the overvoltage state.  Why not just use a resistor divider from Q2 source (aka. U4 OUT). In overvoltage state, that should be 0V (L) to trigger (set NAND SR-latch) U1 1A. In a non-overvoltage state, it'll be a fraction of the output (clamped to U4 REG; 3.3V).

How is the SR-latch guaranteed to be in the correct state upon power-up?

I'm assuming SW1 and SW2 are momentary types and, in the case of SW1, is to manually reset the latch; not sure about SW2 purpose.  I think if U4 POK (with 100K pullup to REG) is connected to U1 2B, then upon power-up the NAND SR-latch would be put in the reset state by default. I'm assuming there is a lag while REG is below <3.3V POK is GNDed giving a momentary L to U1 2B as it's powering up. 

For both set and reset triggers, I think you should use an RC network to just give a pulse in order to avoid an SR-latch invalid state when either input is kept triggered (ie. when U4 GATE remains in overvoltage state AND user keeps reset button pressed).  However, it may be easier to prevent the momentary reset button triggering the SR-latch while the set (U1 1A) is in the L state (via N-FET gate to U1 1A and drain to left leg SW1 and source to /SHDN); since you shouldn't be allowed to reset if U4 is still in an overvoltage state.

See working simulation of what I have in mind here.

[LooseJunkHater]

Wow thanks for the amazing and thorough reply!

U4 GATE output is limited to IN+10V so Q4 gate could be destroyed if U4 IN is >20V over U4 REG output (3.3V).

I don't quite understand what this means? Does that mean if the input voltage is 60v, it WOULD destroy Q4 because the gate would see 70v? Or is it because the +10v at the P-MOS would destroy it (as the P-MOS expects to only see negative voltages)?

How is the SR-latch guaranteed to be in the correct state upon power-up?

I don't expect it to; I was thinking to simply flip SW1 to trigger it into the correct state (essentially waiting for OVP).

Do you recommend me going with the S-R latch to add latching to the MAX6397 circuit, or should I go another route?

[LooseJunkHater]

See working simulation of what I have in mind here.

Okay so is this essentially what I would need to do to enable latching of the MAX6397?

[Solder_Junkie]

I have built many over Voltage protection boards (they also protect for over current) using an LTC4368, the device is tiny, but the circuit is less complex than the one using the MAX IC. Would it suffice for your purpose? I use a switch on surge add-on, which is Cx and Rx in the attached diagram.

https://www.analog.com/en/products/ltc4368.html#product-overview

There is a model of the LTC4368 in LT Spice for computer testing too.

SJ

[LooseJunkHater]

I have built many over Voltage protection boards (they also protect for over current) using an LTC4368, the device is tiny, but the circuit is less complex than the one using the MAX IC. Would it suffice for your purpose? I use a switch on surge add-on, which is Cx and Rx in the attached diagram.

https://www.analog.com/en/products/ltc4368.html#product-overview

There is a model of the LTC4368 in LT Spice for computer testing too.

SJ

I've looked into the LTC4368 but I got a bunch of the MAX6397 for cheap from a Newark sale hence wanting to use them (and because the LTC4368 is quite expensive). I'll likely use the LM5069-1 (latching variety; cheaper than the LTC4368) in the future but I personally don't even want to use that part due to the higher BOM (shunt resistor, timing capacitors, additional resistors), as all I care about is latching, OVP, and the I.C to handle greater than 72v input voltages.

[Terry Bites]

Simple SR latches can't be relied upon to start up in a known state.
That can cramp your style.
For a couple of cents more I'd use a D-type with power on reset eg a CD4013

[pqass]

I don't quite understand what this means? Does that mean if the input voltage is 60v, it WOULD destroy Q4 because the gate would see 70v? Or is it because the +10v at the P-MOS would destroy it (as the P-MOS expects to only see negative voltages)?

WRT 2.png...

The MAX6397 will produce a voltage on its GATE output that is +10V above IN in order to turn on Q2; an N-FET.
With a greater than +10V IN and SW2 closed, Q4 gate to source voltage would exceed the usual ±20 Vgs maximum allowed (see device specific datasheet). 
Regardless if Q2 is on, there is a resistor to RES (+3.3V) which may still be way below the GATE output (couldn't find in the datasheet GATE to GND voltage in OV state, although not sure about "GATE pulls low when SHDN is low." on page 7).
So, it's not because Q4 P-FET saw positive voltages. It's that it went above its Vgs maximum (at least when Q2 is on).

I don't expect it to; I was thinking to simply flip SW1 to trigger it into the correct state (essentially waiting for OVP).

Do you recommend me going with the S-R latch to add latching to the MAX6397 circuit, or should I go another route?

Upon power up, if a particular state isn't assured then the SR-latch may default to shutting down the MAX6397 even though there was no overvoltage condition yet. 
ie. may intermittently require a reset button press on power up.  This can be annoying.

Do I recommend an SR-latch? 
It depends on your... costs and number of components (minimum complexity). I think it can be made to work. See below.

Okay so is this essentially what I would need to do to enable latching of the MAX6397?

Unfortunately, my previous simulation isn't quite right. If Q2 state is off (in overvoltage state; switch is open), that keeps the SET line low in the SR-latch.
The circuit should really only trigger a momentary low (on switch open) since an extended low condition will keep the reset switch from doing its job (via N-FET blocking the reset switch).
Forcing a reset won't work either since that breaks the two simultaneous low inputs rule (invalid state for NAND SR-latches).

I've since modified the simulation to add an RC network and it seems to work. See below for a screenshot of the moment Q2 is open; sending a momentary low to the SET line.  When the reset momentary is pressed, SR-latch is reset and the SHDN goes high resulting in Q2 closing if the overvoltage state has passed (or Q2 will close when it eventually passes).  Although, there is a tiny chance of invalid SR-latch state if the reset button is held while an overvoltage state occurs.

Notice the 12V zener protecting the N-FET gate from exceeding Vgs due to post Q2 voltage (OUT).

Although it needs testing, I think the RESET line of the SR-latch can be directly connected to the POK output to assure the SR-latch is properly reset on power up.  Page 7 of datasheet: "POK: Open-Drain Output. POK remains low until REG exceeds 92.5% or 87.5% of REG nominal output voltage."