I can see it being automated within a decade or so.
i'm getting a bowl of popcorn. this will get interesting. especially since exactly THAT has been said the last 40 years ... I'm wondering when that 10 years span exactly starts ....
Autorouters are getting more and more intelligent. You can fan-out a BGA with a click in newer versions of Altium.
That is NOT autorouting. That is just fan-out. Fan-out is an easy problem to tackle. Even then ... in lots of cases it doesn't work. Try placing and routing all the decoupling caps on let's say a 688 pin BGA processor ( not that big of a beast these days ... ) and then click that fan-out button and see where you end up. Plenty of pins unreachable...
Back to the 'hooman' to make pathways for the 'clickety thing' to complet the fan out... no 'hooman', no solution...
Auto routers can route a board.
Autorouters are nothing more than a bunch of algorithms. It take a 'hooman' in the drivers seat , setting up all the criteria , selecting the algorithms , in which order to launch them , and to clean up the initial placement and preroutes ( like power , decoupling , series and parallel termination , local power switchers and regulators etc ... ) before you can launch the router.
Length tuning and other optimization is not that difficult to do.
obviously you have never done a 'serious' board like a graphics card , computer motherboard, or even something smaller like let's say a DDR4 memory stick ... Cramming all that stuff in the available space is a nightmare. you assume it is easy because you are thinking in terms of 'unlimited' space. Wait till they tell you : you have the size of a 2 postage stamps. cram it in ...
Component placement can be automated.
Really sherlock ? You find me a placement tool that can optimally place all the parts around a switching regulator. Bulk and output caps , coil , and power pathways. Let's just start there. PLace the parts and properly route them with the proper widths. Collapse all current loops and optimize for density. Wake me when you found such a tool. Then we'll tackle something slightly more complex.
Digital simulation is a solved problem
Quote the Late Widlar. Digital ? any idiot can count to one ...
It is so easy to say : it's digital. one and zero. except on the board these things are voltages , that switch , that become waves and fields that interact with the routing and all the 'analog cruft' on the board. Good luck finding that 'one' in all the noise around the trace that needs to carry those electrons. Ever tried to properly run USB3 , Sata , or other 'common' buses these days ? you cant do that on a single layer with 8 mil traces ... and no the computers can;t figure it out by them selves either. It takes a 'hooman' to figure out what layer stack will be used , calculated the required widths and clearances per layer and feed all that information in to the router. and then the computer can place a trace of proper width and length between point a and b. There is not a single PCB layout tool where you can simply feed it the layer thicknesses and the required impedances (through the schematic) and it will do the calculations for you. Needs 'hooman'. And if the layer stack needs adapting for whatever reason ( manufacturing, materials shortage, other busses with other requirements on same board ) guess who gets to do all the 'fun work again' : the trained descendant-of-ape ...
A a matter of fact : coming up with a layer stack itself is a very complex issue. you need thick copper for all the massive currents modern cpu's eat , and at the same time you want thin copper to be able to route all the high speed stuff...
high end solutions are capable of providing useful feedback.
Ah , the good old 'let's run it. look at it ,tweak it some more and re-run it.. approach. Typical manager (aka poo-flinging baboon type) speak.
How many run cycles will be needed before it works ? 10 ? 20 ? 100 ? 1000 ? Sure the computer is fast. But then the 'hooman' needs to check the end rsult of the run , tweak the setup. That is where most time is lost. If you approach it without know-how and rely on this mechanism you end up with total time ( computer + hooman ) orders of magnitude longer than an experienced 'hooman'.
So it is not unconceivable to set up a machine learning algorithm to learn placement and routing.
Quick , someone throw oodles of money at this and get very rich .. or the laughing stock of the industry ...
You would still need the engineer though. To set up the board size, connectors, schematic, footprints, general guides to steer the AI.
First sensible thing you said so far... And this is where most of the time is already spent in the first place.
One of the complex boards i did was going to attempt the 'specctra' autorouter. Had a hired specialist in the field to do the runs. Everything was set up: worked with the GPU maker to do the initial power distribution and other stuff. Everything was ready to go. Only the memories and gigabit lanes between the GPU's were going to be tackled by Specctra. All rules were loaded. Everything else was placed and routed.
First run : aborted after 30 minutes. Not enough routing channels. Specctra could not complete because it could not find enough space to throw down all the tracks.
So the hoomans (two) spend 2 days following the advice of the expert and shuffle via's on a grid so that there would be plenty of horizontal and vertical pathways.
Second run : still no enough pathways. Congestion in area's around memories. Can we use different pinout ?
Hooman : are you effing insane ? I can't change the memory pinout. The chip is like that . Standard Samsung part. GPU vendor uses same on their boards. They already tuned their GPU pinout for easy layout to the memories.
So we studied the congestion map , moved decoupling , moved via's created more lanes in the congested area's.
third run. now congestion in other area's.
15 or 16 runs with every time 2 to 3 days to move stuff around ( sometimes by 1 or 2 mils , converting a via here and there to a laser via to shave another mil or 2 so there was room for one more trace )
Spent 2 months playing this tag game. 2 layout engineers and another expert driving Specctra. It finally completed. The layout looked like a plate of spaghetti, projectile vomited into a pcb. Sure the traces all met impedance , length and diff length criteria, but half busses plowed straight underneath the switching inductors, and so many via's were shot that the ground plane was swiss cheese. Yes there was coupled copper underneath the traces, but everywhere else it was snot. A power analysis showed the copper was so shredded it couldn't even handle the return currents for the power of the GPU... we had to add 2 more planes just for that.
So 2 more power planes and 2 more routing layers later , bringing the board to a 16 layer now, we Specctra again. Marginal improvement but it completed this time.
As a side project we had 2 other engineers do the routing by hand (only the specctra portion). They finished in 4 days , length tuning and all. And got away with a 12 layer board.
We talked to the GPU maker about this. They looked at us and laughed.. Could have told you that....
Their layout engineers did graphics boards on 8 layers in 2 weeks. By hand. They had experience doing that stuff for years.
We did it on 12 layers in 4 weeks ( we had 4 gpu's interconnected with a bunch of other stuff , double complexity ). With less experience in such demanding interconnects.
The autorouter took 3 people during 2 months pushing and shoving a 80% routed board to make enough room for the router to 'vomit' its traces everywhere, without even understanding that it can't route a PCI-x underneath the magnetics of a switcher !
SPECCTRA :
Stupid
Program,
Expert in
Creating
Crappy
Traces and
Routing
Aborts.
We didn't even bother to produce that board ... the hand routed one worked first time right.
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