Electronics > Beginners
Wounded in Combat: Attacking DIY SMPS + Linear PSU Overshoot Under Load
<< < (3/3)
Mechatrommer:
i think i've found the problem. its Mr Murphy (the devil) came to have a peek a poke at me. while turning the board up and down, placing probes here and there, i didnt notice that Vrfs trimpot was accidentally turned so low, that there is not enough headroom for linear stage drop (i guess) hence opamp cant control it properly, thats why the opamp output skyrocketted earlier, due to this inadequacy, and darlington's Vemitter just followed the Vcollector swing mimicking 0% PSRR. with enough headroom, everything work back to normal. except there are still a bit of ringing inherent to every smps switching, but thats a different bit to tackle, for now the overshoot disappeared and its in acceptable region now. thanks guys for looking. this is just a waste of time for careless stupidity :palm:

here are the (reduced size to better see the overall) snapshots of different Vss+ level (cyan) and its effect on the linear regulated output VO+ (blue). left to right top to bottom numbered 1-4 (increasing Vss+ level) just look how nasty and hard the opamp output (purple) tried to stabilize things in snapshot 1 to no success... poor uA741... btw, time and break is a good healing potion... fwiw...


coppercone2:
people often add series resistors to trim pots to prevent then from operating in bad conditions you might want to update your circuit, its a easy way to blow something up
Mechatrommer:

--- Quote from: coppercone2 on January 15, 2019, 02:50:00 pm ---people often add series resistors to trim pots to prevent then from operating in bad conditions you might want to update your circuit, its a easy way to blow something up

--- End quote ---
looking at Vrfs trimpot, there is no real harm if the trimpot accidentally turned to max low or max high, there is 4.7Kohm high impedance protecting it. the worst case is the poor output performance as we saw here, or there will be too much (Vrfs - Vref), too high Vss+ and hotter linear stage, even if Vss+ maxed out to Vcc+ (in case of burnt short smps stage), this is how it was working in psu1e (earlier version 1) without smps pre-regulation feature. in fact, this later version psu1g can be made like how version 1 was working, ie depopulating (disabling) smps components and just shorting Vss+ node to Vcc+. the version 1 blown after years of service.fwiw.
David Hess:

--- Quote from: Mechatrommer on January 14, 2019, 11:41:20 pm ---i dont understand how darlington went into saturation when its in emitter follower mode.
--- End quote ---

When Vss is low, the operational amplifier drives the base of the Darlington pass transistor hard to raise the output which will never happen.  This leads to the pass transistor and drive transistor in this case being saturated.


--- Quote ---i've read class a,b,ab amplifier several times i thought i understand them but when some people talked about them i felt like clueless its like something big i've missed. for what i know, when the PSU is under load, it will be in class b mode, full conduction so to speak in quadrant I area.
--- End quote ---

That would be class-a but what we have here is class-b because there is a 1.2 volt voltage difference or "dead zone" between the bases of the driver circuit.  The output of the operational amplifier has to transition through this 1.2 volts before the output current from the driver reverses.  A class-a design would replace the lower PNP transistor with a resistor or current sink so that the output of the driver always follows the output of the operational amplifier.  A class-ab design would make both transistors of the driver always conduct at least a little bit so there is no "dead zone" for the operational amplifier to slew through to control the output.

Note that the design example below has this same problem to come extent when switching between constant voltage and constant current modes.


--- Quote ---but well, whats certain, is i need to learn more about transistor behaviour esp under transient mode, and its slew rate or sort of propagation delay or internal capacitance and what not. thanks for the advice.
--- End quote ---

Most of the problems here are just caused by the large dead zone in the class-b driver and allowing the output pass transistor to saturate.  Integrated linear regulators often include anti-saturation circuits to prevent exactly this sort of problem.  A bench power supply might disable the output by zeroing the reference until the input voltage to the pass transistor is sufficient.

The example shown below handles this problem in two ways:

1. During startup, Q15 and Q115 directly clamp the outputs of the operational amplifiers until their supply voltages are high enough for proper operation.  This is especially important in this case because during startup, the common mode input voltage of reference operational amplifiers U35 and U135 and voltage control operational amplifiers U45 and U145 is violated.  All operational amplifiers in this design are 741s or 301As.
2. Reference circuit VR25/Q25/Q30 ramps up slower than and is dependent on the supply voltage.  When the output is disabled, it is the reference which is shorted and C34 controls its rise when it is enabled.
Navigation
Message Index
Previous page
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod