Nothing wrong with a modular approach per se, but this schematic is a real pain to read like that. It is essentially the antithesis of a vintage Marantz receiver schematic (which also is very hard to follow but for exactly the opposite reasons - the optimum would be somewhere in the middle).
sorry i tried to cramp all those in one single sheet. but its actually a very simple circuit, not like other fully discrete transistors based linear regulator solution around here, i have to rotate head right and left to see where a transistor goes, its just my incompetence in transistor level design... when they tried to combat mV or uV of noises, i tried to combat V level of overshoot here

Anyway... you didn't say what your testing conditions were (nor does your scope make it obvious where the 0 V level was for all the traces), but I guess these overshoots occur after removing the load, right?
sorry i didnt see what you dont see, i was typing too much trying to explain it in the OP until i forgot what is what. 0V level is the same for all channels, you can see 0V for CH1, thats the same 0V level overlapped behind for CH2-4, except different V/div scale (you can see at the bottom of every capture)
the capture/test is fully under load. 1A of load, using my diy constant current load. i checked current draw within the constant load its ok, its unrelated to the overshoot figure/shape. it recovered as it should be when overshoot or undershoot occured (see last attachment). when the circuit is not under load, the overshoot/ringing is very minimized or none at all.
Also, your supply has no way of bringing the output down actively - current can only flow out but never back in. So when a load is being removed, the output transistor is still saturated and its base charge has nowhere much to go, and all the loop can do is pull base charge out of the first transistor.... maybe even make the output stage AB push-pull. The "pull" half could be substantially weaker, of course...
the circuit has active pull, see description below...
Also consider going discrete rather than integrated Darlington, which would give you access to the internal nodes.
as i said, i'm incompetent in transistor level design. i know few transistors based PSU here (amspire's iirc is one of them), but i just dont understand how every bjt works and what their purpose. try to ask them i think is like a kid asking every single part in automotive, maybe will bore many big guys people...
Might explain why your output is not fond of capacitive loading either.
i agree its not as robust and as stable as other PSU design, but 1V overshoot is just specifically unacceptable, this should be easy to tame i guess by most expert around here, its not like taming mV of spike, so thats why i published my query. earlier i put big capacitor 1000uF on the Vout, the 39 ohm pull down resistor (R6) is smoking like not so crazy, but its an unnecessary waste of power during idle, so i reduced capacitance to 10uF and its stable for now. but just in case end user will put capacitive loading on the output, i've reduced pull down resistor power as well (increase resistance) to 220 ohm.
BTW, your approach of transistor "back up" is just about completely broken. For one thing, you will have random current sharing between one TIP122 and the TIP142, and then transistors have a habit of failing short rather than open.
they are not meant to work together, either use a pair of TIP122s, or a single TIP142. i just provided the footprint in case i want to use TIP142 (but both TIP122 must be removed with redundant balancing power resistor R8, otherwise i guess some smoke will emerged)
What's the theory of operation for the tracking circuit?
tracking means, both +Ve and -ve rail will have same magnitude with a single potentiometer control, ie single voltage reference to control +Ve and -ve rail. the SMPS voltage output that feed linear regulator is set (adjustable) to be slightly higher 1 - 6 or so volt than the linear regulated output (VO+) but lets look at +Ve rail only for now to avoid further confusion.
Why does it apparently involve a µA741 misused as a comparator? Is there no way it can be done in a linear fashion?
there is no opamp (uA741) is configured as comparator, every one of them has feedback from output voltage they are meant to control, in 5-6X gain configuration (since voltage control is 5-6X than TL431 reference, 2.5V max translates to 2.5 x 5 or 6 = 12 - 15V output max.
Have you simulated any of this beforehand?
no, iirc. i dont trust simulation will reflect reality as i think i dont have every part model available in a sim, and i'm no sim (script) expert either. i will use sim for new topology/concept that i've never done before, but only rough estimate of performance and stability analysis, i dont expect them to match reality 100%. this topology in the OP has been working in circuit version 1, so i dont think sim is necessary. moving to "real world" performance is the stage i'm currently at. but maybe i'll consider SIMing it next time with this SMPS (spike and overshoot) addition.
Is your buck regulator circuit pre-tested?
its working as it should in my current circuit.

its just the switching will propagate into linear output stage, its like the linear stage has 0% PSRR for a moment.
You sure you can't spare one 1N4148 to go between the bases of 3904/3906 at least?
i'm not sure why, can you explain?
let me run through it for you and others fwiw... in step by step.
the heart of this PSU (brought from version 1, except with added active pull down) is darlington emitter follower controlled by opamp feedback from output voltage divided by 5 on its inverting input and reference voltage on its non inverting input. as pictured below. i really dont know how to explain this any simpler, since in eevblog level, anyone who is eligible to give an advice, will quickly recognize this. its a very simple thing in the universe, not like many transistors upside down topology that makes my brain hurt.
just notice, the opamp and darlington are feed from different power rails, VCC+ unregulated input voltage ±20V (going to ±15V or ±10V during loaded event, bigger input capacitor tank will improve 50Hz sag C1 and C2 in complete sch leftmost topmost) for opamp for maximum swing control and pre-regulation output VSS+ will power darlington and push pull driver. VSS+ may vary from 20V - 1V depending on Vout setting (15V down to virtually 0V). thats why there are clamp diodes on the push pull base. you can see the active pull Q5 (BC516) and weak pull 220 ohm resistor R6 are there in case of overshoot during idle operation (unloaded), during loaded event this pull mechanism should stay idle (pull is done by the external load) and not in the picture i forgot to edit, is 10uF output capacitor and protection diode. (D4, C7 in complete schematic in OP, rightmost)

whats important not in the picture above is (1) VCC+ (2) Vref (3) VSS+ lets go VCC+ first. picture below, the battery symbol is connectors to mains 50Hz transformer 20Vac output, a smaller one, and then setup to give ±20V in voltage doubler config. done, thats easy.

VCC+ will go to 2.2Kohm and TL431 for main 2.5V voltage reference. across the 2.5V reference is 10Kohm trimpot, this is the user interface to control output voltage VO+. from 0V to 2.5V, multiplied by 6 will be 0 - 15V output. the trimpot voltage level is buffered by opamp uA741. due to i sensed unstability, i've added 10ohm and 4.7nF (can be any value i guess but not too big) on the output and become Vref, the main control for smps voltage level, linear output level for both +ve and -ve rail. any question ask, any complaint shoot. do not hesitate


VSS+ smps pre-regulation output will get its reference from this (picture below) Vrfs. a jellybean simple 2 diodes voltage increase, and another (internal) small trimpot across them to set how much excess SMPS compared to VO+ voltage, set by designer's desire (which is me) once and done, after everything are ok. its 0 - 1.4V increase 5X multiplication in control system will reflect in 0 - 7V bigger than linear output. please note i should buffer this Vrfs since its high impedance, it was my careless mistake, now my -ve rail is not symmetric, but leave that alone for now, thats another thing to tackle later (or maybe i have to respin pcb making with the better updated design)

now we go to the new part, smps pre-regulation get its command from Vrfs reference... opamp will sense VSS+ output, in case less than Vrfs x 5.65, it will give less than 1.25V output (mc34063 smps internal reference, refer to datasheet) to CII compare pin and will force 34063 to turned on (low on SWC due to connection to SWE and resulting p-mosfet AO3401 to turned on) this should be pretty simple to experienced people, just how optimum is this setup i'm not sure, all i know is it works as i intended it to be. the end result, is smps regulation on VSS+ to be a little higher than VO+ (Vref x 5.65 or so), so less Vce on linear power element, less power dissipation, less heat less risk of damage, thats its purpose.

man, i'm not sure if its worth explaining it all this long since there seems to be less interest with lack of respond after 100+ of view, or maybe spaghetti schematics

but sorry guys i think i prefer this way for compact view all in one page for now, i hate many pages when designing things, altium is slow you know. but maybe noobs like me may benefit from this? fwiw...