You nearly have what's called a Vbe multiplier circuit: in the both-switches-on state, Q3 should be well saturated, and Q4's collector voltage is set by R4-R6, less Q2 Vbe. Normally, a Vbe multiplier has a voltage divider from collector to base to emitter; here, the B-E resistor is infinite, so the multiplication of Vbe will be small, about 1, which means the collector voltage should be pretty low, nearly saturated.
But... that assumes Q2 doesn't deliver current, but it will (let me guess, both transistors get rather hot?). As a result, Q4 gets overpowered to some extent, and the actual voltage will be somewhere between 1-3V depending on hFE. Towards the high side I think, since Q2 has the advantage (a 10k pullup versus 15k from an already-pulled-down-ish node).
So, yeah, not a good logic level, and inefficient.
It would work better if the common emitter output had a series resistor, so the NAND can pull down on it. Then it has crappy output drive level, but, you could buffer it. Maybe using an inverter, so you get an XNOR instead, but the same basic operation in any case. And then since the interior node doesn't need much drive strength, you could use diodes from the switches, instead of transistors, so you're actually using one fewer transistor overall.
Question: an XOR gate is symmetrical; there is no distinction between SW1 and SW2 behavior. Should the circuit not be symmetrical as well? That is, would you not also have a resistor between Q1 and Q3 bases? (Not that you can have perfect symmetry from a series NAND configuration, but that shouldn't matter much in most cases.)
Tim