after getting drawn into knowing more about vref, i was drawn to watch this multi-part video by peter oakes ( i cant remember who posted it, BUT a big thanks to you!)
https://www.youtube.com/playlist?list=PL_atu5RtEPi4aNzoMtZ5_S6ruhFR98T_p 
in the 2nd video, he introduces a very jellybean approach to getting a vref = zener + N-JFet
i started to try some simulations and came up with this. but i tried it in 2 stages, so the 2nd stage Jfet tries to further stabilize the stabilized output of stage 1. the 2nd pic shows the target zener D1 after being "shielded" from a higher input voltage and increase of 9uV.
is my understanding of oakes' constant current jfet application correct by this 2 stage simulation?
in his video he speaks of the JFET 2n5xxx or J109. in simulation, it is hard to tell, i assume the constant current setting is related to the gate threshold but it doesnt really run that way in virtual so this portion i am confused.

( in E14 listing i found the J110 has -500mV, J109 has -2v Vgs(off). in essence does it mean a 1mA current will require using 0.5k/2k respectively?)
if other noise factors are not an interference/problem (or could be negated), would it in theory mean that with a correct combination of stages ... it is very likely 1 could approach very nearly remarkable stability level?
i am guessing the jfet are terrible at tempco stability ...
