Author Topic: EEVBlog #543 - PCB VIA Current Investigation  (Read 22030 times)

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Offline Monkeh

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #25 on: November 04, 2013, 08:02:02 pm »
Interesting.  I guess that, for production purposes, you'd be stuck with Lead Free Solder (taste-free beer?), but I would be interested to see if there is any significant different between lead free, lead, or even silver solder (although the last one is getting a bit esoteric, admitedly).

Tin is a better conductor than lead.

Silver is one of the best conductors.

Indeed. It's a tiny percentage of solder, though.
 

Offline ali80

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #26 on: November 04, 2013, 08:25:22 pm »
Interesting video, thanks Dave
How the temperature rise of the via is calculated? filling out the via may have some effect on heat transfer coefficient of the via. so the temperature rise may be different.
and since the via's mass is pretty small probing it with a thermocouple may change the via's temperature.
and how much temperature rise would you recommend for a Power supply  board without reducing the board life significantly?
 

Offline walshms

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #27 on: November 04, 2013, 08:28:36 pm »
Rolled copper lays horizontally. You grow plating on top and sideways. So the shear point is if you go down in the tunnel at the point where the vertical plating transits from rolled copper to the dielectric material. That is a fragile point.

Well... maybe.  If we're going to talk about the mechanical interface, let's don't forget about the ductility of the metal.  Even thin layers of copper have ductility, and can withstand some expansion, contraction and flexion.  In fact, copper is one of the more ductile metals, and that's one of the reasons (along with its conductivity) that it's the preferred material for wires.

Basically, the interface between the "rolled" layer of copper and the plated layer isn't as fragile as I think you believe it to be; the process of plating includes a cleaning step where nearly all of the oxidation is removed from the "rolled" layer before it's plated.  The result is a nearly continuous interface.  Provided enough copper is plated, there's enough ductility to handle the mechanical interface as long as you're not beating the board to death or trying to fold it, which would indeed place large shear forces across the interface.

The only way this would actually become a problem is if the plating was too thin.  Most quality manufacturers will plate enough material to obviate that in all but extreme cases.   I think the only real problem is that the plating in the via is thinner, and has increased resistivity; the way to obviate that is either to fill the via with solder or use a Z-wire.

Quote
Most microcracks happen during reflow. Improperly conditioned boards, poor temperature control and the via's will popcorn or microcrack.

If you're seeing this, your boards weren't sufficiently plated.  It simply shouldn't happen if the board is up to snuff.  However -- I'll give you this: larger boards would be more susceptible to it, and smaller boards would be less susceptible to it.  A lot depends on the substrate.  FR-4 will behave differently than polyimide or PTFE.  What we're talking about here is obviously FR-4, but I think you'd be far more likely to see issues with PTFE, and far less likely to see them with polyimide, because of the differences in the thermal expansion coefficient for those materials.

My bottom line on it is the same, though -- if you're seeing the sorts of problems you're describing here, you've made an engineering error (not specifying sufficient plating) or your PCB manufacturer has made a production error (not plating sufficient material or not seeding the vias properly for plating.)
 

Offline walshms

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #28 on: November 04, 2013, 08:29:36 pm »
Silver is one of the best conductors.

Indeed. It's a tiny percentage of solder, though.

No doubt, but even adding a small amount significantly increases electron mobility.
 

Offline open loop

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #29 on: November 04, 2013, 08:55:57 pm »
I wonder when putting a leaded component like a resistor in it would act like a heat sink and then would improve the current handling capability of the via. Would it be worth repeating some measurements with the component wires trimmed off.

Btw very interesting video as I was not expecting the solder filling to have such an effect..
 

Offline walshms

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #30 on: November 04, 2013, 09:05:51 pm »
I wonder when putting a leaded component like a resistor in it would act like a heat sink and then would improve the current handling capability of the via. Would it be worth repeating some measurements with the component wires trimmed off.

The resistivity of most materials increases with temperature.  If it heats up, it will become more resistive, and current will drop.  Adding metal would allow you to sink more heat, up to a point, and keep resistivity lower.  A trimmed component lead, for example, will reach its thermal capacity sooner than it would if it weren't because there's less surface area to reject the heat to the atmosphere.

If you want to seriously start slicing and dicing, however, you have to include the effects of the thermal conductivity of the substrate, the copper traces and other components, convection currents and airflow, yada yada... :blah:

For the kinds of things we do on a day-to-day basis (i.e., we're not designing high-precision measurement and test equipment) the effects are negligible if you use reasonably good engineering practice and always design in enough margin to absolutely kill dead any of these effects.  If you are designing high-precision equipment, you need to consider all of these factors sufficiently to ensure that you're not getting unintended effects. 
 

Online EEVblog

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #31 on: November 04, 2013, 10:12:04 pm »
I wonder when putting a leaded component like a resistor in it would act like a heat sink and then would improve the current handling capability of the via. Would it be worth repeating some measurements with the component wires trimmed off.

It's only 800uW we are talking about here.
And given that we had a 2.2C rise without the wire, and resistance has now dropped by maybe 60-70% with the wire, I don't expect the heat sinking to have any major effect on the results. Plus I took the readings pretty quick, not really giving the "heatsink" much time to heat up.
 

Offline lilshawn

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #32 on: November 05, 2013, 04:28:23 am »
It's only 800uW we are talking about here.
And given that we had a 2.2C rise without the wire, and resistance has now dropped by maybe 60-70% with the wire, I don't expect the heat sinking to have any major effect on the results. Plus I took the readings pretty quick, not really giving the "heatsink" much time to heat up.

but every little bit may have a huge repercussion.

then let's blast the bare via with freeze spray and see if that is indeed true. it stands to reason that the voltage across the via increases when the via was heated (before soldering) that the voltage would also reduce if it was simply cooled.

you could also test that theory by performing the experiment with a same sized via that also had a large thermal mass like an etched copper "heatsink" on the board that would sink away some of that 2.2 degree delta and change the characteristics of the via current handling.
 

Offline walshms

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #33 on: November 05, 2013, 07:54:28 am »
It's only 800uW we are talking about here.

but every little bit may have a huge repercussion.

The resistance change should be relatively small, though; at the power Dave is talking about, the heating isn't significant enough to seriously affect the resistivity.  A meter with good resolution would probably be able to pick it up.  If the delta T were closer to 100C, that would make a big difference, and would be easily measurable.

Quote
then let's blast the bare via with freeze spray and see if that is indeed true. it stands to reason that the voltage across the via increases when the via was heated (before soldering) that the voltage would also reduce if it was simply cooled.

That would be a good little experiment; it's something you can do yourself very easily.  It would certainly show the opposite effect, but again, it would likely be small.  In metals, the resistivity changes are smaller than they would be in, say, a carbon composition resistor.
 

Offline nitro2k01

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #34 on: November 05, 2013, 11:49:27 am »
then let's blast the bare via with freeze spray and see if that is indeed true. it stands to reason that the voltage across the via increases when the via was heated (before soldering) that the voltage would also reduce if it was simply cooled.
Of course it would, but this experiment is less relevant. The relevance of the increased resistance when the via is being heated, is that it's a positive feedback loop. If you are grossly overloading a via, the increased resistance might cause it to break faster than you would expect without taking this effect into consideration. Exactly how much faster? I don't know.
Whoa! How the hell did Dave know that Bob is my uncle? Amazing!
 

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #35 on: November 05, 2013, 11:55:18 am »
but every little bit may have a huge repercussion.

I doesn't work like that.
The changes in resistance from the temperature change was minimal to begin with (you saw it in the video, a few voltage LSD's per second or something). Putting the wire through reduced the resistance heating by maybe 60-70% again.
So it's not going to make any difference to the final result.
 

Offline nathanpc

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #36 on: November 05, 2013, 01:39:30 pm »
Dave, could you share the link to the Google Drive spreadsheet you've created?
 

Offline chat1410

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #37 on: November 05, 2013, 03:04:48 pm »
This video was posted two weeks after I've completed my first PCB layout for senior design. Due to my inexperience laying out boards, my entire 12 V rail comes from the regulator and through a single via to the rest of the board.  |O I'm anticipating a peak current of 1.5 A for ~20 seconds every now and then (water pump will occasionally spray water). The only negative is that the via will heat up, right? I suppose if it heats up too much, I can scrape away the soldermask, jam a lead down it, and fill it with solder.
 

Offline SeanB

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #38 on: November 05, 2013, 07:18:40 pm »
Correct, just scrape top and bottom and place a small copper wire lead and bend over top and bottom and solder.
 

Offline Neilm

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #39 on: November 05, 2013, 09:04:26 pm »
This video was posted two weeks after I've completed my first PCB layout for senior design. Due to my inexperience laying out boards, my entire 12 V rail comes from the regulator and through a single via to the rest of the board.  |O I'm anticipating a peak current of 1.5 A for ~20 seconds every now and then (water pump will occasionally spray water). The only negative is that the via will heat up, right? I suppose if it heats up too much, I can scrape away the soldermask, jam a lead down it, and fill it with solder.

I did that with a 5V rail once. Every so often the micro reset (assuming it actually booted correctly) for no apparent reason.

Chalk it up to a learning experience and remember not to do it in the future.
Two things are infinite: the universe and human stupidity; and I'm not sure about the the universe. - Albert Einstein
 

Offline u271D

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #40 on: November 07, 2013, 10:21:42 am »
just learning about electronics; what good information. I'm putting together a chipino and it has a via for the 5v; after this you best be sure I'm going to be plugin that hole with a bit of copper and solder.  :)
 

Offline lilshawn

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #41 on: November 08, 2013, 01:17:24 am »
After all this talk about vias I ran across this in a schematic for an amplifier...



nice...
 

Offline zapta

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #42 on: November 08, 2013, 04:30:47 pm »
Dave, is it a Digispark left to the scope here?

Drain the swamp.
 

Offline ee851

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #43 on: November 08, 2013, 05:03:46 pm »
Awesome discovery!   Sometimes the smallest detail can make a big difference.   Thanks for sharing, Dave.    Naturally, I'd love to see the reading with Cu-to-Cu, but Cu is quite soft, so you'd have to use sandpaper to scratch down the surfaces until they just barely fit without lubricant.   (Lubricant would probably have a significant resistance.   I'm talking about the anti-corrosion black conductive paste used in mains wiring for connecting Cu to Al)   It would be a lot more work.   But I'd love to know how much lower the Cu-to-Cu would lower the overall DC resistance.

Another thought is there must be some combination of heat, vibration, and perhaps even current that would make the Cu wire bond at the atomic level with the Cu clad on the circuit board, if both were scratched down to bare metal.   But I don't know what that process would be.    It would certainly be a whole new area of research.     And whether or not it would work without causing the PCB to delaminate and self-destruct is another question altogether. 
« Last Edit: November 08, 2013, 05:33:42 pm by ee851 »
 

Offline AndersAnd

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #44 on: November 09, 2013, 02:16:25 am »
Haven't heard about the myth that solder doesn't decrease via resistance.
But I guess it could come from high frequency signals, where it might not be a myth, because of the skin effect.
I would expect the impedance drop by filling a via to become smaller and smaller as frequency rises because of the skin effect.

Could you try a similar experiment at high frequencies?

Skin depth in copper @ 1 MHz is just 0.065 mm:
Source: https://en.wikipedia.org/wiki/Skin_effect
Quote


Skin depth vs. frequency for some materials, red vertical line denotes 50 Hz frequency:
Mn-Zn - magnetically soft ferrite
Al - metallic alumium
Cu - metallic copper
steel 410 - magnetic stainless steel
Fe-Si - grain-oriented electrical steel
Fe-Ni - high-permeability permalloy (80%Ni-20%Fe)
« Last Edit: November 09, 2013, 02:37:07 am by AndersAnd »
 

Offline moemoe

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #45 on: November 10, 2013, 08:50:05 pm »
This might be slightly Off-Topic, but as dave recommended the tool in this episode, I hope it's not totally misplaced:

I tried to reproduce the values printed on the ┬Áruler with http://saturnpcb.com/pcb_toolkit.htm

Max A SMBOC @1oz: 5mil, 10K => 0.45A

But I only get 0.2A as result, see attachement.

Can anybody give me a hint what I'm doing wrong? The via values exactly match the ones on the ┬Áruler.

EDIT: Just found it, it's the IPC-2152 with(out) modifiere mode that changes a lot here.
« Last Edit: November 10, 2013, 08:53:03 pm by moemoe »
https://github.com/maugsburger/
Breadboard Adapters featured in EEVBlog #573 on Tindie
 

Offline Jerry1111

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #46 on: November 10, 2013, 10:09:39 pm »
Very interesting video, thanks Dave.
I've had in my head (for quite a long time now) that solder-filling vias drops their resistance by 10%-20%. I have to admit that I've never actually measured it. I'm a little bit surprised that the resistance is 40% lower than that of the unfilled via. Excellent!

I'm tempted to test if a similar result can be achieved by making holes in the paste mask and using SMD paste instead of solder. The problem of having enough paste to fill the via might be fixed by an over-sized paste-pad. We end up with paste on soldermask, but it should flow into the via (standard technique on various SMD 'modules' with half-cut holes for mounting).

I've just realized that this is quite a good example for a video about test automation in the lab. There are 3 instruments and a time delay involved, which is not uncommon when characterizing something. Writing a simple script which shows how to solve such a task might benefit people (I still remember when I wrote my first ever python script to check a DC/DC using a programmable PSU and a DVM).

 

Offline twistedresistor

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #47 on: November 11, 2013, 04:13:39 pm »
Might be a bit off topic, but does anyone know why the copper thickness of the Saturn PCB toolkit defaults to
18um base copper + 35um plating, which leads to a "total copper thickness" of 53 um (as stated in the "Information" Box of the toolkit).
Reading through a few technolgy guidlines of some pcb-houses for a final copper thickness of 35um they generally start with a copper foil which is about 18um thick and the rest to meet the final copper thickness of 35um is added via electrolysis.

So wouldn't the right choice in the Saturn toolkit be 18um base copper and 18um plating?
 


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