In a Youtube comment David said the big scopes are still all in boxes, because of their move.
There is also a Flash/EEPROM re-programmable version of the chip, the PFS154C.
The padauk IDE, is AFAIK, the only way to create binaries for this platform.
Does this IDE let you access the output binaries yourself? Or are they sent to the programmer directly without giving you access? Comparing these binaries to the data waveforms would be useful. You could observe if data is being shift-clocked in with the need for extra cycles (or similar).
If not, then finding out how the programming protocol works is only a tiny bit of the puzzle :-/O
Perhaps the programmer uses session encryption to the micro based on a unique serial number (read only) in the micro, to mitigate knockoffs (or "midnight batches" in approved factories) being produced.This is a 3¢ micro controller. To cheap to serialize during manufacturing.
7878786768676867
0 0 01 101 101
if the voltage transitions directly form 6 to 8 or 8 to 6 there is an implied '7' meaning : clock ! be weary of these things.Padauk is not making any money selling the programmer, so why don't ask them for the programming protocol?The have been asked and they refused to provide any information.
It usually ends up being more hassle than benefits for a tech company.Tell that to Espressif. They were hiding stuff at first too, and then they quickly realized the power of the passionate community.
Adding support for universal programmers like TL866 can help sell tons of 3cent microcontrollers.
It's unclear to me what incentive they would have to publicly release the programming protocol though. It usually ends up being more hassle than benefits for a tech company. And here I don't think that the kind of customers interested in devising their own tools are the ones who would buy their MCUs by the millions. So...
It's unclear to me what incentive they would have to publicly release the programming protocol though. It usually ends up being more hassle than benefits for a tech company. And here I don't think that the kind of customers interested in devising their own tools are the ones who would buy their MCUs by the millions. So...
With western companies there is a pretty benign explanation for why they don't release even the most trivial things - releasing something implies you will provide support. For whatever reason a concept of releasing things "as is" is not accepted.
But I doubt this is a problem for Padauk. Chinese companies have a habit of releasing a product and not providing any obvious support to the general public. And I like it - it lets us have products that we otherwise would not see, even if they are not well documented.
he says the datasheet is not confidential and I'm allowed to show it to others for review
Funny as the red watermark on every page reads "PADAUK confidential document"
Funny as the red watermark on every page reads "PADAUK confidential document"
Maybe it was confidential at some point, but it really doesn't make sense to hide it. This hardware thread concept looks very useful to simplify application development, without much drawbacks for power consumption or issues with real parallel cores, like synchronization and race conditions etc.
Here is a direct link:Nice work! It looks like you might have all the important instructions decoded. Maybe it would be useful to have a program to parse the compiler output every time and alert if a "new" instruction comes out. After a while, we could be pretty confident about the instruction coding.
https://free-pdk.github.io/PADAUK_FPPA_14_bit_instruction_set.html :) :) :)
It looks like you might have all the important instructions decoded. Maybe it would be useful to have a program to parse the compiler output every time and alert if a "new" instruction comes out. After a while, we could be pretty confident about the instruction coding.
@ js_12345678_55AA: Could you post the modifications you made to deobfuscate the PDKs in the USB_Driver directory?
@ js_12345678_55AA:
Also: in the USB_Driver/USB directory there seems to be the firmware for the programmer (in obfuscated form):
P5SP_BOOT_UPDATER.fw
P5SP_G1.fw
P5SP_G2.fw
P5SP_TESTER.fw
from Dave's video the P5SP files could be for an STM32F072V8T6
seems youtuber "bigclivedotcom" spotted a PADAUK MCU containing device in the wild:
Too bad he doesnt desolder the chip to show the bottom so we can see the package markings.
(Forum doesnt let me post square brackets :-//)
Last picture shows the MCU from back side. I'm pretty sure it is a PMC154 (just the cheapest and the pinout for GND, VDD, crystal also matches).
/* Padauk disassembler plugin for radare */
#include <r_asm.h>
#include <r_lib.h>
#include <string.h>
static struct {
ut8 op1;
ut8 op2;
char *name;
} ops[] = {
{0x00, 0x00, "nopi"},
{0x00, 0x60, "addc a"},
{0x00, 0x61, "subc a"},
{0x00, 0x62, "izsn a"},
{0x00, 0x63, "dzsn a"},
{0x00, 0x64, "?"},
{0x00, 0x65, "?"},
{0x00, 0x66, "?"},
{0x00, 0x67, "pcadd a"},
{0x00, 0x68, "not a"},
{0x00, 0x69, "neg a"},
{0x00, 0x6a, "sr a"},
{0x00, 0x6b, "sl a"},
{0x00, 0x6c, "src a"},
{0x00, 0x6d, "slc a"},
{0x00, 0x6e, "swap a"},
{0x00, 0x6f, "?"},
{0x3f, 0xff, NULL}};
static int _PADAUKDisass (RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
int i;
op->size = 2;
for (i=0; ops[i].name != NULL; i++) {
if (ops[i].op1 == buf[0]) {
if (ops[i].op2 == buf[1]) {
sprintf (op->buf_asm, "%s", ops[i].name);
break;
}
}
}
return op->size;
}
RAsmPlugin r_asm_plugin_padauk = {
.name = "PADAUK",
.arch = "PADAUK",
.license = "LGPL3",
.bits = 16,
.desc = "Padauk disassembler",
.disassemble = &_PADAUKDisass,
};
#ifndef CORELIB
struct r_lib_struct_t radare_plugin = {
.type = R_LIB_TYPE_ASM,
.data = &r_asm_plugin_padauk
};
#endif
NAME=padauk
R2_PLUGIN_PATH=$(shell r2 -hh|grep LIBR_PLUGINS|awk '{print $$2}')
CFLAGS=-g -fPIC $(shell pkg-config --cflags r_asm)
LDFLAGS=-shared $(shell pkg-config --libs r_asm)
OBJS=$(NAME).o
SO_EXT=$(shell uname|grep -q Darwin && echo dylib || echo so)
LIB=$(NAME).$(SO_EXT)
all: $(LIB)
clean:
rm -f $(LIB) $(OBJS)
$(LIB): $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $(LIB)
install:
cp -f $(NAME).$(SO_EXT) $(R2_PLUGIN_PATH)
uninstall:
rm -f $(R2_PLUGIN_PATH)/$(NAME).$(SO_EXT)
/* Padauk (dis)assembler plugin for radare 3.1 git - DocBen 2018 */
#include <r_asm.h>
#include <r_lib.h>
#include <string.h>
static struct {
ut16 op;
char *name;
} ops[] = {
{0x0000, "nop"},
{0x0060, "addc a"},
{0x0061, "subc a"},
{0x0062, "izsn a"},
{0x0063, "dzsn a"},
{0x0064, "?"},
{0x0065, "?"},
{0x0066, "?"},
{0x0067, "pcadd a"},
{0x0068, "not a"},
{0x0069, "neg a"},
{0x006c, "src a"},
{0x006d, "slc a"},
{0x006a, "sr a"},
{0x006b, "sl a"},
{0x006e, "swap a"},
{0x006f, "?"},
{0x0070, "wdreset"},
{0x0071, "?"},
{0x0072, "pushaf"},
{0x0073, "popaf"},
{0x0074, "?"},
{0x0075, "reset"},
{0x0076, "stopsys"},
{0x0077, "stopexe"},
{0x0078, "engint"},
{0x0079, "disgint"},
{0x007b, "reti"},
{0x007a, "ret"},
{0x007c, "mul"},
{0x007d, "?"},
{0x007e, "?"},
{0x007f, "?"},
{0x4000, NULL}};
int _PADAUKDisass (RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
int i;
op->size = 2;
const char *buf_asm = "unknown";
for (i=0; ops[i].name != NULL; i++) {
if (ops[i].op == 0x100 * buf[0] + buf[1]) {
buf_asm = sdb_fmt ("%s", ops[i].name);
break;
}
}
r_strbuf_set (&op->buf_asm, buf_asm);
return op->size;
}
int _PADAUKAss (RAsm *a, RAsmOp *op, const char *buf) {
int i;
op->size = 2;
ut16 opbuf = 0x4000;
const char *buf_hex = "unknown";
for (i = 0; ops[i].name != NULL; i++) {
if (!strncmp(ops[i].name, buf, strlen(ops[i].name))) {
opbuf = ops[i].op;
buf_hex = sdb_fmt ("0x%.4X\n", opbuf);
break;
}
}
r_strbuf_set (&op->buf_hex, buf_hex);
return op->size;
}
RAsmPlugin r_asm_plugin_padauk = {
.name = "padauk",
.arch = "padauk",
.license = "LGPL3",
.bits = 16,
.desc = "Padauk (dis)assembler",
.disassemble = &_PADAUKDisass,
.assemble = &_PADAUKAss,
};
#ifndef CORELIB
struct r_lib_struct_t radare_plugin = {
.type = R_LIB_TYPE_ASM,
.data = &r_asm_plugin_padauk
};
#endif
/* Padauk (dis)assembler plugin for radare 3.1 git - DocBen 2018
now looking more like a datasheet
*/
#include <r_asm.h>
#include <r_lib.h>
#include <string.h>
static struct {
char *op;
char *name;
ut8 args;
char *comment;
} ops[] = {
// memory mapped io i (6-bit)
// nth bit n (3-bit)
// memory address m (6 bit)
// memory address M (7 bit)
// immediate c (8 bit)
// address k (11 bit)
//"binary representation","mnemonic"(,"num parameters (could be inferred)"),"comment"
"0000.0000.0000.0000", "nop", 0, "does nothing (tm)",
"0000.0000.0110.0000", "addc a", 1, "A ← A + CF",
"0000.0000.11ii.iiii", "xor io,a", 2, "IO ← IO ^ A",
"0000.0001.10ii.iiii", "mov io,a", 2, "IO ← A",
"0000.0001.11ii.iiii", "mov a,io", 2, "A ← IO",
"0000.0010.cccc.cccc", "ret c", 1, "",
"0000.0011.1MMM.MMM0", "idxm M, a", 2, "[M] ← A (last bit of M set to 0, M must be word aligned, 2 cycles)",
"0000.0011.1MMM.MMM1", "idxm a, M", 2, "a ← [M] (last bit of M set to 1, M must be word aligned, 2 cycles)",
"0000.010n.nnii.iiii", "swapc io.n", 2, "",
"0000.0110.0MMM.MMMM", "comp a, M", 2, "",
"0010.000n.nnmm.mmmm", "t0sn m.n", 2, "",
"0011.0kkk.kkkk.kkkk", "goto k", 1, "goto address",
"0011.1kkk.kkkk.kkkk", "call k", 1, "call address",
"2222.2222.2222.2222", NULL, 0, "",
};
void bitstring(uint16_t val, char buffer[]) {
int size = 20;
buffer[--size] = 0;
while (size > 0) {
buffer[--size] = (val % 2 ? '1' : '0');
if ( size % 5 == 0 && size > 0) buffer[--size] = '.';
val = val >> 1;
}
}
int _PADAUKDisass (RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
int i;
op->size = 2;
const char *buf_asm = "unknown";
char buf_bin[40];
bitstring(0x100 * buf[0] + buf[1], buf_bin);
for (i=0; ops[i].name != NULL ; i++) {
for (int j = 0; j < 20; j++) {
if (ops[i].op[j] != buf_bin[j]) {
if (ops[i].op[j] != '0' && ops[i].op[j] != '1') { // treat all letters as dont care
continue;
} else {
break;
}
}
if (j == 19) {
buf_asm = sdb_fmt ("%s = %s ; %s", buf_bin, ops[i].name, ops[i].comment);
r_strbuf_set (&op->buf_asm, buf_asm);
return op->size;
}
}
}
r_strbuf_set (&op->buf_asm, buf_asm);
return op->size;
}
int _PADAUKAss (RAsm *a, RAsmOp *op, const char *buf) {
int i;
op->size = 2;
ut16 opbuf = 0x4000;
const char *buf_hex = "unknown";
for (i = 0; ops[i].name != NULL; i++) {
if (!strncmp(ops[i].name, buf, strlen(ops[i].name))) {
//opbuf = ops[i].op;
buf_hex = sdb_fmt ("0x%.4X\n", opbuf);
break;
}
}
r_strbuf_set (&op->buf_hex, buf_hex);
return op->size;
}
RAsmPlugin r_asm_plugin_padauk = {
.name = "padauk2",
.arch = "padauk2",
.license = "LGPL3",
.bits = 16,
.desc = "Padauk (dis)assembler",
.disassemble = &_PADAUKDisass,
.assemble = &_PADAUKAss,
};
#ifndef CORELIB
struct r_lib_struct_t radare_plugin = {
.type = R_LIB_TYPE_ASM,
.data = &r_asm_plugin_padauk
};
#endif
static struct {
char *op;
char *name;
ut8 args;
char *comment;
} ops[] = {
// direction d (1 bit)
// tri-state register t (2 bit)
// nth bit b (3-bit)
// register bank (3 bit)
// register f (5 bit)
// immediate c (8 bit)
// address k (8 bit)
// address K (9 bit)
//"binary representation","mnemonic"(,"num parameters"), "comment"
"0000.0000.0000.0000", "nop", 0, "No operation (MOVW 0,W)",
"0000.0000.0000.0010", "option", 0, "Copy W to OPTION register",
"0000.0000.0000.0011", "sleep", 0, "Go into standby mode",
"0000.0000.0000.0100", "clrwdt", 0, "Restart watchdog timer",
"0000.0000.0000.01tt", "tris t", 0, "Copy W to tri-state register (f = 1, 2 or 3)",
"0000.0000.0001.0BBB", "movlb k", 1, "Set bank select register to k",
"0000.0000.0001.1110", "return", 0, "Return from subroutine, W unmodified",
"0000.0000.0001.1111", "retfie", 0, "Return from interrupt; return & enable interrupts",
"0000.0000.001f.ffff", "movwf f", 1, "dest ← W",
"0000.0000.01df.ffff", "clr f,d", 2, "dest ← 0, usually written CLRW or CLRF f",
"0000.0000.10df.ffff", "subwf f,d", 2, "dest ← f−W (dest ← f+~W+1)",
"0000.0000.11df.ffff", "decf f,d", 2, "dest ← f−1",
"0000.0001.00df.ffff", "iorwf f,d", 2, "dest ← f | W, logical inclusive or",
"0000.0001.01df.ffff", "andwf f,d", 2, "dest ← f & W, logical and",
"0000.0001.10df.ffff", "xorwf f,d", 2, "dest ← f ^ W, logical exclusive or",
"0000.0001.11df.ffff", "addwf f,d", 2, "dest ← f+W",
"0000.0010.00df.ffff", "movwf f,d", 2, "dest ← f",
"0000.0010.01df.ffff", "comf f,d", 2, "dest ← ~f, bitwise complement",
"0000.0010.10df.ffff", "incf f,d", 2, "dest ← f+1",
"0000.0010.11df.ffff", "decfsz f,d", 2, "dest ← f−1, then skip if zero",
"0000.0011.00df.ffff", "rrf f,d", 2, "dest ← CARRY<<7 | f>>1, rotate right through carry",
"0000.0011.01df.ffff", "rlf f,d", 2, "dest ← F<<1 | CARRY, rotate left through carry",
"0000.0011.10df.ffff", "swapf f,d", 2, "dest ← f<<4 | f>>4, swap nibbles",
"0000.0011.11df.ffff", "incfsz f,d", 2, "dest ← f+1, then skip if zero",
"0000.0100.bbbf.ffff", "bcf f,b", 2, "Clear bit b of f",
"0000.0101.bbbf.ffff", "bsf f,b", 2, "Set bit b of f",
"0000.0110.bbbf.ffff", "btfsc f,b", 2, "Skip if bit b of f is clear",
"0000.0111.bbbf.ffff", "btfss f,b", 2, "Skip if bit b of f is set",
"0000.1000.cccc.cccc", "retlw c", 2, "Set W ← k, then return from subroutine",
"0000.1001.kkkk.kkkk", "call k", 2, "Call subroutine, 8-bit address k",
"0000.101K.KKKK.KKKK", "goto k", 2, "Jump to 9-bit address k",
"0000.1100.cccc.cccc", "movlw c", 2, "W ← c",
"0000.1101.cccc.cccc", "iorlw c", 2, "W ← c | W, bitwise logical or",
"0000.1110.cccc.cccc", "andlw c", 2, "W ← c & W, bitwise and",
"0000.1111.cccc.cccc", "xorlw c", 2, "W ← c ^ W, bitwise exclusive or",
"2222.2222.2222.2222", NULL, 0, "",
};
If anyone comes up with a simulator which will run PDK files, I'd love to know about it!
If anyone comes up with a simulator which will run PDK files, I'd love to know about it!
Uhm, I just noticed the PMS150/PMS150C opcodes are different from the PMS154C ones, while still being 14-bit wide. Seems like there are multiple encodings for the same instructions.
For instance:
mov A, 0xAA -> 0x17AA
mov <addr>, A -> 0x05C.. something like that
pcadd a -> 0x0017
wdreset -> 0x0030
But they're not totally different, most of the time it's just one bit off. Also the PDK fill pattern is 0x1FFF instead of 0x3FFF.
This may need some investigation.
edit: actually no value goes beyond 0x1FFF, I should have noticed that before. Seems like they shaved one bit off and the opcodes are 13-bit (?) if that makes any sense.
mov a, lb@fp ; read old frame pointer
pushaf ; save
mov a, sp ; read stack pointer
mov fp, a ; set new frame pointer
add A, 8 ; allocate stack frame
mov SP, A ; update stack pointer
...main code here...
mov a, fp ; read current frame pointer
mov sp, a ; retrack over frame
popaf ; load old frame pointer
mov fp, a ; reload old frame pointer
ret
mov a, 4 ; frame offset
add a, fp ; add frame pointer
mov lb@ptr, a
idxm a, ptr
; index in A, returns value in A
load_value_from_table:
pcadd a ; jump to pc + a
ret 42
ret 99
ret -6
ret 127
...etc...
Re the other flags: the flags byte is at IO address 0, so you can test any individual but with t1sn IO.3 or similar. I don't think we can get away with ignoring them...
Seems like we've been duplicating some work.
Cowgol doesn't use stack frames, though, so it's golden.
Hi Guys,
Just found this thread. Seems like we've been duplicating some work.
I was planning to develop a PC based simulator to allow code to be quickly
tested and debugged, and also perhaps an STM32 based one which would allow
code to be tested "in circuit" with downloadability and decent debugging
capability. Would also like to eventually include device programming in
the STM32 but I've not looked really looked into it yet.
Regards,
Dave
FLAG IO_RW 0x00
OV IO_RW FLAG.3
AC IO_RW FLAG.2
CF IO_RW FLAG.1
ZF IO_RW FLAG.0
T1SN OV
GOTO OVCLEAR
NOP
NOP
OVCLEAR:
Your small language seems really interesting. I also do not see a lot of sense in porting "full" C for this architecture, IMHO it's just less of an hassle to write assembly. A mixed language with assembly+some high level constructs is the best thing, which is in fact what PADAUK did with their Mini-C. If we make an open source toolchain it wouldn't be bad to have our own language for this thing. Of course the self-hosting capability of your compiler (while being really cool) here is pointless, but I see myself liking a language like Cowgol with the possibility to interleave assembly code like PADAUK's Mini-C lets you do. I mean, instead of replicating their Mini-C we could take the opportunity to try something else.
Of course if someone manages to make C compile for this MCUs through SDCC or whatever, that would be really cool, but I would like to see how much overhead it is added, especially regarding function calls.
SDCC makes functions non-reentrant by default (i.e. unless the function is marked __reentrant or the --stack-auto command-line argument is supplied), placing local variables at fixed memory locations.
Anyhow my idea for a "universal" instruction table was to have a list of objects like this, if this can somehow interest you:
It may be faster than your current approach (which I like anyway, it is very readable IMHO) but by pattern matching like that may not be the most efficient thing, also you'll have to reconstruct the parameter values and other stuff which would be easier with a table like mine, at least that's what I anticipate.
I'm an engineer and thus obligated to be as lazy as possible :popcorn:
static const auto PMS154_INSTRUCTIONS_SPEC = std::vector<instr_spec_t>
{
// {mnemonic, opcode, opcode_mask, {args...}}
{"nop", 0x0000, 0x3FFF, {}},
{"addc", 0x0060, 0x3FFF, {{Accumulator, 0, 0}}},
{"subc", 0x0061, 0x3FFF, {{Accumulator, 0, 0}}},
{"izsn", 0x0062, 0x3FFF, {{Accumulator, 0, 0}}},
{"izsn", 0x0063, 0x3FFF, {{Accumulator, 0, 0}}},
// ...
{"wdreset", 0x0070, 0x3FFF, {}},
{"pushaf", 0x0072, 0x3FFF, {}},
{"popaf", 0x0073, 0x3FFF, {}},
// ...
{"xor", 0x00C0, 0x3FC0, {{IO, 0, 6}, {Accumulator, 0, 0}}},
{"mov", 0x0180, 0x3FC0, {{IO, 0, 6}, {Accumulator, 0, 0}}},
{"mov", 0x01C0, 0x3FC0, {{Accumulator, 0, 0}, {IO, 0, 6}}},
{"ret", 0x0200, 0x3F00, {{Immediate, 0, 8}}},
{"stt16", 0x0300, 0x3F81, {{Memory, 0, 7}}},
{"ldt16", 0x0301, 0x3F81, {{Memory, 0, 7}}},
{"idxm", 0x0380, 0x3F81, {{Memory, 0, 7}, {Accumulator, 0, 0}}},
{"idxm", 0x0381, 0x3F81, {{Accumulator, 0, 0}, {Memory, 0, 7}}},
{"swapc", 0x0400, 0x3E00, {{IO, 0, 6}, {Bit_N, 6, 3}}},
{"comp", 0x0600, 0x3F80, {{Accumulator, 0, 0}, {Memory, 0, 7}}},
{"comp", 0x0680, 0x3F80, {{Memory, 0, 7}, {Accumulator, 0, 0}}},
{"nadd", 0x0700, 0x3F80, {{Accumulator, 0, 0}, {Memory, 0, 7}}},
{"nadd", 0x0780, 0x3F80, {{Memory, 0, 7}, {Accumulator, 0, 0}}},
// ...
};
Are you the ImageDisk Dave? Interesting to see you pop up on this thread and looking at these low cost microcontrollers.
#include "extern.h"
void func(void)
{
byte x = 5;
byte y = 6;
byte c;
c = x + y - ~x;
}
void FPPA0 (void)
{
.ADJUST_IC SYSCLK=IHRC/2 // SYSCLK=IHRC/2
func();
byte c = 0;
while (1)
{
c++;
}
}
call _SYS(ADR.ROLL);
call _SYS(ADR.ROLL)+1;
call _SYS(ADR.ROLL)+2;
uint8_t eF = CPUioGet(0x00); //get flags from emulated IO port, mapped like in IO flags: (- - - - V A C Z)
uint8_t eSP = CPUioGet(0x02); //get SP from emulated IO port
uint16_t opcode = CPUcodeGet( ePC++ ); //fetch next opcode and advance PC
eCurrentCycle++; //increment current cycle counter
if( 0x3FFE == opcode ) //special opcode ?
{
//TODO... find out what it does. IDE inserts when using ADJUST_CHIP
}
else
//14 bit opcodes 0x0000 - 0x00BF
if( opcode<=0x00BF )
{
switch( opcode )
{
case 0x0000: break; //NOP
...
}
...
else
//6 bit opcodes 0x02.. , 0x2800 - 0x2FFF
if( (0x0200 == (opcode&0x3F00)) || (0x2800 == (opcode&0x3800)) )
{
switch( opcode & 0x3F00 )
{
case 0x0200: eA = opcode&0xFF; ePC=(((uint16_t)CPUmemGet(--eSP))<<8); ePC|=CPUmemGet(--eSP); break; //RET k
case 0x2800: eA += opcode&0xFF; eF=(eA>255)<<1;eA&=0xFF;eF|=!eA; break; //ADD A,k //TODO: OV, AC
case 0x2900: eA -= opcode&0xFF; eF=(eA>=0)<<1;eA&=0xFF;eF|=!eA; break; //SUB A,k //TODO: OV, AC
case 0x2A00: //CEQSN A,k
case 0x2B00: //CNEQSN A,k
T = eA-(opcode&0xFF); //TODO: A-k or k-A ?
if( ((0x2A00==(opcode&0x3F00)) && !T) ||
((0x2B00==(opcode&0x3F00)) && T) )
{
ePC++; eCurrentCycle++;
}
eF=(T>255)<<1;T&=0xFF;eF|=!T; //TODO: OV,AC (based on T)
break;
case 0x2C00: eA &= opcode&0xFF; eF&=~1;eF|=!eA; break; //AND A,k
case 0x2D00: eA |= opcode&0xFF; eF&=~1;eF|=!eA; break; //OR A,k
case 0x2E00: eA ^= opcode&0xFF; eF&=~1;eF|=!eA; break; //XOR A,k
case 0x2F00: eA = opcode&0xFF; break; //MOV A,k
}
}
else
//5 bit opcodes 0x0400 - 0x0500, 0x1800 - 0x27FF
if( (0x0400 == (opcode&0x3E00)) || ((opcode>=0x1800) && (opcode<=0x27FF)) )
{
uint8_t bit = 1<<((opcode>>6)&7);
uint8_t addr = opcode&0x3F;
switch( opcode & 0x3E00 )
{
case 0x0400: T=CPUioGet(addr);CPUioPut(addr,eF&2?T|bit:T&~bit); eF&=~2;eF|=(T&bit)?2:0; break; //SWAPC IO.n
case 0x1800: if( !(CPUioGet(addr)&bit) ) { ePC++; eCurrentCycle++; } break; //T0SN IO.n
case 0x1A00: if( CPUioGet(addr)&bit ) { ePC++; eCurrentCycle++; } break; //T1SN IO.n
case 0x1C00: CPUioPut(addr,CPUioGet(addr)&~bit); break; //SET0 IO.n
case 0x1E00: CPUioPut(addr,CPUioGet(addr)|bit); break; //SET1 IO.n
case 0x2000: if( !(CPUmemGet(addr)&bit) ) { ePC++; eCurrentCycle++; } break; //T0SN M.n
case 0x2200: if( CPUmemGet(addr)&bit ) { ePC++; eCurrentCycle++; } break; //T1SN M.n
case 0x2400: CPUmemPut(addr,CPUmemGet(addr)&~bit);break; //SET0 M.n
case 0x2600: CPUmemPut(addr,CPUmemGet(addr)|bit);break; //SET1 M.n
}
}
else
//3 bit opcodes 0x3000 - 0x3FFF
if( (0x3000 == (opcode&0x3000)) )
{
if( opcode & 0x0800 ) //CALL needs to put current PC on stack
{
CPUmemPut( eSP++, ePC & 0xFF ); //TODO: check if on stack is little endian
CPUmemPut( eSP++, ePC>>8 ); //TODO: check if on stack is little endian
}
eCurrentCycle++;
ePC = opcode & 0x07FF;
}
else
{
//unknown instruction
CPUexceptionEmulation("Unknown instruction", opcode );
}
CPUioPut(0x02,eSP); //store SP to emulated IO port
CPUioPut(0x00,eF); //store flags to emulated IO port
Is there any possibility of there being an internal ROM with more code in it? That would explain the weird jumps and calls.
Do any of these things have SPI or I2C? Because if we ever figure out the programming protocol, and you could make one of these processors program another, you could incredibly cheaply build a hypercube cluster of the flash versions of these things, all bootstrapped from one processor at the corner attached to the outside world... it'd be useless, but fascinating. Sadly, without some sort of fast comms it's probably not worth it.
Perhaps more relevant to these discussions is my past-life of creating development tools for little processors (mostly 8-bit). C compilers, assemblers, debuggers, simulators etc.
[…]
** Mostly retired now, but always up for an interesting project!
Padauk is not making any money selling the programmer, so why don't ask them for the programming protocol?The have been asked and they refused to provide any information.
Would you be interested in contributing to SDCC, a free C compiler targeting small devices?
Wait, are you the Dunfield C Dunfield?
0x0000: 0x0070 WDRESET ;reset watchdog
0x0001: 0x2f00 MOV A, 0x00
0x0002: 0x0182 MOV IO(0x02), A ;SP ;set SP to memory start (0)
0x0003: 0x3fed CALL 0x7ED ;get IHRCR (value inserted from WRITER)
0x0004: 0x018b MOV IO(0x0B), A ;IHRCR ;setup IHRCR
0x0005: 0x3fee CALL 0x7EE
0x0006: 0x019a MOV IO(0x1A), A ;BGTR? (not in datasheet)
0x0007: 0x2f00 MOV A, 0x00 ;setup low voltage detector (value inserted from IDE .CHIP)
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR 4V/3V5/3V/2V75/2V5/1V8/2V2/2V
0x0009: 0x2f34 MOV A, 0x34
0x000a: 0x0183 MOV IO(0x03), A ;CLKMD ;setup clock mode (value inserted from IDE .ADJUST_IC)
0x000b: 0x3ffe CALL 0x7FE ;get stored calibration value (stored during programing of OTP)
;This is a nice trick. The OTP reads all as '1' when not programmed. Programing will change the relevant bits to '0'.
;The trick is that you can program the OTP multiple times. It is always possible to change '1' to '0' but never the other way around.
;So they store 0x02FF in code memory at position 0x7FE which translates to RET 0xFF. Later programer can change the 0xFF return value by
;overwriting it with the final value (0xFF still all bits '1').
;This means all the code follows is used for calibration during programing only (big waste of OTP)
0x000c: 0x2aff CEQSN A, 0xFF ;Check if is 0xFF (nothing written there?)
0x000d: 0x3054 GOTO 0x054 ;Jump over calibration routine to user program
0x000e: 0x3fed CALL 0x7ED ;get IHRCR (value inserted from programmer)
0x000f: 0x0b81 MOV [0x01], A ;store it in memory @0x01
0x0010: 0x1f91 SET1 IO(0x11).6 ;PAC.6 ;configure PA.6 as output
;calibration routine
0x0011: 0x2f20 MOV A, 0x20
0x0012: 0x0b80 MOV [0x00], A ;store 0x20 in memory @0x00
0x0013: 0x1ad0 T1SN IO(0x10).3 ;PA.3 ;check for HIGH signal at PA.3 <-- check for handshake signal for WRITER
0x0014: 0x3013 GOTO 0x013 ;wait until PA.3 is high
0x0015: 0x1f90 SET1 IO(0x10).6 ;PA.6 ;set PA.6 to HIGH <-- send response to WRITER
0x0016: 0x0063 DZSN A ;1c big delay, underflows after first loop
0x0017: 0x3016 GOTO 0x016 ;2c inner loop apx. 3*256 cycles = 768 cycles
0x0018: 0x1180 DZSN [0x00] ;1c
0x0019: 0x3016 GOTO 0x016 ;2c outer loop apx. 32*(768+3) = 24672 cycles,
;-224 cycles from first inner loop (was init with 32 instead of 255) = 24448 cycles total delay
0x001a: 0x1d90 SET0 IO(0x10).6 ;PA.6 ;set PA.6 to LOW <-- stop sending response to WRITER
0x001b: 0x18d0 T0SN IO(0x10).3 ;PA.3 ;check for LOW signal at PA.3 <-- wait for WRITER to stop sending handshake signal
0x001c: 0x301b GOTO 0x01B ;wait until PA.3 is low
0x001d: 0x2f01 MOV A, 0x01
0x001e: 0x1950 T0SN IO(0x10).5 ;PA.5 ;if PA.5 is LOW ==> A=0x01 , HIGH ==> A=0xFF <-- WRITER sets ? ? ? value to 1/255 by setting PA.5
0x001f: 0x2fff MOV A, 0xFF
0x0020: 0x0c01 ADD A, [0x01] ;add to IHRCR (value inserted from programmer) 1 or 255 (see above)
0x0021: 0x018b MOV IO(0x0B), A ;IHRCR ;set new IHRCR
0x0022: 0x0b81 MOV [0x01], A ;store new IHRCR value in memory @0x01
0x0023: 0x1ad0 T1SN IO(0x10).3 ;PA.3 ;check for HIGH signal at PA.3 <-- check for handshake signal for WRITER
0x0024: 0x3023 GOTO 0x023 ;wait until PA.3 is high
0x0025: 0x1b50 T1SN IO(0x10).5 ;PA.5 ;check for HIGH signal at PA.5 <-- WRITER signals all done?
0x0026: 0x304f GOTO 0x04F ;jump to end of calibration code
0x0027: 0x2f04 MOV A, 0x04
0x0028: 0x0188 MOV IO(0x08), A ;MISC ;disable low voltage detector
0x0029: 0x18d0 T0SN IO(0x10).3 ;PA.3 ;check for LOW signal at PA.3 <-- wait for WRITER to stop sending handshake signal
0x002a: 0x3029 GOTO 0x029 ;wait until PA.3 is low
;start measurment
0x002b: 0x2f02 MOV A, 0x02
0x002c: 0x0182 MOV IO(0x02), A ;SP ;setup SP to memory @0x02
0x002d: 0x1304 CLEAR [0x04] ;zero memory @0x04
0x002e: 0x1305 CLEAR [0x05] ;zero memory @0x05
0x002f: 0x2f55 MOV A, 0x55
0x0030: 0x0b82 MOV [0x02], A ;store 0x55 in memory @0x02
0x0031: 0x2f00 MOV A, 0x00
0x0032: 0x0b83 MOV [0x03], A ;store 0x00 in memory @0x03
;16 bit loop (0x0055) times some operations with internal value LDSPTL:LDSPTH (timing register?)
0x0033: 0x0006 LDSPTL ;?load from timing register L
0x0034: 0x0b04 XOR [0x04], A
0x0035: 0x0007 LDSPTH ;?load from timing register H
0x0036: 0x0805 ADD [0x05], A
0x0037: 0x1584 SL [0x04] ;rotate left 16 bit value
0x0038: 0x1685 SLC [0x05]
0x0039: 0x1004 ADDC [0x04]
0x003a: 0x1282 DECM [0x02] ;memory low byte -1
0x003b: 0x1083 SUBC [0x03] ;memory high byte -1 if carry set
0x003c: 0x1a40 T1SN IO(0x00).1 ;FLAG.CF ;test for carry (0x0000 -1 => carry set)
0x003d: 0x3033 GOTO 0x033 ;loop
0x003e: 0x1f90 SET1 IO(0x10).6 ;PA.6 ;set PA.6 to HIGH <-- send response to WRITER (measurement finished)
;send bit by bit the 16 bit measured value
0x003f: 0x1ad0 T1SN IO(0x10).3 ;PA.3 ;check for HIGH signal at PA.3 <-- check for handshake signal for WRITER
0x0040: 0x303f GOTO 0x03F ;wait until PA.3 is high
0x0041: 0x1584 SL [0x04] ;16 bit shift left
0x0042: 0x1685 SLC [0x05]
0x0043: 0x0590 SWAPC IO(0x10).6 ;PA.6 ;set PA.6 according to carry (highest bit from 16 bit value before shift)
0x0044: 0x18d0 T0SN IO(0x10).3 ;PA.3 ;check for LOW signal at PA.3 <-- wait for WRITER to stop sending handshake signal
0x0045: 0x3044 GOTO 0x044 ;wait until PA.3 is low
0x0046: 0x1950 T0SN IO(0x10).5 ;PA.5 ;check if PA.5 is LOW <-- WRITER signals to send next bit
0x0047: 0x303f GOTO 0x03F
0x0048: 0x1d90 SET0 IO(0x10).6 ;PA.6 ;set PA.6 to LOW
0x0049: 0x1ad0 T1SN IO(0x10).3 ;PA.3 ;check for HIGH signal at PA.3 <-- check for handshake signal for WRITER
0x004a: 0x3049 GOTO 0x049 ;wait until PA.3 is high
0x004b: 0x18d0 T0SN IO(0x10).3 ;PA.3 ;check for LOW signal at PA.3 <-- wait for WRITER to stop sending handshake signal
0x004c: 0x304b GOTO 0x04B ;wait until PA.3 is low
0x004d: 0x1b50 T1SN IO(0x10).5 ;PA.5 ;check for HIGH signal at PA.5 <-- WRITER signals to redo measurement
0x004e: 0x302b GOTO 0x02B ;if PA.5 is LOW do the measurement again
;here seems to be an error in the program from PADAUK, very unlikely PA.3 went hight during last 2 instructions, should be HIGH check for sure
0x004f: 0x18d0 T0SN IO(0x10).3 ;PA.3 ;check for LOW signal at PA.3
0x0050: 0x304f GOTO 0x04F ;wait until PA.3 is low
0x0051: 0x1b50 T1SN IO(0x10).5 ;PA.5 ;check for HIGH signal at PA.5 <-- WRITER signals all done?
0x0052: 0x3011 GOTO 0x011 ;if PA.5 is LOW do the complete calibration again (including all handshakes)
0x0053: 0x3053 GOTO 0x053 ;calibration successful, endless loop (chip needs reset + writing of calibration value from WRITER)
;----------------------------------------------------------------------------------------------------------------------------------------------
0x0054: 0x018b MOV IO(0x0B), A ;IHRCR ;normal program start, set IHRCR
0x0055: 0x3055 GOTO 0x055 ;the user program (was just a "while(1){}" loop)
;start measurment
0x002b: 0x2f02 MOV A, 0x02
0x002c: 0x0182 MOV IO(0x02), A ;SP ;setup SP to memory @0x02
0x002d: 0x1304 CLEAR [0x04] ;zero memory @0x04
0x002e: 0x1305 CLEAR [0x05] ;zero memory @0x05
0x002f: 0x2f55 MOV A, 0x55
0x0030: 0x0b82 MOV [0x02], A ;store 0x55 in memory @0x02
0x0031: 0x2f00 MOV A, 0x00
0x0032: 0x0b83 MOV [0x03], A ;store 0x00 in memory @0x03
;16 bit loop (0x0055) times some operations
0x0033: 0x0006 LDSPTL ;load from memory where SP is pointing to A
0x0034: 0x0b04 XOR [0x04], A
0x0035: 0x0007 LDSPTH ;load from memory where SP is pointing to A
0x0036: 0x0805 ADD [0x05], A
0x0037: 0x1584 SL [0x04] ;rotate left 16 bit value
0x0038: 0x1685 SLC [0x05]
0x0039: 0x1004 ADDC [0x04]
0x003a: 0x1282 DECM [0x02] ;memory low byte -1
0x003b: 0x1083 SUBC [0x03] ;memory high byte -1 if carry set
0x003c: 0x1a40 T1SN IO(0x00).1 ;FLAG.CF ;test for carry (0x0000 -1 => carry set)
0x003d: 0x3033 GOTO 0x033 ;loop
00000 00000000 NOP
00000 00000000 TRAP // Assembler accepts, but same as NOP
00000 00000001
.. .. ??
00000 00001111
00000 00010000 ADDC A
00000 00010001 SUBC A
00000 00010010 IZSN A
00000 00010011 DZSN A
00000 00010100
.. .. ??
00000 00010110
00000 00010111 PCADD A
00000 00011000 NOT A
00000 00011001 NEG A
00000 00011010 SR A
00000 00011011 SL A
00000 00011100 SRC A
00000 00011101 SLC A
00000 00011110 SWAP A
00000 00011111
.. .. ??
00000 00101111
00000 00110000 WDRESET
00000 00110001 ?
00000 00110010 PUSHAF
00000 00110011 POPAF
00000 00110100 ?
00000 00110101 RESET
00000 00110110 STOPSYS
00000 00110111 STOPEXE
00000 00111000 ENGINT
00000 00111001 DISGINT
00000 00111010 RET
00000 00111011 RETI
00000 00111100
.. .. ??
00000 01011111
00000 011ppppp XOR io-addr,A
00000 100ppppp MOV io-addr,A
00000 101ppppp MOV A,io-addr
00000 110aaaa0 STT16 ram-addr-even
00000 110aaaa1 LDT16 ram-addr-even
00000 111aaaa0 IDXM ram-addr-even,A
00000 111aaaa1 IDXM A,ram-addr-even
00001 dddddddd RET imm-data
00010 bbb0aaaa T0SN ram-addr.bit
00010 bbb1aaaa T1SN ram-addr.bit
00011 bbb0aaaa SET0 ram-addr.bit
00011 bbb1aaaa SET1 ram-addr.bit
00100 00aaaaaa ADD ram-addr,a
00100 01aaaaaa SUB ram-addr,a
00100 10aaaaaa ADDC ram-addr,A
00100 11aaaaaa SUBC ram-addr,A
00101 00aaaaaa AND ram-addr,A
00101 01aaaaaa OR ram-addr,A
00101 10aaaaaa XOR ram-addr,A
00101 11aaaaaa MOV ram-addr,A
00110 00aaaaaa ADD A,ram-addr
00110 01aaaaaa SUB A,ram-addr
00110 10aaaaaa ADDC A,ram-addr
00110 11aaaaaa SUBC A,ram-addr
00111 00aaaaaa AND A,ram-addr
00111 01aaaaaa OR A,ram-addr
00111 10aaaaaa XOR A,ram-addr
00111 11aaaaaa MOV A,ram-addr
01000 00000000
.. .. ??
01000 01111111
01000 10aaaaaa IZSN ram-addr
01000 11aaaaaa DZSN ram-addr
01001 00aaaaaa INC ram-addr
01001 01aaaaaa DEC ram-addr
01001 10aaaaaa CLEAR ram-addr
01001 11aaaaaa XCH ram-addr
01010 00aaaaaa NOT ram-addr
01010 01aaaaaa NEG ram-addr
01010 10aaaaaa SR ram-addr
01010 11aaaaaa SL ram-addr
01011 00aaaaaa SRC ram-addr
01011 01aaaaaa SLC ram-addr
01011 10aaaaaa CEQSN A,ram-addr
01011 11000000
.. .. ??
01011 11111111
01100 bbbppppp T0SN io-addr.bit
01101 bbbppppp T1SN io-addr.bit
01110 bbbppppp SET0 io-addr.bit
01111 bbbppppp SET1 io-addr.bit
10000 dddddddd ADD A,imm-data
10001 dddddddd SUB A,imm-data
10010 dddddddd CEQSN A,imm-data
10011 00000000
.. .. ??
10011 11111111
10100 dddddddd AND A,imm-data
10101 dddddddd OR A,imm-data
10110 dddddddd XOR A,imm-data
10111 dddddddd MOV A,imm-data
110aa aaaaaaaa GOTO code-addr
111aa aaaaaaaa CALL code-addr
Nice job js_12345678_55AA, really interesting. Will take an in depth look.
At the moment I also got the 13-bit ISA implemented in my infrastructure so I can disassemble PMS150 (C) ROMs. I noticed an interesting thing (I still have to look at the disasm). The PMS150 (without the C) has an order of magnitude less init code compared to the PMS150C (which seems to have code that more or less does the same stuff the 154C is doing).
I'm attaching the two listings if someone wants to take a look and start figuring it out.
(to discriminate what's "my" code and PADAUK's code, in both ROMs I only have the main which is simply incrementing a byte in memory, you'll find the inc [0x...]; goto @0x... as the last two instructions in both listings, that are the only two things not part of the init code)
After checking the disassembly of the calibration again some things look suspicious:
;start measurment
0x002b: 0x2f02 MOV A, 0x02
0x002c: 0x0182 MOV IO(0x02), A ;SP ;setup SP to memory @0x02
0x002d: 0x1304 CLEAR [0x04] ;zero memory @0x04
0x002e: 0x1305 CLEAR [0x05] ;zero memory @0x05
0x002f: 0x2f55 MOV A, 0x55
0x0030: 0x0b82 MOV [0x02], A ;store 0x55 in memory @0x02
0x0031: 0x2f00 MOV A, 0x00
0x0032: 0x0b83 MOV [0x03], A ;store 0x00 in memory @0x03
;16 bit loop (0x0055) times some operations
0x0033: 0x0006 LDSPTL ;load from memory where SP is pointing to A
0x0034: 0x0b04 XOR [0x04], A
0x0035: 0x0007 LDSPTH ;load from memory where SP is pointing to A
0x0036: 0x0805 ADD [0x05], A
0x0037: 0x1584 SL [0x04] ;rotate left 16 bit value
0x0038: 0x1685 SLC [0x05]
0x0039: 0x1004 ADDC [0x04]
0x003a: 0x1282 DECM [0x02] ;memory low byte -1
0x003b: 0x1083 SUBC [0x03] ;memory high byte -1 if carry set
0x003c: 0x1a40 T1SN IO(0x00).1 ;FLAG.CF ;test for carry (0x0000 -1 => carry set)
0x003d: 0x3033 GOTO 0x033 ;loop
At the beginning the SP is setup to point to a new location. SP / stack is never used anywhere after this point in calibration program.
So the only use could be from the undocumented instructions LDSPTL and LDSPTH. Also SP points to the memory which is initialized
with static values.
This lets me think LDSPTL/LDSPTL stands for "LoaD from SP Table Low" / "LoaD from SP Table High":
LDSPTL => A = [SP]
LDSPTH => A = [SP+1]
Then the above loop would be again some "obfuscation" crypto from PADAUK (XOR 0x55 ... smells like the magic value they love, known from IDE obfuscation).
The result in this case is just 0x11E4 which is then sent out via bitbang to the WRITER to "verify" :-DD
The loop also serves the purpose to run for several cycles, so WRITER can measure the time it takes and use it for calibration.
JS
EDIT: The loop runs for exact 1040 cycles (including loop init) :)
SP / stack is never used anywhere after this point in calibration program.
So the only use could be from the undocumented instructions LDSPTL and LDSPTH.
Also SP points to the memory which is initialized with static values.
Could you also add the 13-bit instructions to the documentation on GitHub?
Also, js_12345678_55AA, I had a pull on the docs repo fixing some stuff that is still unfixed after your last commit (a couple of instr swapped IIRC), maybe you want to check that out.
Back in 2006 I was talking to a uC manufacturer in China about their 4 bit uC then costing $0,11 and lower with high volume we were discussing. It could replace $0,40 of logic on our boards so quite interesting with massproduction.
There were some bizar quirks in those things. They were manufactured for one single goal: cheap toys.
The manufacturing process was not as you expect from fabs these days with a result that in your firmware at boottime you had to test the ram since unknown bits would (not could) be dead and you had to make a map so not to use that byte in ram. Also upto 2% of the devices would have problems in the alu or other critical parts. I asked how I could know that the first code would run ok if the ram was not to be trusted. The answer was you could tell from the end product if it worked or not. :-DD
I couldnt believe this but had it b&w in an email.
They probably also sell 100% tested uCs that had no flaws but that was pricewise much less interesting.
#include "extern.h"
void<>FPPA0 (void)
{
.ADJUST_IC SYSCLK=IHRC/2 // SYSCLK=IHRC/2
while (1){}
}
...
00000008 MOV ---- A / 0x0008: 0x019b MOV IO(0x1B), A ;
...
00000033 NOP / 0x0033: 0x0006 LDSPTL
00000034 NOP / 0x0034: 0x0b04 XOR [0x04], A
00000035 NOP / 0x0035: 0x0007 LDSPTH
00000036 NOP / 0x0036: 0x0805 ADD [0x05], A
00000037 NOP / 0x0037: 0x1584 SL [0x04]
00000038 NOP / 0x0038: 0x1685 SLC [0x05]
00000039 NOP / 0x0039: 0x1004 ADDC [0x04]
0000003A NOP / 0x003a: 0x1282 DECM [0x02]
0000003B NOP / 0x003b: 0x1083 SUBC [0x03]
...
Hi,
I just got my ICE today... and when you connect it and start debugging you can bring up a disassembly window (no opcodes of course but good to verify our stuff).
Is there any way you could determine the type of fpga they are using?
EDIT:
USB enumeration shows this:
VID: 0x0797
PID: 0x7002
Device String: "LGS_DEV FX2-HID 0.01"
T: Bus=01 Lev=01 Prnt=01 Port=01 Cnt=03 Dev#= 9 Spd=480 MxCh= 0
D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1
P: Vendor=0797 ProdID=7002 Rev=80.01
S: Manufacturer=PADAUK
S: Product=LGS_DEV FX2-HID 0.01
C: #Ifs= 1 Cfg#= 1 Atr=a0 MxPwr=500mA
I: If#= 0 Alt= 0 #EPs= 2 Cls=03(HID ) Sub=00 Prot=00 Driver=usbhid
I got my ICE today as well. Here is a high resolution image: https://i.imgur.com/8yef37g.jpg (https://i.imgur.com/8yef37g.jpg)
The FPGA has no markings. It might be possible to capture the JTAG init sequence, if it doesn't store the configuration data inside the FPGA, because looks like there is no external configuration flash memory.
I got my ICE today as well. Here is a high resolution image: https://i.imgur.com/8yef37g.jpg (https://i.imgur.com/8yef37g.jpg)
The FPGA has no markings. It might be possible to capture the JTAG init sequence, if it doesn't store the configuration data inside the FPGA, because looks like there is no external configuration flash memory.
Does the FPGA have markings on the bottom? It doesnt look dremeled on the top to me.
I just ordered one of these PLCC remover from China. Will report back in 4 weeks when it arrives :)
Could be a CPLD - plenty of PLC44 options showing on Digikey for that package. If there is 5V anywhere that would narrow it down a lot.Hi,
I just got my ICE today... and when you connect it and start debugging you can bring up a disassembly window (no opcodes of course but good to verify our stuff).
Is there any way you could determine the type of fpga they are using?
Could be a CPLD - plenty of PLC44 options showing on Digikey for that package. If there is 5V anywhere that would narrow it down a lot.
Hi,
>Hi, do you have any plans to upload your disassembler (and eventually assembler if you have one) to the GitHub organization?
Sure I will do (I just want to structure it a bit more, will take 1-2 days)
>I also have tools in a preliminary state working with the 13-bit and 14-bit ISAs, which unfortunately is duplicate work but I wanted to disasm some listings so I proceeded anyway in implementing them, but that was not a lot of work so it's not a problem for me to trash everything if we want to keep your infrastructure.
All of the code I did is also just for experimentation. Most likely it will be replaced by better implementations later. So no need to keep / stick to something from me right now.
>Also I think we should define a bit how we want to proceed with the assembler.
I did not start with an assembler implementation. Maybe this is something you/somebody else want to try?
I'm already busy reversing stuff and find out how things are connected.
Today my WRITER and SIMULATOR arrived. So now I can start to work with real hardware :-)
>Some stuff to be discussed may be:
>- syntax quirks (how to represent various kind of values/addresses), asm directives, macros, defines, includes, etc...
I did not really investigated on this. I just used a syntax which I thought was good enough for first tests.
Mainly I used the syntax PADAUK used in their manuals. Just to distinguish between RAM / ROM / IO we would need to invent something. Note: The "." syntax is mainly used to represent a special bit (8051 assembly). "[ ]" are used for normal memory access. "WORD PTR" is usually used for 16 bit address references, ... I think we should adapt already known schemes so it easier for others to understand
Creating a document defining the syntax of the assembler would be a good starting point.
I think during implementation of assembler some changes will be required. Since the disassembler is fairly easy to adapt I consider it to follow any syntax changes the assembler creator might need to do.
>- whether to deviate from PADAUK's ASM syntax and implement something of our own, or whether to implement their same syntax for compatibility; or even both at the same time (i.e. a flag to choose the syntax)
One syntax please :-). As close as possible to PADAUK syntax with just some extensions for direct memory/io access.
>- what binary format we want to use across the open source toolchain, i.e. just the raw ROM content on a .bin file, or keeping their PDK format for compatibility with their OTP Writer, or have our own format, or a mix of these three things, or whatever :)
I think we should use the PDK format. The creation for a "liberated" WRITER seems to be the most difficult part which most likely will take the longest time.
>- if it makes sense to keep the ISA description open enough so that it can be imported by someone that wants to implement for instance an SDCC backend or a radare2 plugin to disasm, etc... or just keep it simple and hard coded in the tools
The ISA is so small and simple, everyone can adapt and implement it for a disasm within a few hours. So I think there is no need to be generic here.
>Also, regarding an hypothetical PC simulator (not real time, maybe cycle accurate, or even not) for debugging only:
Why "hypothetical PC simulator"? I finished this task already 8)
>- how that would be presented to the user, i.e.
>- a GUI? With what features? I/O interaction?
>- some kind of simulation you launch and outputs a waveform file in some standard format for inspection later (and that can also accept an input waveform file or some kind of description of what to do with the inputs - i.e. after 0.1s set PA.3 high etc...)
>- a command line tool like GDB where you can single step, inspect memory and regs, run, pause, etc...
>- a combination of some of the things above
>- ...
I was having a look at a 8051 emulator which uses ncurses ( https://github.com/jarikomppa/emu8051 ). This simulator I plan to repurpose for the front end.
>- we'll need our own init code if we want to create a full toolchain you can use from start to finish without touching PADAUK's tools, what should be done in that regard? Should we replicate PADAUK's code (eventually improving it) or do something else? Maybe have different init code options i.e. if you don't need precise clock speeds you can free up space by not having the calibration code, or you can chose to have it, you can have the ROM checksum or not, etc...
The init code is tied to the WRITER which I think we should stay compatible with (see comment above).
Usually this kind of things (init code) is implemented in include (.INC) files which the developer gets automatically in his project when he starts a new project (e.g. from a empty project template).
Then it up to the developer to modify / delete stuff from init code or use different/optimized implementations.
>- least important thing in this message but cool: a library of pre-made routines for stuff like SPI, UART, etc... could be made and optimized by the community. Like a collection of include files "spi.inc" "uart.inc" you can just bring in and use would be pretty cool
Personally I prefer simple sample projects with code snippets I can just cut and paste to my project. I don't like big libraries (like Arduino or STM32). Especially when every byte counts.
>The STM32 emulator you're working on is also vital in the toolchain I think, so keep that up. I started to play around with some methods of efficiently emulating the code on ARM Thumb by checking what assembly GCC generates for various approaches, and it seems like writing the time critical parts in assembly may be the easiest route... GCC insists on keeping the PC/ACC/ecc in RAM but having 12 general purpose registers I think the best thing is to assign the ACC, PC, SP, etc... to a couple of regs and avoid all the LDRs that just slow things down. Of course I may be wrong and there may be a way to write the C code in such a way that GCC does this by itself, but I still didn't find a way. I thought we could map every PADAUK's cycle to 8 cortex cycles with a CPU clock of 64MHz which sounds a reasonable choice given there's the ultracheap STM32F103C8T6 everywhere on eBay, Aliexpress, etc... that fits that frequency, staying in an 8 cycle frame might be viable if most of the stuff is in registers since most instructions take 1 cycle only. Did you make any progress regarding emulation on STM32?
After implementing the FLAG solver for AC and OV i recognized emulation will be quite complex.
Also keep in mind that you need to emulate the CLOCK, IO, PWM, INTERRUPTS, TIMER, WATCHDOG, ...
So I don't think a near real time emulation on STM32 will be possible.
But why not using FPGA? Simple ones are also very cheap. And one guy here in forum already said he would be able to create a FPGA version.
>Let me know what you think about my points and how we should proceed. If we can coordinate at least a bit the work that should be done (and how it should be done) I can start working on some tools.
Creating the assembler would be nice.
I really would love to have an assembler as soon as possible so I can automate tests for the simulator :-)
Does the FPGA have markings on the bottom? It doesnt look dremeled on the top to me.
// define pin names
Out0 BIT PB.0;
Out1 BIT PB.1;
Out2 BIT PB.2;
Out3 BIT PB.3;
Out4 BIT PB.4;
Out5 BIT PB.5;
Out6 BIT PB.6;
Out7 BIT PB.7;
// FPPA0 is started first
void FPPA0 (void)
{
.ADJUST_IC SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V, Bandgap=On;
// set pins to output
$ Out0 High, Out;
$ Out1 High, Out;
$ Out2 High, Out;
$ Out3 High, Out;
$ Out4 High, Out;
$ Out5 High, Out;
$ Out6 High, Out;
$ Out7 High, Out;
// see datasheet "pmode": FPPA duty cycle, 1/8 for all 8 FPPAs
pmode 31;
// enable all FPPAs
fppen = 0xFF;
// generate test output
while (1) {
Out0 = 0;
.delay 1;
Out0 = 1;
.delay 1;
}
}
void FPPA1 (void)
{
// generate test output
while (1) {
Out1 = 0;
.delay 10;
Out1 = 1;
.delay 10;
}
}
void FPPA2 (void)
{
// generate test output
while (1) {
Out2 = 0;
.delay 100;
Out2 = 1;
.delay 100;
}
}
void FPPA3 (void)
{
// generate test output
while (1) {
Out3 = 0;
.delay 1000;
Out3 = 1;
.delay 1000;
}
}
void FPPA4 (void)
{
// generate test output
while (1) {
Out4 = 0;
.delay 10000;
Out4 = 1;
.delay 10000;
}
}
void FPPA5 (void)
{
// generate test output
while (1) {
Out5 = 0;
.delay 100000;
Out5 = 1;
.delay 100000;
}
}
void FPPA6 (void)
{
// generate test output
while (1) {
Out6 = 0;
.delay 1000000;
Out6 = 1;
.delay 1000000;
}
}
void FPPA7 (void)
{
// generate test output
while (1) {
Out7 = 0;
.delay 10000000;
Out7 = 1;
.delay 10000000;
}
}
/*
void Interrupt (void)
{
pushaf;
if (Intrq.T16)
{ // T16 Trig
// User can add code
Intrq.T16 = 0;
//...
}
popaf;
}
*/
PB0: 203 kHz
PB1: 44 kHz
PB2: 5 kHz
PB3: 508 Hz
PB4: 50.8 Hz
PB5: 5.08 Hz
PB6: 0.5 Hz
PB7: 0.05 Hz
Does the FPGA have markings on the bottom? It doesnt look dremeled on the top to me.
Here comes the money shot:
Picture shows the ICE main IC (PLCC 44) from bottom.
Based on the top shape / edge / dot / corner and the "SCD" marking on the bottom it most probably is a Xilinix.
Shape matches exact this drawing: https://japan.xilinx.com/support/documentation/package_specs/pc44.pdf Most other PLCC44 FPGA/CLPD have marks on top / 2 edges / no dot in middle / ...
Happy hunting!
JS
Is that feasible? Are the files in USB_Driver/USB/ICE* really 8051ish code?
I'm reporting a conversation between me and js_12345678_55AA regarding planning of what to do next (and how) if anyone wants to share its thoughts. Not sure why I didn't directly post here in the forum thread, sorry for that :-//
The things of most interest are probably the assembler and the syntaxQuoteHi,
>Hi, do you have any plans to upload your disassembler (and eventually assembler if you have one) to the GitHub organization?
Sure I will do (I just want to structure it a bit more, will take 1-2 days)
>I also have tools in a preliminary state working with the 13-bit and 14-bit ISAs, which unfortunately is duplicate work but I wanted to disasm some listings so I proceeded anyway in implementing them, but that was not a lot of work so it's not a problem for me to trash everything if we want to keep your infrastructure.
All of the code I did is also just for experimentation. Most likely it will be replaced by better implementations later. So no need to keep / stick to something from me right now.
>Also I think we should define a bit how we want to proceed with the assembler.
I did not start with an assembler implementation. Maybe this is something you/somebody else want to try?
I'm already busy reversing stuff and find out how things are connected.
Today my WRITER and SIMULATOR arrived. So now I can start to work with real hardware :-)
>Some stuff to be discussed may be:
>- syntax quirks (how to represent various kind of values/addresses), asm directives, macros, defines, includes, etc...
I did not really investigated on this. I just used a syntax which I thought was good enough for first tests.
Mainly I used the syntax PADAUK used in their manuals. Just to distinguish between RAM / ROM / IO we would need to invent something. Note: The "." syntax is mainly used to represent a special bit (8051 assembly). "[ ]" are used for normal memory access. "WORD PTR" is usually used for 16 bit address references, ... I think we should adapt already known schemes so it easier for others to understand
Creating a document defining the syntax of the assembler would be a good starting point.
I think during implementation of assembler some changes will be required. Since the disassembler is fairly easy to adapt I consider it to follow any syntax changes the assembler creator might need to do.
>- whether to deviate from PADAUK's ASM syntax and implement something of our own, or whether to implement their same syntax for compatibility; or even both at the same time (i.e. a flag to choose the syntax)
One syntax please :-). As close as possible to PADAUK syntax with just some extensions for direct memory/io access.
>- what binary format we want to use across the open source toolchain, i.e. just the raw ROM content on a .bin file, or keeping their PDK format for compatibility with their OTP Writer, or have our own format, or a mix of these three things, or whatever :)
I think we should use the PDK format. The creation for a "liberated" WRITER seems to be the most difficult part which most likely will take the longest time.
>- if it makes sense to keep the ISA description open enough so that it can be imported by someone that wants to implement for instance an SDCC backend or a radare2 plugin to disasm, etc... or just keep it simple and hard coded in the tools
The ISA is so small and simple, everyone can adapt and implement it for a disasm within a few hours. So I think there is no need to be generic here.
>Also, regarding an hypothetical PC simulator (not real time, maybe cycle accurate, or even not) for debugging only:
Why "hypothetical PC simulator"? I finished this task already 8)
>- how that would be presented to the user, i.e.
>- a GUI? With what features? I/O interaction?
>- some kind of simulation you launch and outputs a waveform file in some standard format for inspection later (and that can also accept an input waveform file or some kind of description of what to do with the inputs - i.e. after 0.1s set PA.3 high etc...)
>- a command line tool like GDB where you can single step, inspect memory and regs, run, pause, etc...
>- a combination of some of the things above
>- ...
I was having a look at a 8051 emulator which uses ncurses ( https://github.com/jarikomppa/emu8051 ). This simulator I plan to repurpose for the front end.
>- we'll need our own init code if we want to create a full toolchain you can use from start to finish without touching PADAUK's tools, what should be done in that regard? Should we replicate PADAUK's code (eventually improving it) or do something else? Maybe have different init code options i.e. if you don't need precise clock speeds you can free up space by not having the calibration code, or you can chose to have it, you can have the ROM checksum or not, etc...
The init code is tied to the WRITER which I think we should stay compatible with (see comment above).
Usually this kind of things (init code) is implemented in include (.INC) files which the developer gets automatically in his project when he starts a new project (e.g. from a empty project template).
Then it up to the developer to modify / delete stuff from init code or use different/optimized implementations.
[…]
>Let me know what you think about my points and how we should proceed. If we can coordinate at least a bit the work that should be done (and how it should be done) I can start working on some tools.
Creating the assembler would be nice.
I really would love to have an assembler as soon as possible so I can automate tests for the simulator :-)
void xcode_pdk_data(TPDKinfo &info, bool encode)
{
if (info.length & 31) return; // Must be a multiple of 32 words
uint16_t const x0 = 0x55AA;
CKey key(info.key);
uint16_t x1 = key[3] ^ key[14];
uint16_t x2 = key[7] ^ key[15];
if ((info.version >= 0x15) && (info.version <= 0x17))
x1 ^= 0x1234, x2 ^= 0x5678;
uint16_t t1 = 0, t2 = 0;
unsigned ki = 0, n = 0;
uint16_t *d = info.data;
while (n < info.length) {
for (unsigned j = 0; j < 4; ++j) {
if (encode) {
t1 = *d++ = (*d - key[ki += x1]) ; key[ n] ^= t1;
t2 = *d++ = (*d ^ key[ki += t1]) - x2; key[x2] ^= x1;
x1 = *d++ = (*d - key[ki ^= t2]) ; key[x2] ^= x0;
x2 = *d++ = (*d ^ key[ki = kx(ki, x1)]) + t1;
t1 = *d++ = (*d ^ key[ki += x2]) ; key[x1] += x2;
t2 = *d++ = (*d ^ key[ki ^= t1]) ^ x2; key[t2] ^= t1;
x1 = *d++ = (*d - key[ki ^= t2]) ; key[t1] += t2;
x2 = *d++ = (*d ^ key[ki += x1]) - t1;
} else {
*d++ = ((t1 = *d) ) + key[ki += x1]; key[ n] ^= t1;
*d++ = ((t2 = *d) + x2) ^ key[ki += t1]; key[x2] ^= x1;
*d++ = ((x1 = *d) ) + key[ki ^= t2]; key[x2] ^= x0;
*d++ = ((x2 = *d) - t1) ^ key[ki = kx(ki, x1)];
*d++ = ((t1 = *d) ) ^ key[ki += x2]; key[x1] += x2;
*d++ = ((t2 = *d) ^ x2) ^ key[ki ^= t1]; key[t2] ^= t1;
*d++ = ((x1 = *d) ) + key[ki ^= t2]; key[t1] += t2;
*d++ = ((x2 = *d) + t1) ^ key[ki += x1];
}
key[1] ^= key[15]; key[2] ^= t1;
key[3] ^= key[14]; key[4] += t2;
key[5] ^= key[13]; key[6] += x2;
key[8] -= x1;
ki += j;
}
n += 32;
}
}
struct TPDKinfo
{
unsigned version;
unsigned length;
uint16_t *key;
uint16_t *data;
};
class CKey
{
private:
uint16_t k[16];
public:
CKey(uint16_t *_k) { memcpy(k, _k, sizeof(k)); }
inline uint16_t & operator [] (unsigned const i) { return k[i & 15]; }
};
static inline unsigned kx(unsigned const k, unsigned const i) { return ((k & 0xFFFF) + (i & 0xFFFF)) >> 1; }
/* xcode_pdk_data() goes here */
int get_pdk_info(uint8_t *bd, unsigned len, TPDKinfo &info)
{
// Note: this will only work on little endian CPUs due to the use of
// uint16_t and uint32_t reinterpret casts
memset(&info, 0, sizeof(info));
if (len < 256) return -1; // Header too short
uint16_t *wd = reinterpret_cast<uint16_t *>(bd); // Word (16 bit) data pointer
uint32_t *ld = reinterpret_cast<uint32_t *>(bd); // Long (32 bit) data pointer
uint32_t const version = ld[4 >> 1];
info.version = version;
uint32_t const datalen = ld[16 >> 1];
if (datalen & 31) return -2; // Data size is not a multiple of 32
info.length = datalen;
uint32_t const extrahdr = wd[0x13] + wd[0x14] + wd[0x16] + wd[0x68] + (version > 0x1C ? wd[0x24] >> 8 : 0);
if (extrahdr & 1) return -3; // Data is not word aligned
uint32_t const hdrlen = 256 + extrahdr;
if (len < hdrlen + (datalen << 1)) return -4; // Not enough data
info.key = wd + 0x70;
info.data = reinterpret_cast<uint16_t *>(bd + hdrlen);
return 0;
}
void decode_fw(uint16_t *d, unsigned len)
{
uint16_t const o[8] = { 0xAFCD, 0x0055, 0xAA23, 0x0055, 0x3759, 0x0055, 0xAA23, 0x0055 };
unsigned j = len << 3;
unsigned i = 0;
do *d++ ^= o[i & 7] ^ i++ ^ (j -= 8); while (j);
}
int main()
{
// Read a PDK file into memory
FILE *f;
errno_t e = fopen_s(&f, "test.pdk", "rb");
if (e) return -1;
uint8_t x[9000];
unsigned const l = fread(x, 1, sizeof(x), f);
fclose(f);
if (!l) return -2;
// Get info from the header
TPDKinfo info;
if (get_pdk_info(x, l, info)) return -3;
printf("PDK version: %i\nPDK data size: %i words\n", info.version, info.length);
// Decode it
xcode_pdk_data(info);
// Write the decoded file
e = fopen_s(&f, "test_decode.bin", "wb");
if (e) return -4;
fwrite(x, 1, l, f);
fclose(f);
// Encode it
xcode_pdk_data(info, true);
// Write the encoded file
e = fopen_s(&f, "test_encode.bin", "wb");
if (e) return -4;
fwrite(x, 1, l, f);
fclose(f);
return 0;
}
0000_0000_0000_0000 nop
0000_0000_0001_0000 addc a
0000_0000_0001_0001 subc a
0000_0000_0001_0010 izsn a
0000_0000_0001_0011 dzsn a
0000_0000_0001_0111 pcadd a
0000_0000_0001_1000 not a
0000_0000_0001_1001 neg a
0000_0000_0001_1010 sr a
0000_0000_0001_1011 sl a
0000_0000_0001_1100 src a
0000_0000_0001_1101 slc a
0000_0000_0001_1110 swap a
0000_0000_0001_1111 delay a
0000_0000_0011_0000 wdreset
0000_0000_0011_0010 pushaf
0000_0000_0011_0011 popaf
0000_0000_0011_0101 reset
0000_0000_0011_0110 stopsys
0000_0000_0011_0111 stopexe
0000_0000_0011_1000 engint
0000_0000_0011_1001 disgint
0000_0000_0011_1010 ret
0000_0000_0011_1011 reti
0000_0000_10pp_pppp mov IO,a
0000_0000_11pp_pppp mov a,IO
0000_0001_kkkk_kkkk cneqsn a,I
0000_001w_wwww_www0 stt16 word
0000_001w_wwww_www1 ldt16 word
0000_100w_wwww_www0 idxm index,a
0000_100w_wwww_www1 idxm a,index
0000_101w_wwww_www0 ldtabl word
0000_101w_wwww_www1 ldtabh word
0000_1110_kkkk_kkkk delay I
0000_1111_kkkk_kkkk ret I
0001_0000_00pp_pppp xor IO,a
0001_0000_01pp_pppp xor a,IO
0001_011m_mmmm_mmmm cneqsn a,M
0001_1000_kkkk_kkkk add a,I
0001_1001_kkkk_kkkk sub a,I
0001_1010_kkkk_kkkk ceqsn a,I
0001_1011_kkkk_kkkk comp a,I
0001_1100_kkkk_kkkk and a,I
0001_1101_kkkk_kkkk or a,I
0001_1110_kkkk_kkkk xor a,I
0001_1111_kkkk_kkkk mov a,I
0010_000b_bbpp_pppp t0sn IO.n
0010_001b_bbpp_pppp t1sn IO.n
0010_010b_bbpp_pppp set0 IO.n
0010_011b_bbpp_pppp set1 IO.n
0010_100b_bbpp_pppp tog IO.n
0010_101b_bbpp_pppp wait0 IO.n
0010_110b_bbpp_pppp wait1 IO.n
0010_111b_bbpp_pppp swapc IO.n
0011_000m_mmmm_mmmm nmov M,a
0011_001m_mmmm_mmmm nmov a,M
0011_010m_mmmm_mmmm nadd M,a
0011_011m_mmmm_mmmm nadd a,M
0011_100m_mmmm_mmmm ceqsn M,a
0011_101m_mmmm_mmmm ceqsn a,M
0011_110m_mmmm_mmmm comp M,a
0011_111m_mmmm_mmmm comp a,M
0100_000m_mmmm_mmmm add M,a
0100_001m_mmmm_mmmm add a,M
0100_011m_mmmm_mmmm sub a,M
0100_100m_mmmm_mmmm addc M,a
0100_101m_mmmm_mmmm addc a,M
0100_010m_mmmm_mmmm sub M,a
0100_111m_mmmm_mmmm subc a,M
0100_110m_mmmm_mmmm subc M,a
0101_000m_mmmm_mmmm and M,a
0101_001m_mmmm_mmmm and a,M
0101_010m_mmmm_mmmm or M,a
0101_011m_mmmm_mmmm or a,M
0101_100m_mmmm_mmmm xor M,a
0101_101m_mmmm_mmmm xor a,M
0101_110m_mmmm_mmmm mov M,a
0101_111m_mmmm_mmmm mov a,M
0110_000m_mmmm_mmmm addc M
0110_001m_mmmm_mmmm subc M
0110_010m_mmmm_mmmm izsn M
0110_011m_mmmm_mmmm dzsn M
0110_100m_mmmm_mmmm inc M
0110_101m_mmmm_mmmm dec M
0110_110m_mmmm_mmmm clear M
0110_111m_mmmm_mmmm xch M
0111_000m_mmmm_mmmm not M
0111_001m_mmmm_mmmm neg M
0111_010m_mmmm_mmmm sr M
0111_011m_mmmm_mmmm sl M
0111_100m_mmmm_mmmm src M
0111_101m_mmmm_mmmm slc M
0111_110m_mmmm_mmmm swap M
0111_111m_mmmm_mmmm delay M
1000_bbbm_mmmm_mmmm t0sn M.n
1001_bbbm_mmmm_mmmm t1sn M.n
1010_bbbm_mmmm_mmmm set0 M.n
1011_bbbm_mmmm_mmmm set1 M.n
110a_aaaa_aaaa_aaaa goto label
111a_aaaa_aaaa_aaaa call label
16 bit instruction set encoding used by PMS234
...Code: [Select]0000_0000_0001_1111 delay a
...
000 C002 goto 0x002
001 C049 goto 0x049
002 1F00 mov a,0x00
003 0082 mov SP,a
004 1F00 mov a,0x00
005 008B mov IHRCR,a
006 EFFD call 0x3FD
007 00B8 mov A_IHRC,a
008 1F3C mov a,0x3C
009 0083 mov CLKCMD,a
00A 1F0F mov a,0x0F
00B 5C01 mov M001,a
00C 1FFE mov a,0xFE
00D 5C00 mov M000,a
00E 0A00 ldtabl M000
00F 1AFF ceqsn a,0xFF
010 C040 goto 0x040
011 2791 set1 PAC.6
012 6C01 clear M001
013 1F20 mov a,0x20
014 5C00 mov M000,a
015 2D10 wait1 PA.4
016 2790 set1 PA.6
017 001F delay a
018 6600 dzsn M000
019 C017 goto 0x017
01A 2590 set0 PA.6
01B 2210 t1sn PA.0
01C C03C goto 0x03C
01D 1FA4 mov a,0xA4
01E 00A0 mov ADCC,a
01F 1F84 mov a,0x84
020 00A1 mov ADCM,a
021 1F80 mov a,0x80
022 5C00 mov M000,a
023 5E00 mov a,M000
024 00B9 mov BGTR,a
025 27A0 set1 ADCC.6
026 2DA0 wait1 ADCC.6
027 27A0 set1 ADCC.6
028 2DA0 wait1 ADCC.6
029 00E2 mov a,ADCRH
02A 5C01 mov M001,a
02B 00E3 mov a,ADCRL
02C 2CD0 wait1 PA.3
02D 001B sl a
02E 7A01 slc M001
02F 2F90 swapc PA.6
030 2AD0 wait0 PA.3
031 2010 t0sn PA.0
032 C02C goto 0x02C
033 2150 t0sn PA.5
034 C025 goto 0x025
035 1FBC mov a,0xBC
036 00A0 mov ADCC,a
037 21D0 t0sn PA.7
038 6800 inc M000
039 23D0 t1sn PA.7
03A 6A00 dec M000
03B C023 goto 0x023
03C 6801 inc M001
03D 5E01 mov a,M001
03E 008B mov IHRCR,a
03F C013 goto 0x013
040 008B mov IHRCR,a
041 0A01 ldtabh M000
042 00B9 mov BGTR,a
; FPPA0 User Code
043 1F00 mov a,0x00
044 0082 mov SP,a
045 0030 wdreset
046 0E64 delay 0x64
047 2810 tog PA.0
048 C045 goto 0x045
; FPPA1 User Code
049 1F04 mov a,0x04
04A 0082 mov SP,a
04B 0EC8 delay 0xC8
04C 2850 tog PA.1
04D C04B goto 0x04B
add a,I 1_0000_kkkk_kkkk 10_1000_kkkk_kkkk 0001_1000_kkkk_kkkk
add a,M 0_0110_00mm_mmmm 00_1100_0mmm_mmmm 0100_001m_mmmm_mmmm
add M,a 0_0100_00mm_mmmm 00_1000_0mmm_mmmm 0100_000m_mmmm_mmmm
addc a 0_0000_0001_0000 00_0000_0110_0000 0000_0000_0001_0000
addc a,M 0_0110_10mm_mmmm 00_1101_0mmm_mmmm 0100_101m_mmmm_mmmm
addc M 01_0000_0mmm_mmmm 0110_000m_mmmm_mmmm
addc M,a 0_0100_10mm_mmmm 00_1001_0mmm_mmmm 0100_100m_mmmm_mmmm
and a,I 1_0100_kkkk_kkkk 10_1100_kkkk_kkkk 0001_1100_kkkk_kkkk
and a,M 0_0111_00mm_mmmm 00_1110_0mmm_mmmm 0101_001m_mmmm_mmmm
and M,a 0_0101_00mm_mmmm 00_1010_0mmm_mmmm 0101_000m_mmmm_mmmm
call label 1_11aa_aaaa_aaaa 11_1aaa_aaaa_aaaa 111a_aaaa_aaaa_aaaa
ceqsn a,I 1_0010_kkkk_kkkk 10_1010_kkkk_kkkk 0001_1010_kkkk_kkkk
ceqsn a,M 0_1011_10mm_mmmm 01_0111_0mmm_mmmm 0011_101m_mmmm_mmmm
ceqsn M,a 0011_100m_mmmm_mmmm
clear M 0_1001_10mm_mmmm 01_0011_0mmm_mmmm 0110_110m_mmmm_mmmm
cneqsn a,I 10_1011_kkkk_kkkk 0000_0001_kkkk_kkkk
cneqsn a,M 01_0111_1mmm_mmmm 0001_011m_mmmm_mmmm
comp a,I 0001_1011_kkkk_kkkk
comp a,M 00_0110_0mmm_mmmm 0011_111m_mmmm_mmmm
comp M,a 00_0110_1mmm_mmmm 0011_110m_mmmm_mmmm
dec M 0_1001_01mm_mmmm 01_0010_1mmm_mmmm 0110_101m_mmmm_mmmm
delay a 0000_0000_0001_1111
delay I 0000_1110_kkkk_kkkk
delay M 0111_111m_mmmm_mmmm
disgint 0_0000_0011_1001 00_0000_0111_1001 0000_0000_0011_1001
dzsn a 0_0000_0001_0011 00_0000_0110_0011 0000_0000_0001_0011
dzsn M 0_1000_11mm_mmmm 01_0001_1mmm_mmmm 0110_011m_mmmm_mmmm
engint 0_0000_0011_1000 00_0000_0111_1000 0000_0000_0011_1000
goto label 1_10aa_aaaa_aaaa 11_0aaa_aaaa_aaaa 110a_aaaa_aaaa_aaaa
idxm a,index 0_0000_111w_www1 00_0011_1www_www1 0000_100w_wwww_www1
idxm index,a 0_0000_111w_www0 00_0011_1www_www0 0000_100w_wwww_www0
inc M 0_1001_00mm_mmmm 01_0010_0mmm_mmmm 0110_100m_mmmm_mmmm
izsn a 0_0000_0001_0010 00_0000_0110_0010 0000_0000_0001_0010
izsn M 0_1000_10mm_mmmm 01_0001_0mmm_mmmm 0110_010m_mmmm_mmmm
ldspth 00_0000_0000_0111
ldsptl 00_0000_0000_0110
ldt16 word 0_0000_110w_www1 00_0011_0www_www1 0000_001w_wwww_www1
ldtabh word 0000_101w_wwww_www1
ldtabl word 0000_101w_wwww_www0
mov a,I 1_0111_kkkk_kkkk 10_1111_kkkk_kkkk 0001_1111_kkkk_kkkk
mov a,IO 0_0000_101p_pppp 00_0001_11pp_pppp 0000_0000_11pp_pppp
mov a,M 0_0111_11mm_mmmm 00_1111_1mmm_mmmm 0101_111m_mmmm_mmmm
mov IO,a 0_0000_100p_pppp 00_0001_10pp_pppp 0000_0000_10pp_pppp
mov M,a 0_0101_11mm_mmmm 00_1011_1mmm_mmmm 0101_110m_mmmm_mmmm
mul 00_0000_0111_1100
nadd a,M 00_0111_0mmm_mmmm 0011_011m_mmmm_mmmm
nadd M,a 00_0111_1mmm_mmmm 0011_010m_mmmm_mmmm
neg a 0_0000_0001_1001 00_0000_0110_1001 0000_0000_0001_1001
neg M 0_1010_01mm_mmmm 01_0100_1mmm_mmmm 0111_001m_mmmm_mmmm
nmov a,M 0011_001m_mmmm_mmmm
nmov M,a 0011_000m_mmmm_mmmm
nop 0_0000_0000_0000 00_0000_0000_0000 0000_0000_0000_0000
not a 0_0000_0001_1000 00_0000_0110_1000 0000_0000_0001_1000
not M 0_1010_00mm_mmmm 01_0100_0mmm_mmmm 0111_000m_mmmm_mmmm
or a,I 1_0101_kkkk_kkkk 10_1101_kkkk_kkkk 0001_1101_kkkk_kkkk
or a,M 0_0111_01mm_mmmm 00_1110_1mmm_mmmm 0101_011m_mmmm_mmmm
or M,a 0_0101_01mm_mmmm 00_1010_1mmm_mmmm 0101_010m_mmmm_mmmm
pcadd a 0_0000_0001_0111 00_0000_0110_0111 0000_0000_0001_0111
popaf 0_0000_0011_0011 00_0000_0111_0011 0000_0000_0011_0011
pushaf 0_0000_0011_0010 00_0000_0111_0010 0000_0000_0011_0010
reset 0_0000_0011_0101 00_0000_0111_0101 0000_0000_0011_0101
ret 0_0000_0011_1010 00_0000_0111_1010 0000_0000_0011_1010
ret I 0_0001_kkkk_kkkk 00_0010_kkkk_kkkk 0000_1111_kkkk_kkkk
reti 0_0000_0011_1011 00_0000_0111_1011 0000_0000_0011_1011
set0 IO.n 0_1110_bbbp_pppp 01_110b_bbpp_pppp 0010_010b_bbpp_pppp
set0 M.n 0_0011_bbb0_mmmm 10_010b_bbmm_mmmm 1010_bbbm_mmmm_mmmm
set1 IO.n 0_1111_bbbp_pppp 01_111b_bbpp_pppp 0010_011b_bbpp_pppp
set1 M.n 0_0011_bbb1_mmmm 10_011b_bbmm_mmmm 1011_bbbm_mmmm_mmmm
sl a 0_0000_0001_1011 00_0000_0110_1011 0000_0000_0001_1011
sl M 0_1010_11mm_mmmm 01_0101_1mmm_mmmm 0111_011m_mmmm_mmmm
slc a 0_0000_0001_1101 00_0000_0110_1101 0000_0000_0001_1101
slc M 0_1011_01mm_mmmm 01_0110_1mmm_mmmm 0111_101m_mmmm_mmmm
sr a 0_0000_0001_1010 00_0000_0110_1010 0000_0000_0001_1010
sr M 0_1010_10mm_mmmm 01_0101_0mmm_mmmm 0111_010m_mmmm_mmmm
src a 0_0000_0001_1100 00_0000_0110_1100 0000_0000_0001_1100
src M 0_1011_00mm_mmmm 01_0110_0mmm_mmmm 0111_100m_mmmm_mmmm
stopexe 0_0000_0011_0111 00_0000_0111_0111 0000_0000_0011_0111
stopsys 0_0000_0011_0110 00_0000_0111_0110 0000_0000_0011_0110
stt16 word 0_0000_110w_www0 00_0011_0www_www0 0000_001w_wwww_www0
sub a,I 1_0001_kkkk_kkkk 10_1001_kkkk_kkkk 0001_1001_kkkk_kkkk
sub a,M 0_0110_01mm_mmmm 00_1100_1mmm_mmmm 0100_011m_mmmm_mmmm
sub M,a 0_0100_01mm_mmmm 00_1000_1mmm_mmmm 0100_010m_mmmm_mmmm
subc a 0_0000_0001_0001 00_0000_0110_0001 0000_0000_0001_0001
subc a,M 0_0110_11mm_mmmm 00_1101_1mmm_mmmm 0100_111m_mmmm_mmmm
subc M 01_0000_1mmm_mmmm 0110_001m_mmmm_mmmm
subc M,a 0_0100_11mm_mmmm 00_1001_1mmm_mmmm 0100_110m_mmmm_mmmm
swap a 0_0000_0001_1110 00_0000_0110_1110 0000_0000_0001_1110
swap M 0111_110m_mmmm_mmmm
swapc IO.n 00_010b_bbpp_pppp 0010_111b_bbpp_pppp
t0sn IO.n 0_1100_bbbp_pppp 01_100b_bbpp_pppp 0010_000b_bbpp_pppp
t0sn M.n 0_0010_bbb0_mmmm 10_000b_bbmm_mmmm 1000_bbbm_mmmm_mmmm
t1sn IO.n 0_1101_bbbp_pppp 01_101b_bbpp_pppp 0010_001b_bbpp_pppp
t1sn M.n 0_0010_bbb1_mmmm 10_001b_bbmm_mmmm 1001_bbbm_mmmm_mmmm
tog IO.n 0010_100b_bbpp_pppp
wait0 IO.n 0010_101b_bbpp_pppp
wait1 IO.n 0010_110b_bbpp_pppp
wdreset 0_0000_0011_0000 00_0000_0111_0000 0000_0000_0011_0000
xch M 0_1001_11mm_mmmm 01_0011_1mmm_mmmm 0110_111m_mmmm_mmmm
xor a,I 1_0110_kkkk_kkkk 10_1110_kkkk_kkkk 0001_1110_kkkk_kkkk
xor a,IO 0001_0000_01pp_pppp
xor a,M 0_0111_10mm_mmmm 00_1111_0mmm_mmmm 0101_101m_mmmm_mmmm
xor IO,a 0_0000_011p_pppp 00_0000_11pp_pppp 0001_0000_00pp_pppp
xor M,a 0_0101_10mm_mmmm 00_1011_0mmm_mmmm 0101_100m_mmmm_mmmm
A comparison of the 13, 14, and 16 bit instruction sets.
[…]
No immediately discernable obvious systema to the opcode layout besides the fixed position of the address/data fields --- I'd be really curious to see a decap of these MCUs, because the randomness of the assignment means they're probably implemented directly with a PLA and no microcode nor field-specific decoding.Ken Sherriff just did a teardown and decap of a flame lamp that uses a 16-pin unmarked MCU, which may or may not be a PADUK chip. Unfortunately no schematic to compare pinouts
What chip has those instructions? I used the PMC234 as a reference and it does not have them.
0x0400 popw word
0x0401 pushw word
0x0060 popw pcN
0x0070 pushw pcN
0x003C mul
.CHIP PDK82S_EV made more opcodes acceptable to the assemblerCode: [Select]0x0400 popw word
0x0401 pushw word
0x0060 popw pcN
0x0070 pushw pcN
0x003C mul
Looking for ideas on how to get the opcodes for 13 and 16 bit ldsptl/ldspth
0x0040 pmode n
0x0600 igoto word
0x0601 icall word
Code: [Select]0x0040 pmode n
0x0600 igoto word
0x0601 icall word
Not many gaps remaining in the 16 bit instruction set
Code: [Select]0x0040 pmode n
0x0600 igoto word
0x0601 icall word
Not many gaps remaining in the 16 bit instruction set
True, although I would consider calling this PDK_SYM_82A instruction set.
Could you also point out what chips you used for the other instruction sets?
If I counted correctly there are only these instruction set families
.Assembly ASM_INSTR SYM_83A
.Assembly ASM_INSTR SYM_84B
.Assembly ASM_INSTR SYM_85A
.Assembly ASM_INSTR SYM_86B
.Assembly ICE_INSTR SYM_83A
.Assembly ICE_INSTR SYM_86A
.Assembly INSTRUMENT SYM_82A
.Assembly INSTRUMENT SYM_83A
.Assembly INSTRUMENT SYM_86A
I suspect that INSTRUMENT means same for ASM and ICE
I have a startup file for the pfs154 that doesnt dissasemble correctly using the current sets, I suspect that 85A is still different from the others
.CHIP PFS154
//{{PADAUK_CODE_OPTION
.Code_Option LVR 2.5V
.Code_Option Security Enable // Security 7/8 words Enable
.Code_Option Comparator_Edge All_Edge
.Code_Option LCD2 Disable // At ICE, LCD always disable, PB0 PA0/3/4 are independent pins
.Code_Option Bootup_Time Fast
.Code_Option Drive Normal
//}}PADAUK_CODE_OPTION
goto FPPA0
WORD Stack_FPPA0 [2]
FPPA0:
.ADJUST_IC SYSCLK=IHRC/8, IHRC=16MHz, VDD=5V
SP = Stack_FPPA0;
@@:
wdreset
nop
goto @B
000 3001 goto 0x001
001 2F00 mov a,0x00
002 0182 mov SP,a
003 3FED call 0x7ED
004 018B mov IHRCR,a
005 3FEE call 0x7EE
006 019A mov BGTR,a
007 2F80 mov a,0x80
008 019B mov MISC_LVR,a
009 2F3C mov a,0x3C
00A 0183 mov CLKCMD,a
00B 3FFE call 0x7FE
00C 2AFF ceqsn a,0xFF
00D 3054 goto 0x054
00E 3FED call 0x7ED
00F 0B81 mov M01,a
010 1F91 set1 PAC.6
011 2F09 mov a,0x09
012 0B80 mov M00,a
013 1AD0 t1sn PA.3
014 3013 goto 0x013
015 1F90 set1 PA.6
016 0063 dzsn a
017 3016 goto 0x016
018 1180 dzsn M00
019 3016 goto 0x016
01A 1D90 set0 PA.6
01B 18D0 t0sn PA.3
01C 301B goto 0x01B
01D 2F01 mov a,0x01
01E 1950 t0sn PA.5
01F 2FFF mov a,0xFF
020 0C01 add a,M01
021 018B mov IHRCR,a
022 0B81 mov M01,a
023 1AD0 t1sn PA.3
024 3023 goto 0x023
025 1B50 t1sn PA.5
026 304F goto 0x04F
027 2F04 mov a,0x04
028 0188 mov MISC,a
029 18D0 t0sn PA.3
02A 3029 goto 0x029
02B 2F02 mov a,0x02
02C 0182 mov SP,a
02D 1304 clear M04
02E 1305 clear M05
02F 2F59 mov a,0x59
030 0B82 mov M02,a
031 2F00 mov a,0x00
032 0B83 mov M03,a
033 0006 ldsptl
034 0B04 xor M04,a
035 0007 ldspth
036 0805 add M05,a
037 1584 sl M04
038 1685 slc M05
039 1004 addc M04
03A 1282 dec M02
03B 1083 subc M03
03C 1A40 t1sn FLAG.1
03D 3033 goto 0x033
03E 1F90 set1 PA.6
03F 1AD0 t1sn PA.3
040 303F goto 0x03F
041 1584 sl M04
042 1685 slc M05
043 0590 swapc PA.6
044 18D0 t0sn PA.3
045 3044 goto 0x044
046 1950 t0sn PA.5
047 303F goto 0x03F
048 1D90 set0 PA.6
049 1AD0 t1sn PA.3
04A 3049 goto 0x049
04B 18D0 t0sn PA.3
04C 304B goto 0x04B
04D 1B50 t1sn PA.5
04E 302B goto 0x02B
04F 18D0 t0sn PA.3
050 304F goto 0x04F
051 1B50 t1sn PA.5
052 3011 goto 0x011
053 3053 goto 0x053
054 018B mov IHRCR,a
055 2F00 mov a,0x00
056 0182 mov SP,a
057 0070 wdreset
058 0000 nop
059 3057 goto 0x057
0x0000 0000_0000_0000_0000 nop
0x0001 0000_0000_0000_0001
0x0002 0000_0000_0000_0010
0x0003 0000_0000_0000_0011
0x0004 0000_0000_0000_0100
0x0005 0000_0000_0000_0101
0x0006 0000_0000_0000_0110
0x0007 0000_0000_0000_0111
0x0008 0000_0000_0000_1000
0x0009 0000_0000_0000_1001
0x000A 0000_0000_0000_1010
0x000B 0000_0000_0000_1011
0x000C 0000_0000_0000_1100
0x000D 0000_0000_0000_1101
0x000E 0000_0000_0000_1110
0x000F 0000_0000_0000_1111
0x0010 0000_0000_0001_0000 addc a
0x0011 0000_0000_0001_0001 subc a
0x0012 0000_0000_0001_0010 izsn a
0x0013 0000_0000_0001_0011 dzsn a
0x0014 0000_0000_0001_0100
0x0015 0000_0000_0001_0101
0x0016 0000_0000_0001_0110
0x0017 0000_0000_0001_0111 pcadd a
0x0018 0000_0000_0001_1000 not a
0x0019 0000_0000_0001_1001 neg a
0x001A 0000_0000_0001_1010 sr a
0x001B 0000_0000_0001_1011 sl a
0x001C 0000_0000_0001_1100 src a
0x001D 0000_0000_0001_1101 slc a
0x001E 0000_0000_0001_1110 swap a
0x001F 0000_0000_0001_1111 delay a
0x0020 0000_0000_0010_----
0x0030 0000_0000_0011_0000 wdreset
0x0031 0000_0000_0011_0001
0x0032 0000_0000_0011_0010 pushaf
0x0033 0000_0000_0011_0011 popaf
0x0034 0000_0000_0011_0100
0x0035 0000_0000_0011_0101 reset
0x0036 0000_0000_0011_0110 stopsys
0x0037 0000_0000_0011_0111 stopexe
0x0038 0000_0000_0011_1000 engint
0x0039 0000_0000_0011_1001 disgint
0x003A 0000_0000_0011_1010 ret
0x003B 0000_0000_0011_1011 reti
0x003C 0000_0000_0011_1100 mul
0x003D 0000_0000_0011_1101
0x003E 0000_0000_0011_1110
0x003F 0000_0000_0011_1111
0x0040 0000_0000_010k_kkkk pmode n
0x0060 0000_0000_0110_tttt popw pcN
0x0070 0000_0000_0111_tttt pushw pcN
0x0080 0000_0000_10pp_pppp mov IO,a
0x00C0 0000_0000_11pp_pppp mov a,IO
0x0100 0000_0001_kkkk_kkkk cneqsn a,I
0x0200 0000_001w_wwww_www0 stt16 word
0x0201 0000_001w_wwww_www1 ldt16 word
0x0400 0000_010w_wwww_www0 popw word
0x0401 0000_010w_wwww_www1 pushw word
0x0600 0000_011w_wwww_www0 igoto word
0x0601 0000_011w_wwww_www1 icall word
0x0800 0000_100w_wwww_www0 idxm index,a
0x0801 0000_100w_wwww_www1 idxm a,index
0x0A00 0000_101w_wwww_www0 ldtabl word
0x0A01 0000_101w_wwww_www1 ldtabh word
0x0C00 0000_110-_----_----
0x0E00 0000_1110_kkkk_kkkk delay I
0x0F00 0000_1111_kkkk_kkkk ret I
0x1000 0001_0000_00pp_pppp xor IO,a
0x1040 0001_0000_01pp_pppp xor a,IO
0x1080 0001_0000_1---_----
0x1100 0001_0001_----_----
0x1200 0001_001-_----_----
0x1400 0001_010m_mmmm_mmmm cneqsn M,a
0x1600 0001_011m_mmmm_mmmm cneqsn a,M
0x1800 0001_1000_kkkk_kkkk add a,I
0x1900 0001_1001_kkkk_kkkk sub a,I
0x1A00 0001_1010_kkkk_kkkk ceqsn a,I
0x1B00 0001_1011_kkkk_kkkk comp a,I
0x1C00 0001_1100_kkkk_kkkk and a,I
0x1D00 0001_1101_kkkk_kkkk or a,I
0x1E00 0001_1110_kkkk_kkkk xor a,I
0x1F00 0001_1111_kkkk_kkkk mov a,I
0x2000 0010_000b_bbpp_pppp t0sn IO.n
0x2200 0010_001b_bbpp_pppp t1sn IO.n
0x2400 0010_010b_bbpp_pppp set0 IO.n
0x2600 0010_011b_bbpp_pppp set1 IO.n
0x2800 0010_100b_bbpp_pppp tog IO.n
0x2A00 0010_101b_bbpp_pppp wait0 IO.n
0x2C00 0010_110b_bbpp_pppp wait1 IO.n
0x2E00 0010_111b_bbpp_pppp swapc IO.n
0x3000 0011_000m_mmmm_mmmm nmov M,a
0x3200 0011_001m_mmmm_mmmm nmov a,M
0x3400 0011_010m_mmmm_mmmm nadd M,a
0x3600 0011_011m_mmmm_mmmm nadd a,M
0x3800 0011_100m_mmmm_mmmm ceqsn M,a
0x3A00 0011_101m_mmmm_mmmm ceqsn a,M
0x3C00 0011_110m_mmmm_mmmm comp M,a
0x3E00 0011_111m_mmmm_mmmm comp a,M
0x4000 0100_000m_mmmm_mmmm add M,a
0x4200 0100_001m_mmmm_mmmm add a,M
0x4400 0100_010m_mmmm_mmmm sub M,a
0x4600 0100_011m_mmmm_mmmm sub a,M
0x4800 0100_100m_mmmm_mmmm addc M,a
0x4A00 0100_101m_mmmm_mmmm addc a,M
0x4C00 0100_110m_mmmm_mmmm subc M,a
0x4E00 0100_111m_mmmm_mmmm subc a,M
0x5000 0101_000m_mmmm_mmmm and M,a
0x5200 0101_001m_mmmm_mmmm and a,M
0x5400 0101_010m_mmmm_mmmm or M,a
0x5600 0101_011m_mmmm_mmmm or a,M
0x5800 0101_100m_mmmm_mmmm xor M,a
0x5A00 0101_101m_mmmm_mmmm xor a,M
0x5C00 0101_110m_mmmm_mmmm mov M,a
0x5E00 0101_111m_mmmm_mmmm mov a,M
0x6000 0110_000m_mmmm_mmmm addc M
0x6200 0110_001m_mmmm_mmmm subc M
0x6400 0110_010m_mmmm_mmmm izsn M
0x6600 0110_011m_mmmm_mmmm dzsn M
0x6800 0110_100m_mmmm_mmmm inc M
0x6A00 0110_101m_mmmm_mmmm dec M
0x6C00 0110_110m_mmmm_mmmm clear M
0x6E00 0110_111m_mmmm_mmmm xch M
0x7000 0111_000m_mmmm_mmmm not M
0x7200 0111_001m_mmmm_mmmm neg M
0x7400 0111_010m_mmmm_mmmm sr M
0x7600 0111_011m_mmmm_mmmm sl M
0x7800 0111_100m_mmmm_mmmm src M
0x7A00 0111_101m_mmmm_mmmm slc M
0x7C00 0111_110m_mmmm_mmmm swap M
0x7E00 0111_111m_mmmm_mmmm delay M
0x8000 1000_bbbm_mmmm_mmmm t0sn M.n
0x9000 1001_bbbm_mmmm_mmmm t1sn M.n
0xA000 1010_bbbm_mmmm_mmmm set0 M.n
0xB000 1011_bbbm_mmmm_mmmm set1 M.n
0xC000 110a_aaaa_aaaa_aaaa goto label
0xE000 111a_aaaa_aaaa_aaaa call label
0x0000 00_0000_0000_0000 nop
0x0001 00_0000_0000_0001
0x0002 00_0000_0000_0010
0x0003 00_0000_0000_0011
0x0004 00_0000_0000_0100
0x0005 00_0000_0000_0101
0x0006 00_0000_0000_0110 ldsptl
0x0007 00_0000_0000_0111 ldspth
0x0008 00_0000_0000_1---
0x0010 00_0000_0001_----
0x0020 00_0000_001-_----
0x0040 00_0000_010-_----
0x0060 00_0000_0110_0000 addc a
0x0061 00_0000_0110_0001 subc a
0x0062 00_0000_0110_0010 izsn a
0x0063 00_0000_0110_0011 dzsn a
0x0064 00_0000_0110_0100
0x0065 00_0000_0110_0101
0x0066 00_0000_0110_0110
0x0067 00_0000_0110_0111 pcadd a
0x0068 00_0000_0110_1000 not a
0x0069 00_0000_0110_1001 neg a
0x006a 00_0000_0110_1010 sr a
0x006b 00_0000_0110_1011 sl a
0x006c 00_0000_0110_1100 src a
0x006d 00_0000_0110_1101 slc a
0x006e 00_0000_0110_1110 swap a
0x006f 00_0000_0110_1111
0x0070 00_0000_0111_0000 wdreset
0x0071 00_0000_0111_0001
0x0072 00_0000_0111_0010 pushaf
0x0073 00_0000_0111_0011 popaf
0x0074 00_0000_0111_0100
0x0075 00_0000_0111_0101 reset
0x0076 00_0000_0111_0110 stopsys
0x0077 00_0000_0111_0111 stopexe
0x0078 00_0000_0111_1000 engint
0x0079 00_0000_0111_1001 disgint
0x007a 00_0000_0111_1010 ret
0x007b 00_0000_0111_1011 reti
0x007c 00_0000_0111_1100 mul
0x007d 00_0000_0111_1101
0x007e 00_0000_0111_1110
0x007f 00_0000_0111_1111
0x0080 00_0000_10--_----
0x00c0 00_0000_11pp_pppp xor io,a
0x0100 00_0001_00--_----
0x0140 00_0001_01--_----
0x0180 00_0001_10pp_pppp mov io,a
0x01c0 00_0001_11pp_pppp mov a,io
0x0200 00_0010_kkkk_kkkk ret k
0x0300 00_0011_0aaa_aaa0 stt16 m
0x0301 00_0011_0aaa_aaa1 ldt16 m
0x0380 00_0011_1aaa_aaa0 idxm m,a
0x0381 00_0011_1aaa_aaa1 idxm a,m
0x0400 00_010b_bbpp_pppp swapc io.b
0x0600 00_0110_0aaa_aaaa comp a,m
0x0680 00_0110 1aaa_aaaa comp m,a
0x0700 00_0111_0aaa_aaaa nadd a,m
0x0780 00_0111_1aaa_aaaa nadd m,a
0x0800 00_1000_0aaa_aaaa add m,a
0x0880 00_1000_1aaa_aaaa sub m,a
0x0900 00_1001_0aaa_aaaa addc m,a
0x0980 00_1001_1aaa_aaaa subc m,a
0x0a00 00_1010_0aaa_aaaa and m,a
0x0a80 00_1010_1aaa_aaaa or m,a
0x0b00 00_1011_0aaa_aaaa xor m,a
0x0b80 00_1011_1aaa_aaaa mov m,a
0x0c00 00_1100_0aaa_aaaa add a,m
0x0c80 00_1100_1aaa_aaaa sub a,m
0x0d00 00_1101_0aaa_aaaa addc a,m
0x0d80 00_1101_1aaa_aaaa subc a,m
0x0e00 00_1110_0aaa_aaaa and a,m
0x0e80 00_1110_1aaa_aaaa or a,m
0x0f00 00_1111_0aaa_aaaa xor a,m
0x0f80 00_1111_1aaa_aaaa mov a,m
0x1000 01_0000_0aaa_aaaa addc m
0x1080 01_0000_1aaa_aaaa subc m
0x1100 01_0001_0aaa_aaaa izsn m
0x1180 01_0001_1aaa_aaaa dzsn m
0x1200 01_0010_0aaa_aaaa inc m
0x1280 01_0010_1aaa_aaaa dec m
0x1300 01_0011_0aaa_aaaa clear m
0x1380 01_0011_1aaa_aaaa xch m
0x1400 01_0100_0aaa_aaaa not m
0x1480 01_0100_1aaa_aaaa neg m
0x1500 01_0101_0aaa_aaaa sr m
0x1580 01_0101_1aaa_aaaa sl m
0x1600 01_0110_0aaa_aaaa src m
0x1680 01_0110_1aaa_aaaa slc m
0x1700 01_0111_0aaa_aaaa ceqsn a,m
0x1780 01_0111_1aaa_aaaa cneqsn a,m
0x1800 01_100b_bbpp_pppp t0sn io.b
0x1a00 01_101b_bbpp_pppp t1sn io.b
0x1c00 01_110b_bbpp_pppp set0 io.b
0x1e00 01_111b_bbpp_pppp set1 io.b
0x2000 10_000b_bbaa_aaaa t0sn m.b
0x2200 10_001b_bbaa_aaaa t1sn m.b
0x2400 10_010b_bbaa_aaaa set0 m.b
0x2600 10_011b_bbaa_aaaa set1 m.b
0x2800 10_1000_dddd_dddd add a,k
0x2900 10_1001_dddd_dddd sub a,k
0x2a00 10_1010_dddd_dddd ceqsn a,k
0x2b00 10_1011_dddd_dddd cneqsn a,k
0x2c00 10_1100_dddd_dddd and a,k
0x2d00 10_1101_dddd_dddd or a,k
0x2e00 10_1110_dddd_dddd xor a,k
0x2f00 10_1111_dddd_dddd mov a,k
0x3000 11_0aaa_aaaa_aaaa goto k
0x3800 11_1aaa_aaaa_aaaa call k
0x0000 0_0000_0000_0000 nop
0x0001 0_0000_0000_0001
0x0002 0_0000_0000_0010
0x0003 0_0000_0000_0011
0x0004 0_0000_0000_0100
0x0005 0_0000_0000_0101
0x0006 0_0000_0000_0110
0x0007 0_0000_0000_0111
0x0008 0_0000_0000_1000
0x0009 0_0000_0000_1001
0x000a 0_0000_0000_1010
0x000b 0_0000_0000_1011
0x000c 0_0000_0000_1100
0x000d 0_0000_0000_1101
0x000e 0_0000_0000_1110
0x000f 0_0000_0000_1111
0x0010 0_0000_0001_0000 addc a
0x0011 0_0000_0001_0001 subc a
0x0012 0_0000_0001_0010 izsn a
0x0013 0_0000_0001_0011 dzsn a
0x0014 0_0000_0001_0100
0x0015 0_0000_0001_0101
0x0016 0_0000_0001_0110
0x0017 0_0000_0001_0111 pcadd a
0x0018 0_0000_0001_1000 not a
0x0019 0_0000_0001_1001 neg a
0x001a 0_0000_0001_1010 sr a
0x001b 0_0000_0001_1011 sl a
0x001c 0_0000_0001_1100 src a
0x001d 0_0000_0001_1101 slc a
0x001e 0_0000_0001_1110 swap a
0x001f 0_0000_0001_1111
0x0020 0_0000_0010_----
0x0030 0_0000_0011_0000 wdreset
0x0031 0_0000_0011_0001
0x0032 0_0000_0011_0010 pushaf
0x0033 0_0000_0011_0011 popaf
0x0034 0_0000_0011_0100
0x0035 0_0000_0011_0101 reset
0x0036 0_0000_0011_0110 stopsys
0x0037 0_0000_0011_0111 stopexe
0x0038 0_0000_0011_1000 engint
0x0039 0_0000_0011_1001 disgint
0x003a 0_0000_0011_1010 ret
0x003b 0_0000_0011_1011 reti
0x003c 0_0000_0011_1100
0x003d 0_0000_0011_1101
0x003e 0_0000_0011_1110
0x003f 0_0000_0011_1111
0x0040 0_0000_010-_----
0x0060 0_0000_011p_pppp xor io,a
0x0080 0_0000_100p_pppp mov io,a
0x00a0 0_0000_101p_pppp mov a,io
0x00c0 0_0000_110a_aaa0 stt16 m
0x00c1 0_0000_110a_aaa1 ldt16 m
0x00e0 0_0000_111a_aaa0 idxm m,a
0x00e1 0_0000_111a_aaa1 idxm a,m
0x0100 0_0001_dddd_dddd ret k
0x0200 0_0010_bbb0_aaaa t0sn m.b
0x0210 0_0010_bbb1_aaaa t1sn m.b
0x0300 0_0011_bbb0_aaaa set0 m.b
0x0310 0_0011_bbb1_aaaa set1 m.b
0x0400 0_0100_00aa_aaaa add m,a
0x0440 0_0100_01aa_aaaa sub m,a
0x0480 0_0100_10aa_aaaa addc m,a
0x04c0 0_0100_11aa_aaaa subc m,a
0x0500 0_0101_00aa_aaaa and m,a
0x0540 0_0101_01aa_aaaa or m,a
0x0580 0_0101_10aa_aaaa xor m,a
0x05c0 0_0101_11aa_aaaa mov m,a
0x0600 0_0110_00aa_aaaa add a,m
0x0640 0_0110_01aa_aaaa sub a,m
0x0680 0_0110_10aa_aaaa addc a,m
0x06c0 0_0110_11aa_aaaa subc a,m
0x0700 0_0111_00aa_aaaa and a,m
0x0740 0_0111_01aa_aaaa or a,m
0x0780 0_0111_10aa_aaaa xor a,m
0x07c0 0_0111_11aa_aaaa mov a,m
0x0800 0_1000_00aa_aaaa addc m
0x0840 0_1000_01aa_aaaa subc m
0x0880 0_1000_10aa_aaaa izsn m
0x08c0 0_1000_11aa_aaaa dzsn m
0x0900 0_1001_00aa_aaaa inc m
0x0940 0_1001_01aa_aaaa dec m
0x0980 0_1001_10aa_aaaa clear m
0x09c0 0_1001_11aa_aaaa xch m
0x0a00 0_1010_00aa_aaaa not m
0x0a40 0_1010_01aa_aaaa neg m
0x0a80 0_1010_10aa_aaaa sr m
0x0ac0 0_1010_11aa_aaaa sl m
0x0b00 0_1011_00aa_aaaa src m
0x0b40 0_1011_01aa_aaaa slc m
0x0b80 0_1011_10aa_aaaa ceqsn a,m
0x0bc0 0_1011_11aa_aaaa cneqsn a,m
0x0c00 0_1100_bbbp_pppp t0sn p.b
0x0d00 0_1101_bbbp_pppp t1sn p.b
0x0e00 0_1110_bbbp_pppp set0 p.b
0x0f00 0_1111_bbbp_pppp set1 p.b
0x1000 1_0000_dddd_dddd add a,k
0x1100 1_0001_dddd_dddd sub a,k
0x1200 1_0010_dddd_dddd ceqsn a,k
0x1300 1_0011_dddd_dddd cneqsn a,k
0x1400 1_0100_dddd_dddd and a,k
0x1500 1_0101_dddd_dddd or a,k
0x1600 1_0110_dddd_dddd xor a,k
0x1700 1_0111_dddd_dddd mov a,k
0x1800 1_10aa_aaaa_aaaa goto j
0x1c00 1_11aa_aaaa_aaaa call j
nop 0000_0000_0000_0000 00_0000_0000_0000 0_0000_0000_0000
ldsptl 00_0000_0000_0110
ldspth 00_0000_0000_0111
addc a 0000_0000_0001_0000 00_0000_0110_0000 0_0000_0001_0000
subc a 0000_0000_0001_0001 00_0000_0110_0001 0_0000_0001_0001
izsn a 0000_0000_0001_0010 00_0000_0110_0010 0_0000_0001_0010
dzsn a 0000_0000_0001_0011 00_0000_0110_0011 0_0000_0001_0011
pcadd a 0000_0000_0001_0111 00_0000_0110_0111 0_0000_0001_0111
not a 0000_0000_0001_1000 00_0000_0110_1000 0_0000_0001_1000
neg a 0000_0000_0001_1001 00_0000_0110_1001 0_0000_0001_1001
sr a 0000_0000_0001_1010 00_0000_0110_1010 0_0000_0001_1010
sl a 0000_0000_0001_1011 00_0000_0110_1011 0_0000_0001_1011
src a 0000_0000_0001_1100 00_0000_0110_1100 0_0000_0001_1100
slc a 0000_0000_0001_1101 00_0000_0110_1101 0_0000_0001_1101
swap a 0000_0000_0001_1110 00_0000_0110_1110 0_0000_0001_1110
delay a 0000_0000_0001_1111
wdreset 0000_0000_0011_0000 00_0000_0111_0000 0_0000_0011_0000
pushaf 0000_0000_0011_0010 00_0000_0111_0010 0_0000_0011_0010
popaf 0000_0000_0011_0011 00_0000_0111_0011 0_0000_0011_0011
reset 0000_0000_0011_0101 00_0000_0111_0101 0_0000_0011_0101
stopsys 0000_0000_0011_0110 00_0000_0111_0110 0_0000_0011_0110
stopexe 0000_0000_0011_0111 00_0000_0111_0111 0_0000_0011_0111
engint 0000_0000_0011_1000 00_0000_0111_1000 0_0000_0011_1000
disgint 0000_0000_0011_1001 00_0000_0111_1001 0_0000_0011_1001
ret 0000_0000_0011_1010 00_0000_0111_1010 0_0000_0011_1010
reti 0000_0000_0011_1011 00_0000_0111_1011 0_0000_0011_1011
mul 0000_0000_0011_1100 00_0000_0111_1100
pmode n 0000_0000_010k_kkkk
popw pcN 0000_0000_0110_tttt
pushw pcN 0000_0000_0111_tttt
mov IO,a 0000_0000_10pp_pppp 00_0001_10pp_pppp 0_0000_100p_pppp
mov a,IO 0000_0000_11pp_pppp 00_0001_11pp_pppp 0_0000_101p_pppp
cneqsn a,I 0000_0001_kkkk_kkkk 10_1011_kkkk_kkkk 1_0011_kkkk_kkkk
stt16 word 0000_001w_wwww_www0 00_0011_0www_www0 0_0000_110w_www0
ldt16 word 0000_001w_wwww_www1 00_0011_0www_www1 0_0000_110w_www1
popw word 0000_010w_wwww_www0
pushw word 0000_010w_wwww_www1
igoto word 0000_011w_wwww_www0
icall word 0000_011w_wwww_www1
idxm index,a 0000_100w_wwww_www0 00_0011_1www_www0 0_0000_111w_www0
idxm a,index 0000_100w_wwww_www1 00_0011_1www_www1 0_0000_111w_www1
ldtabl word 0000_101w_wwww_www0
ldtabh word 0000_101w_wwww_www1
delay I 0000_1110_kkkk_kkkk
ret I 0000_1111_kkkk_kkkk 00_0010_kkkk_kkkk 0_0001_kkkk_kkkk
xor IO,a 0001_0000_00pp_pppp 00_0000_11pp_pppp 0_0000_011p_pppp
xor a,IO 0001_0000_01pp_pppp
cneqsn M,a 0001_010m_mmmm_mmmm
cneqsn a,M 0001_011m_mmmm_mmmm 01_0111_1mmm_mmmm 0_1011_11mm_mmmm
add a,I 0001_1000_kkkk_kkkk 10_1000_kkkk_kkkk 1_0000_kkkk_kkkk
sub a,I 0001_1001_kkkk_kkkk 10_1001_kkkk_kkkk 1_0001_kkkk_kkkk
ceqsn a,I 0001_1010_kkkk_kkkk 10_1010_kkkk_kkkk 1_0010_kkkk_kkkk
comp a,I 0001_1011_kkkk_kkkk
and a,I 0001_1100_kkkk_kkkk 10_1100_kkkk_kkkk 1_0100_kkkk_kkkk
or a,I 0001_1101_kkkk_kkkk 10_1101_kkkk_kkkk 1_0101_kkkk_kkkk
xor a,I 0001_1110_kkkk_kkkk 10_1110_kkkk_kkkk 1_0110_kkkk_kkkk
mov a,I 0001_1111_kkkk_kkkk 10_1111_kkkk_kkkk 1_0111_kkkk_kkkk
t0sn IO.n 0010_000b_bbpp_pppp 01_100b_bbpp_pppp 0_1100_bbbp_pppp
t1sn IO.n 0010_001b_bbpp_pppp 01_101b_bbpp_pppp 0_1101_bbbp_pppp
set0 IO.n 0010_010b_bbpp_pppp 01_110b_bbpp_pppp 0_1110_bbbp_pppp
set1 IO.n 0010_011b_bbpp_pppp 01_111b_bbpp_pppp 0_1111_bbbp_pppp
tog IO.n 0010_100b_bbpp_pppp
wait0 IO.n 0010_101b_bbpp_pppp
wait1 IO.n 0010_110b_bbpp_pppp
swapc IO.n 0010_111b_bbpp_pppp 00_010b_bbpp_pppp
nmov M,a 0011_000m_mmmm_mmmm
nmov a,M 0011_001m_mmmm_mmmm
nadd M,a 0011_010m_mmmm_mmmm 00_0111_1mmm_mmmm
nadd a,M 0011_011m_mmmm_mmmm 00_0111_0mmm_mmmm
ceqsn M,a 0011_100m_mmmm_mmmm
ceqsn a,M 0011_101m_mmmm_mmmm 01_0111_0mmm_mmmm 0_1011_10mm_mmmm
comp M,a 0011_110m_mmmm_mmmm 00_0110_1mmm_mmmm
comp a,M 0011_111m_mmmm_mmmm 00_0110_0mmm_mmmm
add M,a 0100_000m_mmmm_mmmm 00_1000_0mmm_mmmm 0_0100_00mm_mmmm
add a,M 0100_001m_mmmm_mmmm 00_1100_0mmm_mmmm 0_0110_00mm_mmmm
sub M,a 0100_010m_mmmm_mmmm 00_1000_1mmm_mmmm 0_0100_01mm_mmmm
sub a,M 0100_011m_mmmm_mmmm 00_1100_1mmm_mmmm 0_0110_01mm_mmmm
addc M,a 0100_100m_mmmm_mmmm 00_1001_0mmm_mmmm 0_0100_10mm_mmmm
addc a,M 0100_101m_mmmm_mmmm 00_1101_0mmm_mmmm 0_0110_10mm_mmmm
subc M,a 0100_110m_mmmm_mmmm 00_1001_1mmm_mmmm 0_0100_11mm_mmmm
subc a,M 0100_111m_mmmm_mmmm 00_1101_1mmm_mmmm 0_0110_11mm_mmmm
and M,a 0101_000m_mmmm_mmmm 00_1010_0mmm_mmmm 0_0101_00mm_mmmm
and a,M 0101_001m_mmmm_mmmm 00_1110_0mmm_mmmm 0_0111_00mm_mmmm
or M,a 0101_010m_mmmm_mmmm 00_1010_1mmm_mmmm 0_0101_01mm_mmmm
or a,M 0101_011m_mmmm_mmmm 00_1110_1mmm_mmmm 0_0111_01mm_mmmm
xor M,a 0101_100m_mmmm_mmmm 00_1011_0mmm_mmmm 0_0101_10mm_mmmm
xor a,M 0101_101m_mmmm_mmmm 00_1111_0mmm_mmmm 0_0111_10mm_mmmm
mov M,a 0101_110m_mmmm_mmmm 00_1011_1mmm_mmmm 0_0101_11mm_mmmm
mov a,M 0101_111m_mmmm_mmmm 00_1111_1mmm_mmmm 0_0111_11mm_mmmm
addc M 0110_000m_mmmm_mmmm 01_0000_0mmm_mmmm 0_1000_00mm_mmmm
subc M 0110_001m_mmmm_mmmm 01_0000_1mmm_mmmm 0_1000_01mm_mmmm
izsn M 0110_010m_mmmm_mmmm 01_0001_0mmm_mmmm 0_1000_10mm_mmmm
dzsn M 0110_011m_mmmm_mmmm 01_0001_1mmm_mmmm 0_1000_11mm_mmmm
inc M 0110_100m_mmmm_mmmm 01_0010_0mmm_mmmm 0_1001_00mm_mmmm
dec M 0110_101m_mmmm_mmmm 01_0010_1mmm_mmmm 0_1001_01mm_mmmm
clear M 0110_110m_mmmm_mmmm 01_0011_0mmm_mmmm 0_1001_10mm_mmmm
xch M 0110_111m_mmmm_mmmm 01_0011_1mmm_mmmm 0_1001_11mm_mmmm
not M 0111_000m_mmmm_mmmm 01_0100_0mmm_mmmm 0_1010_00mm_mmmm
neg M 0111_001m_mmmm_mmmm 01_0100_1mmm_mmmm 0_1010_01mm_mmmm
sr M 0111_010m_mmmm_mmmm 01_0101_0mmm_mmmm 0_1010_10mm_mmmm
sl M 0111_011m_mmmm_mmmm 01_0101_1mmm_mmmm 0_1010_11mm_mmmm
src M 0111_100m_mmmm_mmmm 01_0110_0mmm_mmmm 0_1011_00mm_mmmm
slc M 0111_101m_mmmm_mmmm 01_0110_1mmm_mmmm 0_1011_01mm_mmmm
swap M 0111_110m_mmmm_mmmm
delay M 0111_111m_mmmm_mmmm
t0sn M.n 1000_bbbm_mmmm_mmmm 10_000b_bbmm_mmmm 0_0010_bbb0_mmmm
t1sn M.n 1001_bbbm_mmmm_mmmm 10_001b_bbmm_mmmm 0_0010_bbb1_mmmm
set0 M.n 1010_bbbm_mmmm_mmmm 10_010b_bbmm_mmmm 0_0011_bbb0_mmmm
set1 M.n 1011_bbbm_mmmm_mmmm 10_011b_bbmm_mmmm 0_0011_bbb1_mmmm
goto label 110a_aaaa_aaaa_aaaa 11_0aaa_aaaa_aaaa 1_10aa_aaaa_aaaa
call label 111a_aaaa_aaaa_aaaa 11_1aaa_aaaa_aaaa 1_11aa_aaaa_aaaa
add a,I 0001_1000_kkkk_kkkk 10_1000_kkkk_kkkk 1_0000_kkkk_kkkk
add a,M 0100_001m_mmmm_mmmm 00_1100_0mmm_mmmm 0_0110_00mm_mmmm
add M,a 0100_000m_mmmm_mmmm 00_1000_0mmm_mmmm 0_0100_00mm_mmmm
addc a 0000_0000_0001_0000 00_0000_0110_0000 0_0000_0001_0000
addc a,M 0100_101m_mmmm_mmmm 00_1101_0mmm_mmmm 0_0110_10mm_mmmm
addc M 0110_000m_mmmm_mmmm 01_0000_0mmm_mmmm 0_1000_00mm_mmmm
addc M,a 0100_100m_mmmm_mmmm 00_1001_0mmm_mmmm 0_0100_10mm_mmmm
and a,I 0001_1100_kkkk_kkkk 10_1100_kkkk_kkkk 1_0100_kkkk_kkkk
and a,M 0101_001m_mmmm_mmmm 00_1110_0mmm_mmmm 0_0111_00mm_mmmm
and M,a 0101_000m_mmmm_mmmm 00_1010_0mmm_mmmm 0_0101_00mm_mmmm
call label 111a_aaaa_aaaa_aaaa 11_1aaa_aaaa_aaaa 1_11aa_aaaa_aaaa
ceqsn a,I 0001_1010_kkkk_kkkk 10_1010_kkkk_kkkk 1_0010_kkkk_kkkk
ceqsn a,M 0011_101m_mmmm_mmmm 01_0111_0mmm_mmmm 0_1011_10mm_mmmm
ceqsn M,a 0011_100m_mmmm_mmmm
clear M 0110_110m_mmmm_mmmm 01_0011_0mmm_mmmm 0_1001_10mm_mmmm
cneqsn a,I 0000_0001_kkkk_kkkk 10_1011_kkkk_kkkk 1_0011_kkkk_kkkk
cneqsn a,M 0001_011m_mmmm_mmmm 01_0111_1mmm_mmmm 0_1011_11mm_mmmm
cneqsn M,a 0001_010m_mmmm_mmmm
comp a,I 0001_1011_kkkk_kkkk
comp a,M 0011_111m_mmmm_mmmm 00_0110_0mmm_mmmm
comp M,a 0011_110m_mmmm_mmmm 00_0110_1mmm_mmmm
dec M 0110_101m_mmmm_mmmm 01_0010_1mmm_mmmm 0_1001_01mm_mmmm
delay a 0000_0000_0001_1111
delay I 0000_1110_kkkk_kkkk
delay M 0111_111m_mmmm_mmmm
disgint 0000_0000_0011_1001 00_0000_0111_1001 0_0000_0011_1001
dzsn a 0000_0000_0001_0011 00_0000_0110_0011 0_0000_0001_0011
dzsn M 0110_011m_mmmm_mmmm 01_0001_1mmm_mmmm 0_1000_11mm_mmmm
engint 0000_0000_0011_1000 00_0000_0111_1000 0_0000_0011_1000
goto label 110a_aaaa_aaaa_aaaa 11_0aaa_aaaa_aaaa 1_10aa_aaaa_aaaa
icall word 0000_011w_wwww_www1
idxm a,index 0000_100w_wwww_www1 00_0011_1www_www1 0_0000_111w_www1
idxm index,a 0000_100w_wwww_www0 00_0011_1www_www0 0_0000_111w_www0
igoto word 0000_011w_wwww_www0
inc M 0110_100m_mmmm_mmmm 01_0010_0mmm_mmmm 0_1001_00mm_mmmm
izsn a 0000_0000_0001_0010 00_0000_0110_0010 0_0000_0001_0010
izsn M 0110_010m_mmmm_mmmm 01_0001_0mmm_mmmm 0_1000_10mm_mmmm
ldspth 00_0000_0000_0111
ldsptl 00_0000_0000_0110
ldt16 word 0000_001w_wwww_www1 00_0011_0www_www1 0_0000_110w_www1
ldtabh word 0000_101w_wwww_www1
ldtabl word 0000_101w_wwww_www0
mov a,I 0001_1111_kkkk_kkkk 10_1111_kkkk_kkkk 1_0111_kkkk_kkkk
mov a,IO 0000_0000_11pp_pppp 00_0001_11pp_pppp 0_0000_101p_pppp
mov a,M 0101_111m_mmmm_mmmm 00_1111_1mmm_mmmm 0_0111_11mm_mmmm
mov IO,a 0000_0000_10pp_pppp 00_0001_10pp_pppp 0_0000_100p_pppp
mov M,a 0101_110m_mmmm_mmmm 00_1011_1mmm_mmmm 0_0101_11mm_mmmm
mul 0000_0000_0011_1100 00_0000_0111_1100
nadd a,M 0011_011m_mmmm_mmmm 00_0111_0mmm_mmmm
nadd M,a 0011_010m_mmmm_mmmm 00_0111_1mmm_mmmm
neg a 0000_0000_0001_1001 00_0000_0110_1001 0_0000_0001_1001
neg M 0111_001m_mmmm_mmmm 01_0100_1mmm_mmmm 0_1010_01mm_mmmm
nmov a,M 0011_001m_mmmm_mmmm
nmov M,a 0011_000m_mmmm_mmmm
nop 0000_0000_0000_0000 00_0000_0000_0000 0_0000_0000_0000
not a 0000_0000_0001_1000 00_0000_0110_1000 0_0000_0001_1000
not M 0111_000m_mmmm_mmmm 01_0100_0mmm_mmmm 0_1010_00mm_mmmm
or a,I 0001_1101_kkkk_kkkk 10_1101_kkkk_kkkk 1_0101_kkkk_kkkk
or a,M 0101_011m_mmmm_mmmm 00_1110_1mmm_mmmm 0_0111_01mm_mmmm
or M,a 0101_010m_mmmm_mmmm 00_1010_1mmm_mmmm 0_0101_01mm_mmmm
pcadd a 0000_0000_0001_0111 00_0000_0110_0111 0_0000_0001_0111
pmode n 0000_0000_010k_kkkk
popaf 0000_0000_0011_0011 00_0000_0111_0011 0_0000_0011_0011
popw pcN 0000_0000_0110_tttt
popw word 0000_010w_wwww_www0
pushaf 0000_0000_0011_0010 00_0000_0111_0010 0_0000_0011_0010
pushw pcN 0000_0000_0111_tttt
pushw word 0000_010w_wwww_www1
reset 0000_0000_0011_0101 00_0000_0111_0101 0_0000_0011_0101
ret 0000_0000_0011_1010 00_0000_0111_1010 0_0000_0011_1010
ret I 0000_1111_kkkk_kkkk 00_0010_kkkk_kkkk 0_0001_kkkk_kkkk
reti 0000_0000_0011_1011 00_0000_0111_1011 0_0000_0011_1011
set0 IO.n 0010_010b_bbpp_pppp 01_110b_bbpp_pppp 0_1110_bbbp_pppp
set0 M.n 1010_bbbm_mmmm_mmmm 10_010b_bbmm_mmmm 0_0011_bbb0_mmmm
set1 IO.n 0010_011b_bbpp_pppp 01_111b_bbpp_pppp 0_1111_bbbp_pppp
set1 M.n 1011_bbbm_mmmm_mmmm 10_011b_bbmm_mmmm 0_0011_bbb1_mmmm
sl a 0000_0000_0001_1011 00_0000_0110_1011 0_0000_0001_1011
sl M 0111_011m_mmmm_mmmm 01_0101_1mmm_mmmm 0_1010_11mm_mmmm
slc a 0000_0000_0001_1101 00_0000_0110_1101 0_0000_0001_1101
slc M 0111_101m_mmmm_mmmm 01_0110_1mmm_mmmm 0_1011_01mm_mmmm
sr a 0000_0000_0001_1010 00_0000_0110_1010 0_0000_0001_1010
sr M 0111_010m_mmmm_mmmm 01_0101_0mmm_mmmm 0_1010_10mm_mmmm
src a 0000_0000_0001_1100 00_0000_0110_1100 0_0000_0001_1100
src M 0111_100m_mmmm_mmmm 01_0110_0mmm_mmmm 0_1011_00mm_mmmm
stopexe 0000_0000_0011_0111 00_0000_0111_0111 0_0000_0011_0111
stopsys 0000_0000_0011_0110 00_0000_0111_0110 0_0000_0011_0110
stt16 word 0000_001w_wwww_www0 00_0011_0www_www0 0_0000_110w_www0
sub a,I 0001_1001_kkkk_kkkk 10_1001_kkkk_kkkk 1_0001_kkkk_kkkk
sub a,M 0100_011m_mmmm_mmmm 00_1100_1mmm_mmmm 0_0110_01mm_mmmm
sub M,a 0100_010m_mmmm_mmmm 00_1000_1mmm_mmmm 0_0100_01mm_mmmm
subc a 0000_0000_0001_0001 00_0000_0110_0001 0_0000_0001_0001
subc a,M 0100_111m_mmmm_mmmm 00_1101_1mmm_mmmm 0_0110_11mm_mmmm
subc M 0110_001m_mmmm_mmmm 01_0000_1mmm_mmmm 0_1000_01mm_mmmm
subc M,a 0100_110m_mmmm_mmmm 00_1001_1mmm_mmmm 0_0100_11mm_mmmm
swap a 0000_0000_0001_1110 00_0000_0110_1110 0_0000_0001_1110
swap M 0111_110m_mmmm_mmmm
swapc IO.n 0010_111b_bbpp_pppp 00_010b_bbpp_pppp
t0sn IO.n 0010_000b_bbpp_pppp 01_100b_bbpp_pppp 0_1100_bbbp_pppp
t0sn M.n 1000_bbbm_mmmm_mmmm 10_000b_bbmm_mmmm 0_0010_bbb0_mmmm
t1sn IO.n 0010_001b_bbpp_pppp 01_101b_bbpp_pppp 0_1101_bbbp_pppp
t1sn M.n 1001_bbbm_mmmm_mmmm 10_001b_bbmm_mmmm 0_0010_bbb1_mmmm
tog IO.n 0010_100b_bbpp_pppp
wait0 IO.n 0010_101b_bbpp_pppp
wait1 IO.n 0010_110b_bbpp_pppp
wdreset 0000_0000_0011_0000 00_0000_0111_0000 0_0000_0011_0000
xch M 0110_111m_mmmm_mmmm 01_0011_1mmm_mmmm 0_1001_11mm_mmmm
xor a,I 0001_1110_kkkk_kkkk 10_1110_kkkk_kkkk 1_0110_kkkk_kkkk
xor a,IO 0001_0000_01pp_pppp
xor a,M 0101_101m_mmmm_mmmm 00_1111_0mmm_mmmm 0_0111_10mm_mmmm
xor IO,a 0001_0000_00pp_pppp 00_0000_11pp_pppp 0_0000_011p_pppp
xor M,a 0101_100m_mmmm_mmmm 00_1011_0mmm_mmmm 0_0101_10mm_mmmm
[…]
If I counted correctly there are only these instruction set families
.Assembly ASM_INSTR SYM_83A
.Assembly ASM_INSTR SYM_84B
.Assembly ASM_INSTR SYM_85A
.Assembly ASM_INSTR SYM_86B
.Assembly ICE_INSTR SYM_83A
.Assembly ICE_INSTR SYM_86A
.Assembly INSTRUMENT SYM_82A
.Assembly INSTRUMENT SYM_83A
.Assembly INSTRUMENT SYM_86A
I suspect that INSTRUMENT means same for ASM and ICE
Do we have any idea if the Padauk Programmer supports on-target debugging in any way?
Philipp
Disassembler for all Padauk MCUs.
Usage: pdisasm pdk [io_symbols [mem_symbols]]
To show instruction set: pdisasm 13 | 14 | 16 | all
--- original/padauk_disasm.cpp 2018-12-01 11:25:20.595205297 +0100
+++ padauk_disasm.cpp 2018-12-01 13:31:07.148535905 +0100
@@ -1,11 +1,11 @@
-
-#include "stdafx.h"
+#include <string.h>
+#include <stdlib.h>
#include "pdk.h"
#include "disasm.h"
-int main(int argc, char **argv)
-{
+int
+main(int argc, char **argv) {
if (argc < 2) {
printf("Usage: pdisasm pdk [ io_symbols [ mem_symbols] ]\n");
return 0;
@@ -30,10 +30,17 @@
auto d = CPadaukDisasm::New(pdk.bits);
if (!d) { printf("Unsupported core (%i bits)\n", pdk.bits); return -2; }
- if (argc > 2) d->io_symbols.ReadFile(argv[2]);
+ if (argc > 2) {
+ d->io_symbols.ReadFile(argv[2]);
+ } else {
+ char fname[17] = {};
+ sprintf(fname, "sym_io_%d.txt", pdk.bits);
+ d->io_symbols.ReadFile(fname);
+ }
+
if (argc > 3) d->mem_symbols.ReadFile(argv[3]);
d->disasm(pdk);
}
- return 0;
+ return 0;
}
I have a startup file for the pfs154 that doesnt dissasemble correctly using the current sets, I suspect that 85A is still different from the others
I have a startup file for the pfs154 that doesnt dissasemble correctly using the current sets, I suspect that 85A is still different from the others
Has this been resolved? Do we know if there are encoding differences within the individual 13-Bit / 14-Bit / 16_ Bit instruction sets (apart from differences in the supported subset of instructions)?
In particular: Can we be reasonably sure that the 14-Bit instruction set at https://free-pdk.github.io/PADAUK_FPPA_14_bit_instruction_set.html reflects the actual encoding for the PFS154?
Philipp
PDK version: 20
PDK data size: 2048 words
Free data size: 2016 words
MCU: PFS154 [ID: 0x2AA1]
Compiler version: 0.83B17
14 bit core
0000 0070 wdreset
0001 2F00 mov a, 0x00
0002 0182 mov SP, a
0003 3FED call 0x07ED
0004 018B mov IHRCR, a
0005 3FEE call 0x07EE
0006 019A mov BGTR, a
0007 2F20 mov a, 0x20
0008 019B mov MISC_LVR, a
0009 2F34 mov a, 0x34
000A 0183 mov CLKCMD, a
000B 3FFE call 0x07FE
000C 2AFF ceqsn a, 0xFF
000D 3054 goto 0x0054
000E 3FED call 0x07ED
000F 0B81 mov M1, a
0010 1F91 set1 PAC.6
0011 2F20 mov a, 0x20
0012 0B80 mov M0, a
0013 1AD0 t1sn PA.3
0014 3013 goto 0x0013
0015 1F90 set1 PA.6
0016 0063 dzsn a
0017 3016 goto 0x0016
0018 1180 dzsn M0
0019 3016 goto 0x0016
001A 1D90 set0 PA.6
001B 18D0 t0sn PA.3
001C 301B goto 0x001B
001D 2F01 mov a, 0x01
001E 1950 t0sn PA.5
001F 2FFF mov a, 0xFF
0020 0C01 add a, M1
0021 018B mov IHRCR, a
0022 0B81 mov M1, a
0023 1AD0 t1sn PA.3
0024 3023 goto 0x0023
0025 1B50 t1sn PA.5
0026 304F goto 0x004F
0027 2F04 mov a, 0x04
0028 0188 mov MISC, a
0029 18D0 t0sn PA.3
002A 3029 goto 0x0029
002B 2F02 mov a, 0x02
002C 0182 mov SP, a
002D 1304 clear M4
002E 1305 clear M5
002F 2F5E mov a, 0x5E
0030 0B82 mov M2, a
0031 2F00 mov a, 0x00
0032 0B83 mov M3, a
0033 0006 ldsptl
0034 0B04 xor M4, a
0035 0007 ldspth
0036 0805 add M5, a
0037 1584 sl M4
0038 1685 slc M5
0039 1004 addc M4
003A 1282 dec M2
003B 1083 subc M3
003C 1A40 t1sn FLAG.C
003D 3033 goto 0x0033
003E 1F90 set1 PA.6
003F 1AD0 t1sn PA.3
0040 303F goto 0x003F
0041 1584 sl M4
0042 1685 slc M5
0043 0590 swapc PA.6
0044 18D0 t0sn PA.3
0045 3044 goto 0x0044
0046 1950 t0sn PA.5
0047 303F goto 0x003F
0048 1D90 set0 PA.6
0049 1AD0 t1sn PA.3
004A 3049 goto 0x0049
004B 18D0 t0sn PA.3
004C 304B goto 0x004B
004D 1B50 t1sn PA.5
004E 302B goto 0x002B
004F 18D0 t0sn PA.3
0050 304F goto 0x004F
0051 1B50 t1sn PA.5
0052 3011 goto 0x0011
0053 3053 goto 0x0053
0054 018B mov IHRCR, a
0055 0000 nop // here a nop/wdreset pattern starts so that I can recognize my code
0056 0070 wdreset
0057 0000 nop
0058 0070 wdreset
0059 0000 nop
005A 0070 wdreset
005B 0000 nop
005C 0070 wdreset
005D 0000 nop
005E 3055 goto 0x0055
.... // all other locations are 3FFF
07EF 1FFE set1 GPCC.7
07F0 3FFF call 0x07FF
07F1 3FFF call 0x07FF
07F2 3FFF call 0x07FF
07F3 3FFF call 0x07FF
07F4 3FFF call 0x07FF
07F5 3FFF call 0x07FF
07F6 3FFF call 0x07FF
07F7 3FFF call 0x07FF
07F8 0000 nop
07F9 0000 nop
07FA 3FFF call 0x07FF
07FB 3FFF call 0x07FF
07FC 3FFF call 0x07FF
07FD 3FFF call 0x07FF
07FE 3FFF call 0x07FF
07FF 3DFD call 0x05FD
6000 goto 0x0000
6FFF goto 0x0FFF
7000 call 0x0000
7FFF call 0x0FFF
Today, I made a first step to inefficently compiling a small subset of C to Padauk asm code. The current version is very restricted and generates very inefficient code; it is untested.
There is no assembler / linker support, so the resulting .asm file has to be assembled in other ways.
[…]
Code in svn at https://svn.code.sf.net/p/sdcc/code/branches/pdk/sdcc, use -mpdk14 to target Padauk (despite the name, the set of instructions emitted is part of the common subset of the Padauk instruction sets).
Has this been resolved? Do we know if there are encoding differences within the individual 13-Bit / 14-Bit / 16_ Bit instruction sets (apart from differences in the supported subset of instructions)?
In particular: Can we be reasonably sure that the 14-Bit instruction set at https://free-pdk.github.io/PADAUK_FPPA_14_bit_instruction_set.html reflects the actual encoding for the PFS154?
Philipp
0x0000 000_0000_0000_0000 nop
0x0001 000_0000_0000_0001
0x0002 000_0000_0000_001-
0x0004 000_0000_0000_01--
0x0008 000_0000_0000_1---
0x0010 000_0000_0001_----
0x0020 000_0000_001-_----
0x0040 000_0000_010-_----
0x0050 000_0000_0101_----
0x0060 000_0000_0110_0000 addc a
0x0061 000_0000_0110_0001 subc a
0x0062 000_0000_0110_0010 izsn a
0x0063 000_0000_0110_0011 dzsn a
0x0064 000_0000_0110_0100
0x0065 000_0000_0110_0101
0x0066 000_0000_0110_0110
0x0067 000_0000_0110_0111 pcadd a
0x0068 000_0000_0110_1000 not a
0x0069 000_0000_0110_1001 neg a
0x006A 000_0000_0110_1010 sr a
0x006B 000_0000_0110_1011 sl a
0x006C 000_0000_0110_1100 src a
0x006D 000_0000_0110_1101 slc a
0x006E 000_0000_0110_1110 swap a
0x006F 000_0000_0110_1111
0x0070 000_0000_0111_0000 wdreset
0x0071 000_0000_0111_0001
0x0072 000_0000_0111_0010 pushaf
0x0073 000_0000_0111_0011 popaf
0x0074 000_0000_0111_0100
0x0075 000_0000_0111_0101 reset
0x0076 000_0000_0111_0110 stopsys
0x0077 000_0000_0111_0111 stopexe
0x0078 000_0000_0111_1000 engint
0x0079 000_0000_0111_1001 disgint
0x007A 000_0000_0111_1010 ret
0x007B 000_0000_0111_1011 reti
0x007C 000_0000_0111_1100 mul
0x007D 000_0000_0111_1101
0x007E 000_0000_0111_1110
0x007F 000_0000_0111_1110
0x0080 000_0000_1ppp_pppp xor a,IO
0x0100 000_0001_0ppp_pppp mov IO,a
0x0180 000_0001_1ppp_pppp mov a,IO
0x0200 000_0010_kkkk_kkkk ret I
0x0300 000_0011_----_----
0x0400 000_0100_----_----
0x0500 000_0101_wwww_www0 ldtabl word
0x0501 000_0101_wwww_www1 ldtabh word
0x0600 000_0110_wwww_www0 stt16 word
0x0601 000_0110_wwww_www1 ldt16 word
0x0700 000_0111_wwww_www0 idxm index,a
0x0701 000_0111_wwww_www1 idxm a,index
0x0800 000_10--_----_----
0x0C00 000_1100_mmmm_mmmm comp a,M
0x0D00 000_1101_mmmm_mmmm comp M,a
0x0E00 000_1110_mmmm_mmmm nadd a,M
0x0F00 000_1111_mmmm_mmmm nadd M,a
0x1000 001_0000_mmmm_mmmm add M,a
0x1100 001_0001_mmmm_mmmm sub M,a
0x1200 001_0010_mmmm_mmmm addc M,a
0x1300 001_0011_mmmm_mmmm subc M,a
0x1400 001_0100_mmmm_mmmm and M,a
0x1500 001_0101_mmmm_mmmm or M,a
0x1600 001_0110_mmmm_mmmm xor M,a
0x1700 001_0111_mmmm_mmmm mov M,a
0x1800 001_1000_mmmm_mmmm add a,M
0x1900 001_1001_mmmm_mmmm sub a,M
0x1A00 001_1010_mmmm_mmmm addc a,M
0x1B00 001_1011_mmmm_mmmm subc a,M
0x1C00 001_1100_mmmm_mmmm and a,M
0x1D00 001_1101_mmmm_mmmm or a,M
0x1E00 001_1110_mmmm_mmmm xor a,M
0x1F00 001_1111_mmmm_mmmm mov a,M
0x2000 010_0000_mmmm_mmmm addc M
0x2100 010_0001_mmmm_mmmm subc M
0x2200 010_0010_mmmm_mmmm izsn M
0x2300 010_0011_mmmm_mmmm dzsn M
0x2400 010_0100_mmmm_mmmm inc M
0x2500 010_0101_mmmm_mmmm dec M
0x2600 010_0110_mmmm_mmmm clear M
0x2700 010_0111_mmmm_mmmm xch M
0x2800 010_1000_mmmm_mmmm not M
0x2900 010_1001_mmmm_mmmm neg M
0x2A00 010_1010_mmmm_mmmm sr M
0x2B00 010_1011_mmmm_mmmm sl M
0x2C00 010_1100_mmmm_mmmm src M
0x2D00 010_1101_mmmm_mmmm slc M
0x2E00 010_1110_mmmm_mmmm ceqsn a,M
0x2F00 010_1111_mmmm_mmmm cneqsn a,M
0x3000 011_00bb_bppp_pppp t0sn IO.n
0x3400 011_01bb_bppp_pppp t1sn IO.n
0x3800 011_10bb_bppp_pppp set0 IO.n
0x3C00 011_11bb_bppp_pppp set1 IO.n
0x4000 100_00bb_bmmm_mmmm t0sn M.n
0x4400 100_01bb_bmmm_mmmm t1sn M.n
0x4800 100_10bb_bmmm_mmmm set0 M.n
0x4C00 100_11bb_bmmm_mmmm set1 M.n
0x5000 101_0000_kkkk_kkkk add a,I
0x5100 101_0001_kkkk_kkkk sub a,I
0x5200 101_0010_kkkk_kkkk ceqsn a,I
0x5300 101_0011_kkkk_kkkk cneqsn a,I
0x5400 101_0100_kkkk_kkkk and a,I
0x5500 101_0101_kkkk_kkkk or a,I
0x5600 101_0110_kkkk_kkkk xor a,I
0x5700 101_0111_kkkk_kkkk mov a,I
0x5800 101_10--_----_----
0x5C00 101_11bb_bppp_pppp swapc IO.n
0x6000 110_aaaa_aaaa_aaaa goto label
0x7000 111_aaaa_aaaa_aaaa call label
Edit: It's actually slightly different from the one posted above, but only single instructions and coherent with the encoding.
Probably the options I chose?
Just a reminder to myself:
the amount of addressable memory is (core size in bits - 3)
16 -> 13 -> 8192 words, Family 83A
15 -> 12 -> 4096 words, Family 86B
14 -> 11 -> 2048 words, Family 85A
13 -> 10 -> 1024 words, Family 84B
nop 0000_0000_0000_0000 000_0000_0000_0000 00_0000_0000_0000 0_0000_0000_0000
ldsptl 00_0000_0000_0110
ldspth 00_0000_0000_0111
addc a 0000_0000_0001_0000 000_0000_0110_0000 00_0000_0110_0000 0_0000_0001_0000
subc a 0000_0000_0001_0001 000_0000_0110_0001 00_0000_0110_0001 0_0000_0001_0001
izsn a 0000_0000_0001_0010 000_0000_0110_0010 00_0000_0110_0010 0_0000_0001_0010
dzsn a 0000_0000_0001_0011 000_0000_0110_0011 00_0000_0110_0011 0_0000_0001_0011
pcadd a 0000_0000_0001_0111 000_0000_0110_0111 00_0000_0110_0111 0_0000_0001_0111
not a 0000_0000_0001_1000 000_0000_0110_1000 00_0000_0110_1000 0_0000_0001_1000
neg a 0000_0000_0001_1001 000_0000_0110_1001 00_0000_0110_1001 0_0000_0001_1001
sr a 0000_0000_0001_1010 000_0000_0110_1010 00_0000_0110_1010 0_0000_0001_1010
sl a 0000_0000_0001_1011 000_0000_0110_1011 00_0000_0110_1011 0_0000_0001_1011
src a 0000_0000_0001_1100 000_0000_0110_1100 00_0000_0110_1100 0_0000_0001_1100
slc a 0000_0000_0001_1101 000_0000_0110_1101 00_0000_0110_1101 0_0000_0001_1101
swap a 0000_0000_0001_1110 000_0000_0110_1110 00_0000_0110_1110 0_0000_0001_1110
delay a 0000_0000_0001_1111
wdreset 0000_0000_0011_0000 000_0000_0111_0000 00_0000_0111_0000 0_0000_0011_0000
pushaf 0000_0000_0011_0010 000_0000_0111_0010 00_0000_0111_0010 0_0000_0011_0010
popaf 0000_0000_0011_0011 000_0000_0111_0011 00_0000_0111_0011 0_0000_0011_0011
reset 0000_0000_0011_0101 000_0000_0111_0101 00_0000_0111_0101 0_0000_0011_0101
stopsys 0000_0000_0011_0110 000_0000_0111_0110 00_0000_0111_0110 0_0000_0011_0110
stopexe 0000_0000_0011_0111 000_0000_0111_0111 00_0000_0111_0111 0_0000_0011_0111
engint 0000_0000_0011_1000 000_0000_0111_1000 00_0000_0111_1000 0_0000_0011_1000
disgint 0000_0000_0011_1001 000_0000_0111_1001 00_0000_0111_1001 0_0000_0011_1001
ret 0000_0000_0011_1010 000_0000_0111_1010 00_0000_0111_1010 0_0000_0011_1010
reti 0000_0000_0011_1011 000_0000_0111_1011 00_0000_0111_1011 0_0000_0011_1011
mul 0000_0000_0011_1100 000_0000_0111_1100 00_0000_0111_1100
pmode n 0000_0000_010k_kkkk
popw pcN 0000_0000_0110_tttt
pushw pcN 0000_0000_0111_tttt
mov IO,a 0000_0000_10pp_pppp 000_0001_0ppp_pppp 00_0001_10pp_pppp 0_0000_100p_pppp
mov a,IO 0000_0000_11pp_pppp 000_0001_1ppp_pppp 00_0001_11pp_pppp 0_0000_101p_pppp
cneqsn a,I 0000_0001_kkkk_kkkk 101_0011_kkkk_kkkk 10_1011_kkkk_kkkk 1_0011_kkkk_kkkk
stt16 word 0000_001w_wwww_www0 000_0110_wwww_www0 00_0011_0www_www0 0_0000_110w_www0
ldt16 word 0000_001w_wwww_www1 000_0110_wwww_www1 00_0011_0www_www1 0_0000_110w_www1
popw word 0000_010w_wwww_www0
pushw word 0000_010w_wwww_www1
igoto word 0000_011w_wwww_www0
icall word 0000_011w_wwww_www1
idxm index,a 0000_100w_wwww_www0 000_0111_wwww_www0 00_0011_1www_www0 0_0000_111w_www0
idxm a,index 0000_100w_wwww_www1 000_0111_wwww_www1 00_0011_1www_www1 0_0000_111w_www1
ldtabl word 0000_101w_wwww_www0 000_0101_wwww_www0
ldtabh word 0000_101w_wwww_www1 000_0101_wwww_www1
delay I 0000_1110_kkkk_kkkk
ret I 0000_1111_kkkk_kkkk 000_0010_kkkk_kkkk 00_0010_kkkk_kkkk 0_0001_kkkk_kkkk
xor IO,a 0001_0000_00pp_pppp 000_0000_1ppp_pppp 00_0000_11pp_pppp 0_0000_011p_pppp
xor a,IO 0001_0000_01pp_pppp
cneqsn M,a 0001_010m_mmmm_mmmm
cneqsn a,M 0001_011m_mmmm_mmmm 010_1111_mmmm_mmmm 01_0111_1mmm_mmmm 0_1011_11mm_mmmm
add a,I 0001_1000_kkkk_kkkk 101_0000_kkkk_kkkk 10_1000_kkkk_kkkk 1_0000_kkkk_kkkk
sub a,I 0001_1001_kkkk_kkkk 101_0001_kkkk_kkkk 10_1001_kkkk_kkkk 1_0001_kkkk_kkkk
ceqsn a,I 0001_1010_kkkk_kkkk 101_0010_kkkk_kkkk 10_1010_kkkk_kkkk 1_0010_kkkk_kkkk
comp a,I 0001_1011_kkkk_kkkk
and a,I 0001_1100_kkkk_kkkk 101_0100_kkkk_kkkk 10_1100_kkkk_kkkk 1_0100_kkkk_kkkk
or a,I 0001_1101_kkkk_kkkk 101_0101_kkkk_kkkk 10_1101_kkkk_kkkk 1_0101_kkkk_kkkk
xor a,I 0001_1110_kkkk_kkkk 101_0110_kkkk_kkkk 10_1110_kkkk_kkkk 1_0110_kkkk_kkkk
mov a,I 0001_1111_kkkk_kkkk 101_0111_kkkk_kkkk 10_1111_kkkk_kkkk 1_0111_kkkk_kkkk
t0sn IO.n 0010_000b_bbpp_pppp 011_00bb_bppp_pppp 01_100b_bbpp_pppp 0_1100_bbbp_pppp
t1sn IO.n 0010_001b_bbpp_pppp 011_01bb_bppp_pppp 01_101b_bbpp_pppp 0_1101_bbbp_pppp
set0 IO.n 0010_010b_bbpp_pppp 011_10bb_bppp_pppp 01_110b_bbpp_pppp 0_1110_bbbp_pppp
set1 IO.n 0010_011b_bbpp_pppp 011_11bb_bppp_pppp 01_111b_bbpp_pppp 0_1111_bbbp_pppp
tog IO.n 0010_100b_bbpp_pppp
wait0 IO.n 0010_101b_bbpp_pppp
wait1 IO.n 0010_110b_bbpp_pppp
swapc IO.n 0010_111b_bbpp_pppp 101_11bb_bppp_pppp 00_010b_bbpp_pppp
nmov M,a 0011_000m_mmmm_mmmm
nmov a,M 0011_001m_mmmm_mmmm
nadd M,a 0011_010m_mmmm_mmmm 000_1111_mmmm_mmmm 00_0111_1mmm_mmmm
nadd a,M 0011_011m_mmmm_mmmm 000_1110_mmmm_mmmm 00_0111_0mmm_mmmm
ceqsn M,a 0011_100m_mmmm_mmmm
ceqsn a,M 0011_101m_mmmm_mmmm 010_1110_mmmm_mmmm 01_0111_0mmm_mmmm 0_1011_10mm_mmmm
comp M,a 0011_110m_mmmm_mmmm 000_1101_mmmm_mmmm 00_0110_1mmm_mmmm
comp a,M 0011_111m_mmmm_mmmm 000_1100_mmmm_mmmm 00_0110_0mmm_mmmm
add M,a 0100_000m_mmmm_mmmm 001_0000_mmmm_mmmm 00_1000_0mmm_mmmm 0_0100_00mm_mmmm
add a,M 0100_001m_mmmm_mmmm 001_1000_mmmm_mmmm 00_1100_0mmm_mmmm 0_0110_00mm_mmmm
sub M,a 0100_010m_mmmm_mmmm 001_0001_mmmm_mmmm 00_1000_1mmm_mmmm 0_0100_01mm_mmmm
sub a,M 0100_011m_mmmm_mmmm 001_1001_mmmm_mmmm 00_1100_1mmm_mmmm 0_0110_01mm_mmmm
addc M,a 0100_100m_mmmm_mmmm 001_0010_mmmm_mmmm 00_1001_0mmm_mmmm 0_0100_10mm_mmmm
addc a,M 0100_101m_mmmm_mmmm 001_1010_mmmm_mmmm 00_1101_0mmm_mmmm 0_0110_10mm_mmmm
subc M,a 0100_110m_mmmm_mmmm 001_0011_mmmm_mmmm 00_1001_1mmm_mmmm 0_0100_11mm_mmmm
subc a,M 0100_111m_mmmm_mmmm 001_1011_mmmm_mmmm 00_1101_1mmm_mmmm 0_0110_11mm_mmmm
and M,a 0101_000m_mmmm_mmmm 001_0100_mmmm_mmmm 00_1010_0mmm_mmmm 0_0101_00mm_mmmm
and a,M 0101_001m_mmmm_mmmm 001_1100_mmmm_mmmm 00_1110_0mmm_mmmm 0_0111_00mm_mmmm
or M,a 0101_010m_mmmm_mmmm 001_0101_mmmm_mmmm 00_1010_1mmm_mmmm 0_0101_01mm_mmmm
or a,M 0101_011m_mmmm_mmmm 001_1101_mmmm_mmmm 00_1110_1mmm_mmmm 0_0111_01mm_mmmm
xor M,a 0101_100m_mmmm_mmmm 001_0110_mmmm_mmmm 00_1011_0mmm_mmmm 0_0101_10mm_mmmm
xor a,M 0101_101m_mmmm_mmmm 001_1110_mmmm_mmmm 00_1111_0mmm_mmmm 0_0111_10mm_mmmm
mov M,a 0101_110m_mmmm_mmmm 001_0111_mmmm_mmmm 00_1011_1mmm_mmmm 0_0101_11mm_mmmm
mov a,M 0101_111m_mmmm_mmmm 001_1111_mmmm_mmmm 00_1111_1mmm_mmmm 0_0111_11mm_mmmm
addc M 0110_000m_mmmm_mmmm 010_0000_mmmm_mmmm 01_0000_0mmm_mmmm 0_1000_00mm_mmmm
subc M 0110_001m_mmmm_mmmm 010_0001_mmmm_mmmm 01_0000_1mmm_mmmm 0_1000_01mm_mmmm
izsn M 0110_010m_mmmm_mmmm 010_0010_mmmm_mmmm 01_0001_0mmm_mmmm 0_1000_10mm_mmmm
dzsn M 0110_011m_mmmm_mmmm 010_0011_mmmm_mmmm 01_0001_1mmm_mmmm 0_1000_11mm_mmmm
inc M 0110_100m_mmmm_mmmm 010_0100_mmmm_mmmm 01_0010_0mmm_mmmm 0_1001_00mm_mmmm
dec M 0110_101m_mmmm_mmmm 010_0101_mmmm_mmmm 01_0010_1mmm_mmmm 0_1001_01mm_mmmm
clear M 0110_110m_mmmm_mmmm 010_0110_mmmm_mmmm 01_0011_0mmm_mmmm 0_1001_10mm_mmmm
xch M 0110_111m_mmmm_mmmm 010_0111_mmmm_mmmm 01_0011_1mmm_mmmm 0_1001_11mm_mmmm
not M 0111_000m_mmmm_mmmm 010_1000_mmmm_mmmm 01_0100_0mmm_mmmm 0_1010_00mm_mmmm
neg M 0111_001m_mmmm_mmmm 010_1001_mmmm_mmmm 01_0100_1mmm_mmmm 0_1010_01mm_mmmm
sr M 0111_010m_mmmm_mmmm 010_1010_mmmm_mmmm 01_0101_0mmm_mmmm 0_1010_10mm_mmmm
sl M 0111_011m_mmmm_mmmm 010_1011_mmmm_mmmm 01_0101_1mmm_mmmm 0_1010_11mm_mmmm
src M 0111_100m_mmmm_mmmm 010_1100_mmmm_mmmm 01_0110_0mmm_mmmm 0_1011_00mm_mmmm
slc M 0111_101m_mmmm_mmmm 010_1101_mmmm_mmmm 01_0110_1mmm_mmmm 0_1011_01mm_mmmm
swap M 0111_110m_mmmm_mmmm
delay M 0111_111m_mmmm_mmmm
t0sn M.n 1000_bbbm_mmmm_mmmm 100_00bb_bmmm_mmmm 10_000b_bbmm_mmmm 0_0010_bbb0_mmmm
t1sn M.n 1001_bbbm_mmmm_mmmm 100_01bb_bmmm_mmmm 10_001b_bbmm_mmmm 0_0010_bbb1_mmmm
set0 M.n 1010_bbbm_mmmm_mmmm 100_10bb_bmmm_mmmm 10_010b_bbmm_mmmm 0_0011_bbb0_mmmm
set1 M.n 1011_bbbm_mmmm_mmmm 100_11bb_bmmm_mmmm 10_011b_bbmm_mmmm 0_0011_bbb1_mmmm
goto label 110a_aaaa_aaaa_aaaa 110_aaaa_aaaa_aaaa 11_0aaa_aaaa_aaaa 1_10aa_aaaa_aaaa
call label 111a_aaaa_aaaa_aaaa 111_aaaa_aaaa_aaaa 11_1aaa_aaaa_aaaa 1_11aa_aaaa_aaaa
add a,I 0001_1000_kkkk_kkkk 101_0000_kkkk_kkkk 10_1000_kkkk_kkkk 1_0000_kkkk_kkkk
add a,M 0100_001m_mmmm_mmmm 001_1000_mmmm_mmmm 00_1100_0mmm_mmmm 0_0110_00mm_mmmm
add M,a 0100_000m_mmmm_mmmm 001_0000_mmmm_mmmm 00_1000_0mmm_mmmm 0_0100_00mm_mmmm
addc a 0000_0000_0001_0000 000_0000_0110_0000 00_0000_0110_0000 0_0000_0001_0000
addc a,M 0100_101m_mmmm_mmmm 001_1010_mmmm_mmmm 00_1101_0mmm_mmmm 0_0110_10mm_mmmm
addc M 0110_000m_mmmm_mmmm 010_0000_mmmm_mmmm 01_0000_0mmm_mmmm 0_1000_00mm_mmmm
addc M,a 0100_100m_mmmm_mmmm 001_0010_mmmm_mmmm 00_1001_0mmm_mmmm 0_0100_10mm_mmmm
and a,I 0001_1100_kkkk_kkkk 101_0100_kkkk_kkkk 10_1100_kkkk_kkkk 1_0100_kkkk_kkkk
and a,M 0101_001m_mmmm_mmmm 001_1100_mmmm_mmmm 00_1110_0mmm_mmmm 0_0111_00mm_mmmm
and M,a 0101_000m_mmmm_mmmm 001_0100_mmmm_mmmm 00_1010_0mmm_mmmm 0_0101_00mm_mmmm
call label 111a_aaaa_aaaa_aaaa 111_aaaa_aaaa_aaaa 11_1aaa_aaaa_aaaa 1_11aa_aaaa_aaaa
ceqsn a,I 0001_1010_kkkk_kkkk 101_0010_kkkk_kkkk 10_1010_kkkk_kkkk 1_0010_kkkk_kkkk
ceqsn a,M 0011_101m_mmmm_mmmm 010_1110_mmmm_mmmm 01_0111_0mmm_mmmm 0_1011_10mm_mmmm
ceqsn M,a 0011_100m_mmmm_mmmm
clear M 0110_110m_mmmm_mmmm 010_0110_mmmm_mmmm 01_0011_0mmm_mmmm 0_1001_10mm_mmmm
cneqsn a,I 0000_0001_kkkk_kkkk 101_0011_kkkk_kkkk 10_1011_kkkk_kkkk 1_0011_kkkk_kkkk
cneqsn a,M 0001_011m_mmmm_mmmm 010_1111_mmmm_mmmm 01_0111_1mmm_mmmm 0_1011_11mm_mmmm
cneqsn M,a 0001_010m_mmmm_mmmm
comp a,I 0001_1011_kkkk_kkkk
comp a,M 0011_111m_mmmm_mmmm 000_1100_mmmm_mmmm 00_0110_0mmm_mmmm
comp M,a 0011_110m_mmmm_mmmm 000_1101_mmmm_mmmm 00_0110_1mmm_mmmm
dec M 0110_101m_mmmm_mmmm 010_0101_mmmm_mmmm 01_0010_1mmm_mmmm 0_1001_01mm_mmmm
delay a 0000_0000_0001_1111
delay I 0000_1110_kkkk_kkkk
delay M 0111_111m_mmmm_mmmm
disgint 0000_0000_0011_1001 000_0000_0111_1001 00_0000_0111_1001 0_0000_0011_1001
dzsn a 0000_0000_0001_0011 000_0000_0110_0011 00_0000_0110_0011 0_0000_0001_0011
dzsn M 0110_011m_mmmm_mmmm 010_0011_mmmm_mmmm 01_0001_1mmm_mmmm 0_1000_11mm_mmmm
engint 0000_0000_0011_1000 000_0000_0111_1000 00_0000_0111_1000 0_0000_0011_1000
goto label 110a_aaaa_aaaa_aaaa 110_aaaa_aaaa_aaaa 11_0aaa_aaaa_aaaa 1_10aa_aaaa_aaaa
icall word 0000_011w_wwww_www1
idxm a,index 0000_100w_wwww_www1 000_0111_wwww_www1 00_0011_1www_www1 0_0000_111w_www1
idxm index,a 0000_100w_wwww_www0 000_0111_wwww_www0 00_0011_1www_www0 0_0000_111w_www0
igoto word 0000_011w_wwww_www0
inc M 0110_100m_mmmm_mmmm 010_0100_mmmm_mmmm 01_0010_0mmm_mmmm 0_1001_00mm_mmmm
izsn a 0000_0000_0001_0010 000_0000_0110_0010 00_0000_0110_0010 0_0000_0001_0010
izsn M 0110_010m_mmmm_mmmm 010_0010_mmmm_mmmm 01_0001_0mmm_mmmm 0_1000_10mm_mmmm
ldspth 00_0000_0000_0111
ldsptl 00_0000_0000_0110
ldt16 word 0000_001w_wwww_www1 000_0110_wwww_www1 00_0011_0www_www1 0_0000_110w_www1
ldtabh word 0000_101w_wwww_www1 000_0101_wwww_www1
ldtabl word 0000_101w_wwww_www0 000_0101_wwww_www0
mov a,I 0001_1111_kkkk_kkkk 101_0111_kkkk_kkkk 10_1111_kkkk_kkkk 1_0111_kkkk_kkkk
mov a,IO 0000_0000_11pp_pppp 000_0001_1ppp_pppp 00_0001_11pp_pppp 0_0000_101p_pppp
mov a,M 0101_111m_mmmm_mmmm 001_1111_mmmm_mmmm 00_1111_1mmm_mmmm 0_0111_11mm_mmmm
mov IO,a 0000_0000_10pp_pppp 000_0001_0ppp_pppp 00_0001_10pp_pppp 0_0000_100p_pppp
mov M,a 0101_110m_mmmm_mmmm 001_0111_mmmm_mmmm 00_1011_1mmm_mmmm 0_0101_11mm_mmmm
mul 0000_0000_0011_1100 000_0000_0111_1100 00_0000_0111_1100
nadd a,M 0011_011m_mmmm_mmmm 000_1110_mmmm_mmmm 00_0111_0mmm_mmmm
nadd M,a 0011_010m_mmmm_mmmm 000_1111_mmmm_mmmm 00_0111_1mmm_mmmm
neg a 0000_0000_0001_1001 000_0000_0110_1001 00_0000_0110_1001 0_0000_0001_1001
neg M 0111_001m_mmmm_mmmm 010_1001_mmmm_mmmm 01_0100_1mmm_mmmm 0_1010_01mm_mmmm
nmov a,M 0011_001m_mmmm_mmmm
nmov M,a 0011_000m_mmmm_mmmm
nop 0000_0000_0000_0000 000_0000_0000_0000 00_0000_0000_0000 0_0000_0000_0000
not a 0000_0000_0001_1000 000_0000_0110_1000 00_0000_0110_1000 0_0000_0001_1000
not M 0111_000m_mmmm_mmmm 010_1000_mmmm_mmmm 01_0100_0mmm_mmmm 0_1010_00mm_mmmm
or a,I 0001_1101_kkkk_kkkk 101_0101_kkkk_kkkk 10_1101_kkkk_kkkk 1_0101_kkkk_kkkk
or a,M 0101_011m_mmmm_mmmm 001_1101_mmmm_mmmm 00_1110_1mmm_mmmm 0_0111_01mm_mmmm
or M,a 0101_010m_mmmm_mmmm 001_0101_mmmm_mmmm 00_1010_1mmm_mmmm 0_0101_01mm_mmmm
pcadd a 0000_0000_0001_0111 000_0000_0110_0111 00_0000_0110_0111 0_0000_0001_0111
pmode n 0000_0000_010k_kkkk
popaf 0000_0000_0011_0011 000_0000_0111_0011 00_0000_0111_0011 0_0000_0011_0011
popw pcN 0000_0000_0110_tttt
popw word 0000_010w_wwww_www0
pushaf 0000_0000_0011_0010 000_0000_0111_0010 00_0000_0111_0010 0_0000_0011_0010
pushw pcN 0000_0000_0111_tttt
pushw word 0000_010w_wwww_www1
reset 0000_0000_0011_0101 000_0000_0111_0101 00_0000_0111_0101 0_0000_0011_0101
ret 0000_0000_0011_1010 000_0000_0111_1010 00_0000_0111_1010 0_0000_0011_1010
ret I 0000_1111_kkkk_kkkk 000_0010_kkkk_kkkk 00_0010_kkkk_kkkk 0_0001_kkkk_kkkk
reti 0000_0000_0011_1011 000_0000_0111_1011 00_0000_0111_1011 0_0000_0011_1011
set0 IO.n 0010_010b_bbpp_pppp 011_10bb_bppp_pppp 01_110b_bbpp_pppp 0_1110_bbbp_pppp
set0 M.n 1010_bbbm_mmmm_mmmm 100_10bb_bmmm_mmmm 10_010b_bbmm_mmmm 0_0011_bbb0_mmmm
set1 IO.n 0010_011b_bbpp_pppp 011_11bb_bppp_pppp 01_111b_bbpp_pppp 0_1111_bbbp_pppp
set1 M.n 1011_bbbm_mmmm_mmmm 100_11bb_bmmm_mmmm 10_011b_bbmm_mmmm 0_0011_bbb1_mmmm
sl a 0000_0000_0001_1011 000_0000_0110_1011 00_0000_0110_1011 0_0000_0001_1011
sl M 0111_011m_mmmm_mmmm 010_1011_mmmm_mmmm 01_0101_1mmm_mmmm 0_1010_11mm_mmmm
slc a 0000_0000_0001_1101 000_0000_0110_1101 00_0000_0110_1101 0_0000_0001_1101
slc M 0111_101m_mmmm_mmmm 010_1101_mmmm_mmmm 01_0110_1mmm_mmmm 0_1011_01mm_mmmm
sr a 0000_0000_0001_1010 000_0000_0110_1010 00_0000_0110_1010 0_0000_0001_1010
sr M 0111_010m_mmmm_mmmm 010_1010_mmmm_mmmm 01_0101_0mmm_mmmm 0_1010_10mm_mmmm
src a 0000_0000_0001_1100 000_0000_0110_1100 00_0000_0110_1100 0_0000_0001_1100
src M 0111_100m_mmmm_mmmm 010_1100_mmmm_mmmm 01_0110_0mmm_mmmm 0_1011_00mm_mmmm
stopexe 0000_0000_0011_0111 000_0000_0111_0111 00_0000_0111_0111 0_0000_0011_0111
stopsys 0000_0000_0011_0110 000_0000_0111_0110 00_0000_0111_0110 0_0000_0011_0110
stt16 word 0000_001w_wwww_www0 000_0110_wwww_www0 00_0011_0www_www0 0_0000_110w_www0
sub a,I 0001_1001_kkkk_kkkk 101_0001_kkkk_kkkk 10_1001_kkkk_kkkk 1_0001_kkkk_kkkk
sub a,M 0100_011m_mmmm_mmmm 001_1001_mmmm_mmmm 00_1100_1mmm_mmmm 0_0110_01mm_mmmm
sub M,a 0100_010m_mmmm_mmmm 001_0001_mmmm_mmmm 00_1000_1mmm_mmmm 0_0100_01mm_mmmm
subc a 0000_0000_0001_0001 000_0000_0110_0001 00_0000_0110_0001 0_0000_0001_0001
subc a,M 0100_111m_mmmm_mmmm 001_1011_mmmm_mmmm 00_1101_1mmm_mmmm 0_0110_11mm_mmmm
subc M 0110_001m_mmmm_mmmm 010_0001_mmmm_mmmm 01_0000_1mmm_mmmm 0_1000_01mm_mmmm
subc M,a 0100_110m_mmmm_mmmm 001_0011_mmmm_mmmm 00_1001_1mmm_mmmm 0_0100_11mm_mmmm
swap a 0000_0000_0001_1110 000_0000_0110_1110 00_0000_0110_1110 0_0000_0001_1110
swap M 0111_110m_mmmm_mmmm
swapc IO.n 0010_111b_bbpp_pppp 101_11bb_bppp_pppp 00_010b_bbpp_pppp
t0sn IO.n 0010_000b_bbpp_pppp 011_00bb_bppp_pppp 01_100b_bbpp_pppp 0_1100_bbbp_pppp
t0sn M.n 1000_bbbm_mmmm_mmmm 100_00bb_bmmm_mmmm 10_000b_bbmm_mmmm 0_0010_bbb0_mmmm
t1sn IO.n 0010_001b_bbpp_pppp 011_01bb_bppp_pppp 01_101b_bbpp_pppp 0_1101_bbbp_pppp
t1sn M.n 1001_bbbm_mmmm_mmmm 100_01bb_bmmm_mmmm 10_001b_bbmm_mmmm 0_0010_bbb1_mmmm
tog IO.n 0010_100b_bbpp_pppp
wait0 IO.n 0010_101b_bbpp_pppp
wait1 IO.n 0010_110b_bbpp_pppp
wdreset 0000_0000_0011_0000 000_0000_0111_0000 00_0000_0111_0000 0_0000_0011_0000
xch M 0110_111m_mmmm_mmmm 010_0111_mmmm_mmmm 01_0011_1mmm_mmmm 0_1001_11mm_mmmm
xor a,I 0001_1110_kkkk_kkkk 101_0110_kkkk_kkkk 10_1110_kkkk_kkkk 1_0110_kkkk_kkkk
xor a,IO 0001_0000_01pp_pppp
xor a,M 0101_101m_mmmm_mmmm 001_1110_mmmm_mmmm 00_1111_0mmm_mmmm 0_0111_10mm_mmmm
xor IO,a 0001_0000_00pp_pppp 000_0000_1ppp_pppp 00_0000_11pp_pppp 0_0000_011p_pppp
xor M,a 0101_100m_mmmm_mmmm 001_0110_mmmm_mmmm 00_1011_0mmm_mmmm 0_0101_10mm_mmmm
On the second day, wrt. completeness of implementation of the C standard, this has now far surpassed Mini-C.
unsigned int a = 15;
unsigned int b = 23;
unsigned int c;
void
main( void ) {
while (c < a * b) {
c += a;
}
}
...
_main:
; test.c: 7: while (c < a * b) {
00101$:
mov a, _a+0
mov __mulint_PARM_1+0, a
mov a, _a+1
mov __mulint_PARM_1+1, a
mov a, _b+0
mov __mulint_PARM_2+0, a
mov a, _b+1
mov __mulint_PARM_2+1, a
call __mulint
mov _main_sloc0_1_0+0, a
mov a, p
mov _main_sloc0_1_0+1, a
mov a, _c+0
sub a, _main_sloc0_1_0+0
mov a, _c+1
subc a, _main_sloc0_1_0+1
mov a, #0x00
slc a
mov _main_sloc1_1_0+0, a
mov a, _main_sloc1_1_0+0
cneqsn a, #0x00
goto 00104$
; test.c: 8: c += a;
mov a, _c+0
add a, _a+0
mov _c+0, a
mov a, _c+1
addc a, _a+1
mov _c+1, a
goto 00101$
00104$:
; test.c: 10: }
ret
...
__xinit__a:
.dw #0x000f
__xinit__b:
.dw #0x0017
test.asm:60: Error: <a> machine specific addressing or addressing mode error
test.asm:61: Error: <a> machine specific addressing or addressing mode error
test.asm:62: Error: <a> machine specific addressing or addressing mode error
test.asm:63: Error: <a> machine specific addressing or addressing mode error
test.asm:64: Error: <a> machine specific addressing or addressing mode error
test.asm:65: Error: <a> machine specific addressing or addressing mode error
test.asm:66: Error: <a> machine specific addressing or addressing mode error
test.asm:67: Error: <a> machine specific addressing or addressing mode error
test.asm:69: Error: <a> machine specific addressing or addressing mode error
test.asm:70: Error: <a> machine specific addressing or addressing mode error
test.asm:71: Error: <a> machine specific addressing or addressing mode error
test.asm:72: Error: <a> machine specific addressing or addressing mode error
test.asm:74: Error: <a> machine specific addressing or addressing mode error
test.asm:75: Error: <o> .org in REL area or directive / mnemonic error
test.asm:76: Error: <a> machine specific addressing or addressing mode error
test.asm:77: Error: <o> .org in REL area or directive / mnemonic error
test.asm:78: Error: <a> machine specific addressing or addressing mode error
test.asm:79: Error: <a> machine specific addressing or addressing mode error
test.asm:80: Error: <o> .org in REL area or directive / mnemonic error
test.asm:81: Error: <q> missing or improper operators, terminators, or delimiters
test.asm:83: Error: <a> machine specific addressing or addressing mode error
test.asm:85: Error: <a> machine specific addressing or addressing mode error
test.asm:86: Error: <a> machine specific addressing or addressing mode error
test.asm:87: Error: <o> .org in REL area or directive / mnemonic error
test.asm:88: Error: <a> machine specific addressing or addressing mode error
test.asm:89: Error: <q> missing or improper operators, terminators, or delimiters
removing test.rel
PDK version: 20
PDK data size: 3072 words
Free data size: 3040 words
MCU: PFS173 [ID: 0x2AA2]
Compiler version: 0.84
15 bit core
0000 5700 mov a, 0x00
0001 0102 mov SP, a
0002 7BED call 0x0BED
0003 010B mov IHRCR, a
0004 7BEE call 0x0BEE
0005 0163 mov BGTR, a
0006 5770 mov a, 0x70
0007 0128 mov MISC_LVR, a
0008 573C mov a, 0x3C
0009 0103 mov CLKCMD, a
000A 57F9 mov a, 0xF9
000B 010D mov PADIER, a
000C 57FF mov a, 0xFF
000D 010E mov PBDIER, a
000E 570F mov a, 0x0F
000F 010F mov PCDIER, a
0010 5700 mov a, 0x00
0011 0167 mov ROP, a
0012 7BFE call 0x0BFE
0013 52FF ceqsn a, 0xFF
0014 6059 goto 0x0059
0015 7BED call 0x0BED
0016 1701 mov M1, a
0017 3F11 set1 PAC.6
0018 5709 mov a, 0x09
0019 1700 mov M0, a
001A 3590 t1sn PA.3
001B 601A goto 0x001A
001C 3F10 set1 PA.6
001D 0063 dzsn a
001E 601D goto 0x001D
001F 2300 dzsn M0
0020 601D goto 0x001D
0021 3B10 set0 PA.6
0022 3190 t0sn PA.3
0023 6022 goto 0x0022
0024 5701 mov a, 0x01
0025 3290 t0sn PA.5
0026 57FF mov a, 0xFF
0027 1801 add a, M1
0028 010B mov IHRCR, a
0029 1701 mov M1, a
002A 3590 t1sn PA.3
002B 602A goto 0x002A
002C 3690 t1sn PA.5
002D 6054 goto 0x0054
002E 5704 mov a, 0x04
002F 0126 mov MISC, a
0030 3190 t0sn PA.3
0031 6030 goto 0x0030
0032 2604 clear M4
0033 2605 clear M5
0034 575A mov a, 0x5A
0035 1702 mov M2, a
0036 5700 mov a, 0x00
0037 1703 mov M3, a
0038 0502 ldtabl M2
0039 1604 xor M4, a
003A 0503 ldtabh M2
003B 1005 add M5, a
003C 2B04 sl M4
003D 2D05 slc M5
003E 2004 addc M4
003F 2502 dec M2
0040 2103 subc M3
0041 3480 t1sn FLAG.C
0042 6038 goto 0x0038
0043 3F10 set1 PA.6
0044 3590 t1sn PA.3
0045 6044 goto 0x0044
0046 2B04 sl M4
0047 2D05 slc M5
0048 5F10 swapc PA.6
0049 3190 t0sn PA.3
004A 6049 goto 0x0049
004B 3290 t0sn PA.5
004C 6044 goto 0x0044
004D 3B10 set0 PA.6
004E 3590 t1sn PA.3
004F 604E goto 0x004E
0050 3190 t0sn PA.3
0051 6050 goto 0x0050
0052 3690 t1sn PA.5
0053 6032 goto 0x0032
0054 3190 t0sn PA.3
0055 6054 goto 0x0054
0056 3690 t1sn PA.5
0057 6018 goto 0x0018
0058 6058 goto 0x0058
0059 010B mov IHRCR, a
005A 605A goto 0x005A
005B 7FFF call 0x0FFF
005C 7FFF call 0x0FFF
005D 7FFF call 0x0FFF
005E 7FFF call 0x0FFF
005F 7FFF call 0x0FFF
0060 7FFF call 0x0FFF
...
0BE0 7FFF call 0x0FFF
0BE1 7FFF call 0x0FFF
0BE2 7FFF call 0x0FFF
0BE3 7FFF call 0x0FFF
0BE4 7FFF call 0x0FFF
0BE5 7FFF call 0x0FFF
0BE6 7FFF call 0x0FFF
0BE7 7FFF call 0x0FFF
0BE8 7FFF call 0x0FFF
0BE9 7FFF call 0x0FFF
0BEA 7FFF call 0x0FFF
0BEB 7FFF call 0x0FFF
0BEC 7FFF call 0x0FFF
0BED 7FFF call 0x0FFF
0BEE 7FFF call 0x0FFF
0BEF 3FFE set1 io.126.7
0BF0 7FFF call 0x0FFF
0BF1 7FFF call 0x0FFF
0BF2 7FFF call 0x0FFF
0BF3 7FFF call 0x0FFF
0BF4 7FFF call 0x0FFF
0BF5 7FFF call 0x0FFF
0BF6 7FFF call 0x0FFF
0BF7 7FFF call 0x0FFF
0BF8 0000 nop
0BF9 0000 nop
0BFA 7FFF call 0x0FFF
0BFB 7FFF call 0x0FFF
0BFC 7FFF call 0x0FFF
0BFD 7FFF call 0x0FFF
0BFE 7FFF call 0x0FFF
0BFF 7AFC call 0x0AFC
Although init code seems to be missing and I get lot of this:Code: [Select]test.asm:60: Error: <a> machine specific addressing or addressing mode error
[…]
Now that the software side seems on track, how about some hardware engineering?
It should be possible to program the chips with xFFF so they stay fresh and useable.
Just for a quick peek at what the programmer does.
We should now be able to distinguish between the programming phase and the bit-banged calibration.
./switch1.c
./rotate6.c
./rotate6.c:86: warning 94: comparison is always true due to limited range of data type
./rotate6.c:84: warning 158: overflow in implicit constant conversion
./rotate6.c:121: warning 158: overflow in implicit constant conversion
./compare3.c
./compare3.c:151: warning 94: comparison is always false due to limited range of data type
./compare3.c:152: warning 126: unreachable code
./compare3.c:152: warning 126: unreachable code
./compare3.c:152: warning 126: unreachable code
./compare3.c:152: warning 126: unreachable code
./compare3.c:173: warning 94: comparison is always false due to limited range of data type
./compare3.c:174: warning 126: unreachable code
./compare3.c:174: warning 126: unreachable code
./compare3.c:174: warning 126: unreachable code
./compare3.c:174: warning 126: unreachable code
./rotate1.c
./compare7.c
In file included from ./compare7.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./compare5.c
./compare5.c:219: warning 94: comparison is always false due to limited range of data type
./compare5.c:220: warning 126: unreachable code
./compare5.c:220: warning 126: unreachable code
./compare5.c:220: warning 126: unreachable code
./compare5.c:220: warning 126: unreachable code
./compare5.c:242: warning 94: comparison is always false due to limited range of data type
./compare5.c:271: warning 94: comparison is always false due to limited range of data type
./compare5.c:243: warning 126: unreachable code
./compare5.c:243: warning 126: unreachable code
./compare5.c:243: warning 126: unreachable code
./compare5.c:243: warning 126: unreachable code
./compare5.c:272: warning 126: unreachable code
./compare5.c:272: warning 126: unreachable code
./compare5.c:272: warning 126: unreachable code
./compare5.c:272: warning 126: unreachable code
./compare6.c
Backtrace:
sdcc(+0xa4bce)[0x55b8eaabbbce]
sdcc(+0x1d73a7)[0x55b8eabee3a7]
sdcc(+0x1d7946)[0x55b8eabee946]
sdcc(+0x1d9c1e)[0x55b8eabf0c1e]
sdcc(+0x1d671e)[0x55b8eabed71e]
sdcc(+0x3c35c)[0x55b8eaa5335c]
sdcc(+0x568b0)[0x55b8eaa6d8b0]
sdcc(+0x1fe9f)[0x55b8eaa36e9f]
sdcc(+0x1be86)[0x55b8eaa32e86]
/lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xe7)[0x7fde56ffdb97]
sdcc(+0x1d7aa)[0x55b8eaa347aa]
./compare6.c:165: error 9: FATAL Compiler Internal Error in file 'gen.c' line number '265' : code generator internal error
Contact Author with source code
Caught signal 11: SIGSEGV
./bool2.c
./nestfor.c
In file included from ./nestfor.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./pcodeopt.c
./struct1.c
./compare8.c
In file included from ./compare8.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./rotate3.c
./ptrarg.c
./add3.c
./add3.c:64: warning 94: comparison is always true due to limited range of data type
./rotate2.c
./call1.c
./bool1.c
./compare4.c
./compare4.c:63: warning 94: comparison is always false due to limited range of data type
./compare4.c:64: warning 126: unreachable code
./compare4.c:64: warning 126: unreachable code
./compare4.c:64: warning 126: unreachable code
./compare4.c:64: warning 126: unreachable code
./compare4.c:93: warning 94: comparison is always false due to limited range of data type
./compare4.c:94: warning 126: unreachable code
./compare4.c:94: warning 126: unreachable code
./compare4.c:94: warning 126: unreachable code
./compare4.c:94: warning 126: unreachable code
./compare4.c:250: warning 94: comparison is always true due to limited range of data type
./compare4.c:294: warning 158: overflow in implicit constant conversion
./compare4.c:304: warning 158: overflow in implicit constant conversion
./compare4.c:313: warning 158: overflow in implicit constant conversion
./rotate4.c
./rotate4.c:30: error 9: FATAL Compiler Internal Error in file 'gen.c' line number '1520' : Unimplemented iCode
Contact Author with source code
./add2.c
./compare10.c
In file included from ./compare10.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./inline.c
In file included from ./inline.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./rotate5.c
./rotate5.c:179: warning 158: overflow in implicit constant conversion
./rotate5.c:205: warning 158: overflow in implicit constant conversion
./rotate5.c:206: warning 158: overflow in implicit constant conversion
./rotate5.c:209: warning 158: overflow in implicit constant conversion
./rotate5.c:210: warning 158: overflow in implicit constant conversion
./rotate5.c:213: warning 158: overflow in implicit constant conversion
./rotate5.c:216: warning 158: overflow in implicit constant conversion
./rotate5.c:219: warning 158: overflow in implicit constant conversion
./rotate5.c:222: warning 158: overflow in implicit constant conversion
./rotate5.c:225: warning 158: overflow in implicit constant conversion
./rotate5.c:228: warning 158: overflow in implicit constant conversion
./rotate5.c:229: warning 158: overflow in implicit constant conversion
./bool3.c
./string1.c
In file included from ./string1.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./xor.c
./compare.c
./compare9.c
In file included from ./compare9.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./for.c
./for.c:37: error 226: no type specifier for '(cast)'
./add4.c
./add.c
./pointer1.c
./and1.c
./and2.c
./b.c
./ptrfunc.c
./ptrfunc.c:47: error 9: FATAL Compiler Internal Error in file 'gen.c' line number '516' : Unimplemented call through function pointer
Contact Author with source code
./compare2.c
./mult1.c
./sub.c
./rotate7.c
./rotate7.c:206: warning 158: overflow in implicit constant conversion
./rotate7.c:212: warning 158: overflow in implicit constant conversion
./rotate7.c:218: warning 158: overflow in implicit constant conversion
./rotate7.c:224: warning 158: overflow in implicit constant conversion
./rotate7.c:230: warning 158: overflow in implicit constant conversion
./rotate7.c:236: warning 158: overflow in implicit constant conversion
./rotate7.c:242: warning 158: overflow in implicit constant conversion
./rotate7.c:248: warning 158: overflow in implicit constant conversion
./rotate7.c:254: warning 158: overflow in implicit constant conversion
./rotate7.c:260: warning 158: overflow in implicit constant conversion
./rotate7.c:266: warning 158: overflow in implicit constant conversion
./rotate7.c:272: warning 158: overflow in implicit constant conversion
./rotate7.c:278: warning 158: overflow in implicit constant conversion
./rotate7.c:284: warning 158: overflow in implicit constant conversion
./rotate7.c:290: warning 158: overflow in implicit constant conversion
./rotate7.c:297: warning 158: overflow in implicit constant conversion
./rotate7.c:303: warning 158: overflow in implicit constant conversion
./rotate7.c:309: warning 158: overflow in implicit constant conversion
./rotate7.c:315: warning 158: overflow in implicit constant conversion
./rotate7.c:321: warning 158: overflow in implicit constant conversion
./rotate7.c:327: warning 158: overflow in implicit constant conversion
./rotate7.c:333: warning 158: overflow in implicit constant conversion
./rotate7.c:339: warning 158: overflow in implicit constant conversion
./rotate7.c:345: warning 158: overflow in implicit constant conversion
./rotate7.c:351: warning 158: overflow in implicit constant conversion
./rotate7.c:357: warning 158: overflow in implicit constant conversion
./rotate7.c:363: warning 158: overflow in implicit constant conversion
./rotate7.c:369: warning 158: overflow in implicit constant conversion
./rotate7.c:375: warning 158: overflow in implicit constant conversion
./rotate7.c:381: warning 158: overflow in implicit constant conversion
./init0.c
./init0.c:43: error 9: FATAL Compiler Internal Error in file 'gen.c' line number '516' : Unimplemented call through function pointer
Contact Author with source code
./while.c
./empty.c
./arrays.c
./or1.c
./sub2.c
./sub2.c:162: warning 158: overflow in implicit constant conversion
./configword.c
In file included from ./configword.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./bank1.c
./bank1.c:20: error 9: FATAL Compiler Internal Error in file 'SDCCmem.c' line number '385' : code generator internal error
Contact Author with source code
Caught signal 11: SIGSEGV
./switch1.c
./rotate6.c
./rotate6.c:86: warning 94: comparison is always true due to limited range of data type
./rotate6.c:84: warning 158: overflow in implicit constant conversion
./rotate6.c:121: warning 158: overflow in implicit constant conversion
./compare3.c
./compare3.c:151: warning 94: comparison is always false due to limited range of data type
./compare3.c:152: warning 126: unreachable code
./compare3.c:152: warning 126: unreachable code
./compare3.c:152: warning 126: unreachable code
./compare3.c:152: warning 126: unreachable code
./compare3.c:173: warning 94: comparison is always false due to limited range of data type
./compare3.c:174: warning 126: unreachable code
./compare3.c:174: warning 126: unreachable code
./compare3.c:174: warning 126: unreachable code
./compare3.c:174: warning 126: unreachable code
./rotate1.c
./compare7.c
In file included from ./compare7.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./compare5.c
./compare5.c:219: warning 94: comparison is always false due to limited range of data type
./compare5.c:220: warning 126: unreachable code
./compare5.c:220: warning 126: unreachable code
./compare5.c:220: warning 126: unreachable code
./compare5.c:220: warning 126: unreachable code
./compare5.c:242: warning 94: comparison is always false due to limited range of data type
./compare5.c:271: warning 94: comparison is always false due to limited range of data type
./compare5.c:243: warning 126: unreachable code
./compare5.c:243: warning 126: unreachable code
./compare5.c:243: warning 126: unreachable code
./compare5.c:243: warning 126: unreachable code
./compare5.c:272: warning 126: unreachable code
./compare5.c:272: warning 126: unreachable code
./compare5.c:272: warning 126: unreachable code
./compare5.c:272: warning 126: unreachable code
./compare6.c
./bool2.c
./nestfor.c
In file included from ./nestfor.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./pcodeopt.c
./struct1.c
./compare8.c
In file included from ./compare8.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./rotate3.c
./ptrarg.c
./add3.c
./add3.c:64: warning 94: comparison is always true due to limited range of data type
./rotate2.c
./call1.c
./bool1.c
./compare4.c
./compare4.c:63: warning 94: comparison is always false due to limited range of data type
./compare4.c:64: warning 126: unreachable code
./compare4.c:64: warning 126: unreachable code
./compare4.c:64: warning 126: unreachable code
./compare4.c:64: warning 126: unreachable code
./compare4.c:93: warning 94: comparison is always false due to limited range of data type
./compare4.c:94: warning 126: unreachable code
./compare4.c:94: warning 126: unreachable code
./compare4.c:94: warning 126: unreachable code
./compare4.c:94: warning 126: unreachable code
./compare4.c:250: warning 94: comparison is always true due to limited range of data type
./compare4.c:294: warning 158: overflow in implicit constant conversion
./compare4.c:304: warning 158: overflow in implicit constant conversion
./compare4.c:313: warning 158: overflow in implicit constant conversion
./rotate4.c
./add2.c
./compare10.c
In file included from ./compare10.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./inline.c
In file included from ./inline.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./rotate5.c
./rotate5.c:179: warning 158: overflow in implicit constant conversion
./rotate5.c:205: warning 158: overflow in implicit constant conversion
./rotate5.c:206: warning 158: overflow in implicit constant conversion
./rotate5.c:209: warning 158: overflow in implicit constant conversion
./rotate5.c:210: warning 158: overflow in implicit constant conversion
./rotate5.c:213: warning 158: overflow in implicit constant conversion
./rotate5.c:216: warning 158: overflow in implicit constant conversion
./rotate5.c:219: warning 158: overflow in implicit constant conversion
./rotate5.c:222: warning 158: overflow in implicit constant conversion
./rotate5.c:225: warning 158: overflow in implicit constant conversion
./rotate5.c:228: warning 158: overflow in implicit constant conversion
./rotate5.c:229: warning 158: overflow in implicit constant conversion
./bool3.c
./string1.c
In file included from ./string1.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./xor.c
./compare.c
./compare9.c
In file included from ./compare9.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./for.c
./for.c:37: error 226: no type specifier for '(cast)'
./add4.c
./add.c
./pointer1.c
./and1.c
./and2.c
./b.c
./ptrfunc.c
./compare2.c
./mult1.c
./sub.c
./rotate7.c
./rotate7.c:206: warning 158: overflow in implicit constant conversion
./rotate7.c:212: warning 158: overflow in implicit constant conversion
./rotate7.c:218: warning 158: overflow in implicit constant conversion
./rotate7.c:224: warning 158: overflow in implicit constant conversion
./rotate7.c:230: warning 158: overflow in implicit constant conversion
./rotate7.c:236: warning 158: overflow in implicit constant conversion
./rotate7.c:242: warning 158: overflow in implicit constant conversion
./rotate7.c:248: warning 158: overflow in implicit constant conversion
./rotate7.c:254: warning 158: overflow in implicit constant conversion
./rotate7.c:260: warning 158: overflow in implicit constant conversion
./rotate7.c:266: warning 158: overflow in implicit constant conversion
./rotate7.c:272: warning 158: overflow in implicit constant conversion
./rotate7.c:278: warning 158: overflow in implicit constant conversion
./rotate7.c:284: warning 158: overflow in implicit constant conversion
./rotate7.c:290: warning 158: overflow in implicit constant conversion
./rotate7.c:297: warning 158: overflow in implicit constant conversion
./rotate7.c:303: warning 158: overflow in implicit constant conversion
./rotate7.c:309: warning 158: overflow in implicit constant conversion
./rotate7.c:315: warning 158: overflow in implicit constant conversion
./rotate7.c:321: warning 158: overflow in implicit constant conversion
./rotate7.c:327: warning 158: overflow in implicit constant conversion
./rotate7.c:333: warning 158: overflow in implicit constant conversion
./rotate7.c:339: warning 158: overflow in implicit constant conversion
./rotate7.c:345: warning 158: overflow in implicit constant conversion
./rotate7.c:351: warning 158: overflow in implicit constant conversion
./rotate7.c:357: warning 158: overflow in implicit constant conversion
./rotate7.c:363: warning 158: overflow in implicit constant conversion
./rotate7.c:369: warning 158: overflow in implicit constant conversion
./rotate7.c:375: warning 158: overflow in implicit constant conversion
./rotate7.c:381: warning 158: overflow in implicit constant conversion
./init0.c
./while.c
./empty.c
./arrays.c
./or1.c
./sub2.c
./sub2.c:162: warning 158: overflow in implicit constant conversion
./configword.c
In file included from ./configword.c:2:
./picregs.h:6:25: fatal error: pic14regs.h: No such file or directory
compilation terminated.
./picregs.h:1: warning 190: ISO C forbids an empty source file
./bank1.c
Might need a few weeks, but then I can sample a full programming cycle with all pins in parallel.
|\
| \
| \______ _______
| | | |
| |_| | .........
|- select -||-----command / data-----
mode
The remark "Please notice that bit 0 should be kept 0 due to program counter is 16 bits" in the datasheets seems odd to me. Any idea, what this could be about? Would anything break if I place the stack at an odd address? Do push / pop / call / ret require the stack pointer to be aligned?
Philipp
I interpret this to mean that the RAM is word accessible only on word boundaries. Bit 0 of SP must be 0 to ensure word alignment. This implies that push/pop af will use a word of stack instead of a byte.
Another question on push af would be which one of a and f goes into the lower address.
Philipp
Another question on push af would be which one of a and f goes into the lower address.
Philipp
Doesnt really matter does it?
If you implement pushaf and popaf symetrically for an emulator there will be no difference.
A isn't used as return value (thats the whole point of pushing it).
Unless youre trying to expicitly modify A or the flags on the stack there is absolutely no difference. They are designed to be atomic operations.
pushw #retlabel
pushw funcptr
ret
retlabel:
ld a, sp
ld p, a
push af
ld a, op0
idxm p, a
inc p
ld a, op1
idxm p, a
That could obviously be brought down to 6 or 7 (depending on which byte a goes in on push af).
Philipp
mov a, sp; a = sp
mov p, a; p = a
push af // a is already overwritten by sp so why save it? shouldn't this be the first instruction?
mov a, op0; a = op0
idxm p, a; [p] = a
inc p; p += 1
mov a, op1; a = op1
idxm p, a; [p] = a
pushaf
mov a, sp
mov p, a
mov a, op0
idxm p, a
inc a
mov a, op1
idxm p, a
add sp, 2
pushaf
mov a, op0
idxm sp, a
inc sp
mov a, op1
idxm sp, a
inc sp
dec sp
idxm a, sp
mov op1, a
dec sp
idxm a, sp
mov op0, a
popaf
Yes, I meant mov, not ld.
The push af is curently just used to cheaply increase sp by 2. But If I knew which byte a goes into, it could be used to at the same time write one of the bytes I want on the stack.
Philipp
mov a, op0
idxm sp, a
inc sp
mov a, op1
idxm sp, a
inc sp
But then you dont need the pushaf/popaf at all and youre down to six instructions anyway ;)Code: [Select]mov a, op0
idxm sp, a
inc sp
mov a, op1
idxm sp, a
inc sp
mov a, sp
mov p, a
mov a, op0
pushaf
inc p
mov a, op1
idxm p, a
mov a, op0
pushaf
mov a, op1
pushaf
Updated disassembler with 15 bit instruction set support.
Linux and Windows binaries included.
001D 3F10 set1 .6
001E 0063 dzsn a
001F 601E goto 0x001E
0020 2300 dzsn M0
0021 601E goto 0x001E
0022 3B10 set0 .6
0023 3190 t0sn .3
0024 6023 goto 0x0023
0025 5701 mov a, 0x01
0026 3290 t0sn .5
0027 57FF mov a, 0xFF
0028 1801 add a, M1
0029 010B mov IHRCR, a
002A 1701 mov M1, a
002B 3590 t1sn .3
I looked at the PMC884 datasheet and you really cannot infer the positions on the stack.
word data0 ; // declare data0 in RAM
word data1 ; // declare data1 in RAM
...
From the startup code and the description of idxm one can infer that the Padauks are little endian, so the byte order for pusw in the 16-Bit instruction set should be the same. But push af is a different matter. Doing push af twice won't push a 16-Bit value onto the stack. It pushes two 16-bit vales, and the two a value bytes are apart, so I can't use that to push a 16-bit value.
word op;
....
mov a, ld@op //low byte of op
pushaf
mov a, hd@op //high byte of op
pushaf
...
popaf
mov hd@op, a
popaf
mov ld@op, a
There seems to be a small problem with the io.txt file for the 15-bit core: some of the ios are no longer named (PFS173 startup code). PFS154 and test pdks previously included work fine.
A good starting point to see what I mean might be this datasheet for old PIC16C7XX OTPsI think they're more complex than that --- the PIC only uses the high voltage to enter programming mode and then it's just data/clock. In the video you can see more voltage levels than that.
(although the padauks will probably behave differently I guess its reasonable to assume for now that their approach is similar)
http://ww1.microchip.com/downloads/en/DeviceDoc/30298d.pdf (http://ww1.microchip.com/downloads/en/DeviceDoc/30298d.pdf)
I think they're more complex than that --- the PIC only uses the high voltage to enter programming mode and then it's just data/clock. In the video you can see more voltage levels than that.
0x63421c 70 69 Please remove all IC, and check VDD,\nVPP(PA5), PA0 / 3 / 4 / 7 is 0 V
0x634264 30 29 Please check VPP (PA5) = 4.6V
0x634284 31 30 Please check VPP (PA5) = 11.3V
0x6342a4 24 23 Please check VDD = 5.5V
0x6342bc 24 23 Please check VDD = 7.5V
0x6342d4 24 23 Please check VDD = 3.3V
The Padauks are different, but I dont think that we need the full waveform to be captured.
Just the maybe 30 - 40 cycles after each rise of VDD. The mode select is probably a combination of analog voltage levels and commands.
Also its much easier to trigger on a rising edge so the timinig issues that David was having shouldnt be that much of a problem.
There are different voltages on more pins than just VDD.
You can see some screen shots of the capture below (focus on first data block, zoomed in, zoomed in more).
I grouped CLK and DATA into a BUS (SPI) so the software tried to decode some bits... unfortunately it seems a non standard 8 bit transmissions is used.
You can hook if a few analog comparators to diffetentiate between the required voltage levels. Something like a flash ADC structure, but with far less bits.
A single CA339 + 4 trimpots would give you five voltage levels, and take 4 bits on the logic analyzer.
Enviado de meu SM-N910C usando o Tapatalk
EDIT: Since I like the idea of using some bits of the logic analyzer to capture analog voltage so much, I will use a cheap STM32F072 board to do exactly this... 2 parallel ADC channels, output 2x8 bit, should only take an hour to implement :-)
A Padauk or Puolop would provide the ADC channels cheaper.
Philipp
...
/* USER CODE BEGIN 0 */
//double buffer(2) * 32 bit // 32 bit = (2 * 16 bit) // each adc value always takes 16 bit
static uint32_t adcDMABuffer[2];
//first part of double buffer complete
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* AdcHandle) {
//combine and output 2 adc values (8bit : 8bit) on GPIOB
GPIOB->ODR = (adcDMABuffer[0] | (adcDMABuffer[0]>>8)) & 0xFFFF;
}
//second part of double buffer complete
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* AdcHandle) {
//combine and output 2 adc values (8bit : 8bit) on GPIOB
GPIOB->ODR = (adcDMABuffer[1] | (adcDMABuffer[1]>>8)) & 0xFFFF;
}
/* USER CODE END 0 */
...
/* USER CODE BEGIN 2 */
HAL_ADCEx_Calibration_Start(&hadc);
HAL_ADC_Start_DMA(&hadc, (uint32_t*)adcDMABuffer, 2*2 );
/* USER CODE END 2 */
...
Hi,
I was trying to find out some info about the "BGTR" register which is defined in PFS154.INC and used by init code of PFS154 when I came across this:
"SONiX 8-Bit Micro-Controller"
I think I just found the initial IC designer which seem to have created the CPU core in 2004 or earlier (several years before PADAUK adapted it):
[…]
[…] I also did not see the 100% identical "Puolop" brand before 8)
Hi,
I was trying to find out some info about the "BGTR" register which is defined in PFS154.INC and used by init code of PFS154 when I came across this:
"SONiX 8-Bit Micro-Controller"
I think I just found the initial IC designer which seem to have created the CPU core in 2004 or earlier (several years before PADAUK adapted it):
[…]
That looks somewhat similar to, but still different from the Padauk devices. In particular, Padauk (and Puolop) have a stack in RAM. SONiX has a tiny fixed-size stack in separate memory (similar to low-end PIC devices). That makes Padauk / Puolop a better target for a C compiler.
Philipp
void LookUp_A(void)
{
ADD A,1
PCADD A
RET 0x0F
RET 0x1F
RET 0x7F
RET 0x00
}
...
A = i;
LookUp_A();
tm2b = A;
...
void LookUp_A(void)
{
//caller needs to make sure A is in range of 0-3
ADD A,1
PCADD A
RET 0x0F
RET 0x1F
RET 0x7F
RET 0x00
}
void FPPA0(void):stack=4
{
.ADJUST_IC SYSCLK=IHRC/32, IHRC=16MHz, VDD=3V, Bandgap=Off
$ TM2S = 8BIT, /1, /1; // 8-bit PWM, pre-scalar = 1, scalar = 1 (tm2s = 0b0_00_00000)
while (1) {
BYTE i = 0;
while (1)
{
A = i;
LookUp_A();
if( 0==A )
$ TM2C = STOP;
else
{
TM2B = A;
$ TM2C = SYSCLK, PA3, PWM; // setup timer2 as pwm out: system clock (512kHz), output=PA3, PWM mode (tm2c = 0b0001_10_1_0)
}
i++;
if (i == 4) break;
.delay 40000;
}
.delay 1000000;
}
}
void LookUp_A(void) //caller needs to make sure A is in range of 0-3
{
ADD A,1
PCADD A
RET 0x0F
RET 0x1F
RET 0x7F
RET 0x00
}
void DeepSleep_2s(void)
{
WORD sleep = 0;
STT16 sleep
INTRQ.T16 = 0;
$ T16M = ILRC, /64, BIT11; //T16 clock source = ILRC (typ. 62 kHz on PMC150), / 64 => approx 1 kHz timer, 11BIT = 2048 => approx 2 seconds
while( !INTRQ.T16 ) //STOPEXE could be interrupted by multiple sources, we wait for T16 overflow here
STOPEXE;
$ T16M = STOP;
}
void FPPA0(void) : stack=2
{
.ADJUST_IC SYSCLK=ILRC (IHRC/16), IHRC=16MHz, VDD=3V, Bandgap=Off
#if _SYS (AT_ICE)
$ CLKMD = ILRC/4, En_ILRC; // ICE does not support ILRC/16, so we use /4 instead
#else
$ CLKMD = ILRC/16, En_ILRC; // use ILRC/16 as system clock (3.875kHz), turn off IHRC to save more power
#endif
$ TM2S = 8BIT, /1, /1; // 8-bit PWM, pre-scalar = 1, scalar = 1 (tm2s = 0b0_00_00000)
while (1)
{
BYTE i = 0;
while (1)
{
A = i;
LookUp_A();
if( 0==A )
$ TM2C = STOP;
else
{
TM2B = A;
$ TM2C = ILRC, PA3, PWM; // setup timer2 as pwm out: clock ilrc (62kHz), output=PA3, PWM mode
}
i++;
if (i == 4) break;
.delay 300;
#if _SYS (AT_ICE)
.delay 900; // wait extra time since ICE clock is faster
#endif
}
DeepSleep_2s();
}
}
You really need ADD A, 1?
Not sure about padauk, but other microcontroller always have PC pointing to the next instruction, so PCADD zero behaves like NOP.
Enviado de meu SM-N910C usando o Tapatalk
signal - | SOT-23-6 pin - | DIP 14 pin |
PA4 | 1 | 9 |
GND | 2 | 11 |
PA6 | 3 | 6 |
PA5 | 4 | 7 |
VDD | 5 | 4 |
PA3 | 6 | 8 |
.writer package 14, 4, 32, 8, 9, 7, 6, 32, 11, 0x0000, 0x0000, 0
Hi,
I finally got the time to use a logic analyzer (ZeroPlus Logic Cube LAP-C322000) to capture the writing of a program on a PFS154.
...
00000000: 70 00 00 2f 82 01 ed 3f 8b 01 ee 3f 9a 01 80 2f p../...?...?.../
00000010: 9b 01 1c 2f 83 01 fe 3f ff 2a 54 30 ed 3f 81 0b .../...?.*T0.?..
00000020: 91 1f 05 2f 80 0b d0 1a 13 30 90 1f 63 00 16 30 .../.....0..c..0
00000030: 80 11 16 30 90 1d d0 18 1b 30 01 2f 50 19 ff 2f ...0.....0./P../
00000040: 01 0c 8b 01 81 0b d0 1a 23 30 50 1b 4f 30 04 2f ........#0P.O0./
00000050: 88 01 d0 18 29 30 02 2f 82 01 04 13 05 13 6e 2f ....)0./......n/
00000060: 82 0b 00 2f 83 0b 06 00 04 0b 07 00 05 08 84 15 .../............
00000070: 85 16 04 10 82 12 83 10 40 1a 33 30 90 1f d0 1a ........@.30....
00000080: 3f 30 84 15 85 16 90 05 d0 18 44 30 50 19 3f 30 ?0........D0P.?0
00000090: 90 1d d0 1a 49 30 d0 18 4b 30 50 1b 2b 30 d0 18 ....I0..K0P.+0..
000000a0: 4f 30 50 1b 11 30 53 30 8b 01 d1 1e d0 1e 03 2f O0P..0S0......./
000000b0: c1 0b 8a 2f c0 0b 56 2f 63 00 5c 30 c0 11 5c 30 .../..V/c.\0..\0
000000c0: c1 11 5c 30 d0 1c 03 2f c1 0b 8a 2f c0 0b 56 2f ..\0.../.../..V/
000000d0: 63 00 68 30 c0 11 68 30 c1 11 68 30 56 30 ff 3f c.h0..h0..h0V0.?
000000e0: ff 3f ff 3f ff 3f ff 3f ff 3f ff 3f ff 3f ff 3f .?.?.?.?.?.?.?.?
000000f0: ff 3f ff 3f ff 3f ff 3f ff 3f ff 3f ff 3f ff 3f .?.?.?.?.?.?.?.?
1009: 1010010110100101101001011010011000001010101000010
55103: 1010010110100101101001011010011000011010101000010
65685: 001111110111101111111111110000111111100000000000000001100011111110001000000000000111
92201: 1010010110100101101001011010001100011010101000010
112855: 0
122857: 00
132871: 0
158597: 1010010110100101101001011010011001111010101000010
737022: 1010010110100101101001011010011100001010101000010
757693: 000000000001001111111111111111111111111111111111111111110011111110000000000000
784240: 1010010110100101101001011010011000001010101000010
820818: 1010010110100101101001011010011100001010101000010
841488: 111111111111110000000000010011111111111111111111111111110011111110000000000000
868054: 1010010110100101101001011010011000001010101000010
904632: 1010010110100101101001011010011000001010101000010
949230: 1010010110100101101001011010011000001010101000010
969891: 00111111000001111111111111100011111100001011111111111110001111110001001111111111111100111111000110111111111111110011111100100111111111111111001111110010101111111111111100111111001100111111111111110011111100111011111111111111001111110100011111111111111100111111010010111111111111110011111101010011111111111111001111110101111111111111111100111111011001111111111111110011111101101000010100000011001111110111000001001111010100111111011110111111111111000011111110000000000000001000001111111000100000000000100100111111100101111111111111100011111110011111111111111110001111111010011111111111111100111111101011111111111111110011111110110111111111111111001111111011111111111111111100111111110000111111111111110011111111001111111111111111001111111101001111111111111100111111110111111111111111110011111111100011111111111111001111111110111111111111111100111111111100111111111111110011111111111111111111111111
1004046: 1010010110100101101001011010011000011010101000010
1589373: 1010010110100101101001011010011100011010101000010
1620117: 000000011100001011110000000000000110000010111111111011010000000000000000000000000001100010111111111110111000000110011010101111100000000000000000100000000000000001100110111011110001110000000110000011111111111111100000000001000000000000101010111111111100000101010011111111101101001011100000010000000001100000000000011111100100011011110000010100101110000000011010110100000000000010000000000000110000000100110111111001000000000001100011110000000101100000000010100000000000010001100000001100000001011001110110010000011000110100000000000011000000000000110000000110111011110000000101100101010000101111111111110000000011100000000000001100000000010000011000101100101110000001011010110100000000000100000000000000110000001000110110110101000011000001001111101111000001000000000100100000000000000001100010000110001101000011000000101001101111000000100000000101000000000000000001100000100100110000010001001100000101101111011011100000000101100000000000001011100000101011110000000000101110000011000000000001100000000110000000000000001011000001000000000000011100100000000101010101100001000000000110100000000000010110100001010100000000010001001010000010010000100000110000000111000000000000011010010000001100000011001101111110010000011010110100000000000111100000000000110000001111110101011000010001011010000101000101100100000000001000000000000000011000110100001100000100010001100101010000110000001111110000001000100000000000011101100100000110101101000011000001001001011000110100000000001001000000000000110000010010110110110101000011000000101011011000110100000000001001100000000000110000010011110110110101000011000000010001110000010100110000001010000000000000000001100010110111101101000101111011010000101111000000110000001010100000000000001011110000011011111000101000101111000000101111010101100000001011000000000000000000011000111100000101110001000111000000110000010111000000001011100000000000010001110000011100000101110001110011010000101111000000110000001100000000000000001011110000011011111000101000101111000000101111010101100000001100100000000000000000011000111100000110100001000111000000110000011010000000001101000000000000010001110000011100000110100011000001010110111111111111110000001101100000000000
1669266: 1010010110100101101001011010011100001010101000010
1689953: 111111111111110000101000000100001001111010011111111111100011111101100000000000000000000001000000000000010011111111111111111111111111110011111110000000000000011000010100001111110101010011111111111111111111111111110011111111000000000000111111111111111111111111111100001011111111110001111111010011111111100000000000
1746862: 1010010110100101101001011010011000001010101000010
1767523: 00111111000001111111111111100011111100001111111111111110001111110001011111111111111100111111000111111111111111110011111100100111111111111111001111110010101111111111111100111111001101111111111111110011111100111011111111111111001111110100011111111111111100111111010010111111111111110011111101010111111111111111001111110101101111111111111100111111011001111111111111110011111101101000010100000011001111110111000001001111010100111111011110111111111111000011111110000000000000001000001111111000100000000000100100111111100101111111111111100011111110011111111111111110001111111010011111111111111100111111101011111111111111110011111110110111111111111111001111111011111111111111111100111111110000110000101000010011111111001111111010101001001111111101011111111111111100111111110111111111111111110011111111100011111111111111001111111110111111111111111100111111111100000101111111110011111111111110001111111011
1801641: 1010010110100101101001011010011000011010101000010
1832399: 0000000000000000000011100000000000000000110111100000000000000000000100000011000001000000000000011111111111011010000000000010000000110001011000000000001011111111110111010000000000110000001100110100000000000011110111110000000100000000010000000011001101100000000001001101111000111000000000000101000000110000011000000000010110111111111111000000000001100101010111111110000000000110101000001010100100000000011101111111110110100000000001111001011100000011000000001000001111110010001100000000100010011110000010100000000010010001011100000001000000001001101101011010000000000000101001100000001001100000000010101011111100100001000000001011000000001100011100000000101111100000001011010000000011000010001100000000000000001100101000000010110100000000110100111011001000010000000011011011000110100001000000001110001000000011011100000000111011011110000000110000000011110011001010100001000000001111110111111111111000000001000000011000000000110000000100001000001100010110000000010001000101110000001000000001000110110101101000000000000100100010000001000110000000010010101101101010000100000001001101100000100111110000000100111101111000001001000000010100000000110001000100000001010010110001101000000000000101010010000001010010000000010101110111100000010100000001011000000011000001010000000101101010011000001000000000010111001001100000101000000001011111011110110111010000000110000001011100000101000000011000110111100000000000000001100100010111000001100000000110011000000000001100000000011010000101100000100000000001101010000000000011100000000110110001000000001010000000011011101010110000100000000001110000101101000010100000000111001010000000001001000000011101001001010000010100000001110110100001000001110000000111100011010010000001000000011110111000000110011100000001111100111111001000010000000111111011010110100001000000100000011000000111111100000010000010101011000010010000001000010010110100001011000000100001100010110010000100000010001000110001101000010000001000101010000010001000000000100011001100101010000100000010001110100000011111110000001001000011101100100001000000100100101101011010000100000010010100100000100100110000001001011011000110100001000000100110011000001001011100000010011010110110101000010000001001110010000001010111000000100111101100011010000100000010100001100000100111110000001010001011011010100001000000101001001000000010001100000010100110100000101001110000001010100000001100010111000000101010101111011010001100000010101100111101101000000000001010111101111000000111000000101100000101111000001100000010110011011111000101000000001011010001011110000000000000101101110111101010110000000010111000000000110001100000001011101110000010111000000000101111001000111000000000000010111111100000101110010000001100000010001110000011000000110000111000001011100100000011000100111001101000010000001100011101111000000111000000110010000101111000001100000011001011011111000101000000001100110001011110000000000000110011110111101010110000000011010000000000110001100000001101001110000011010000000000110101001000111000000000000011010111100000110100010000001101100010001110000011000000110110111000001101000100000011011101100000101011010000001101111111111111111111
1890615: 1010010110100101101001011010011000011010101000010
1935310: 1010010110100101101001011010011000001010101000010
2004366: 1010010110100101101001011010011100011010101000010
2035112: 000000011100001011110000000000000110000010111111111011010000000000000000000000000001100010111111111110111000000110011010101111100000000000000000100000000000000001100110111011110001110000000110000011111111111111100000000001000000000000101010111111111100000101010011111111101101001011100000010000000001100000000000011111100100011011110000010100101110000000011010110100000000000010000000000000110000000100110111111001000000000001100011110000000101100000000010100000000000010001100000001100000001011001110110010000011000110100000000000011000000000000110000000110111011110000000101100101010000101111111111110000000011100000000000001100000000010000011000101100101110000001011010110100000000000100000000000000110000001000110110110101000011000001001111101111000001000000000100100000000000000001100010000110001101000011000000101001101111000000100000000101000000000000000001100000100100110000010001001100000101101111011011100000000101100000000000001011100000101011110000000000101110000011000000000001100000000110000000000000001011000001000000000000011100100000000101010101100001000000000110100000000000010110100001010100000000010001001010000010010000100000110000000111000000000000011010010000001100000011001101111110010000011010110100000000000111100000000000110000001111110101011000010001011010000101000101100100000000001000000000000000011000110100001100000100010001100101010000110000001111110000001000100000000000011101100100000110101101000011000001001001011000110100000000001001000000000000110000010010110110110101000011000000101011011000110100000000001001100000000000110000010011110110110101000011000000010001110000010100110000001010000000000000000001100010110111101101000101111011010000101111000000110000001010100000000000001011110000011011111000101000101111000000101111010101100000001011000000000000000000011000111100000101110001000111000000110000010111000000001011100000000000010001110000011100000101110001110011010000101111000000110000001100000000000000001011110000011011111000101000101111000000101111010101100000001100100000000000000000011000111100000110100001000111000000110000011010000000001101000000000000010001110000011100000110100011000001010110111111111111110000001101100000000000
2110976: 0
2223667: 00
2230308: 00
2237010: 0
2277626: 1101001010001110
2301113: 0
2304898: 11010010100011100
2333060: 0
2445751: 00
2452389: 00
2459091: 0
2489632: 1101001010001110
2523220: 0
2527007: 11010010100011100
2584511: 1010010110100101101001011010011100001010101000010
2605196: 111111111111110000101000000100001001111010011111111111100011111101100000000000000000000001000000000000010011111111111111111111111111110011111110000000000000011000010100001111110101010011111111111111111111111111110011111111000000000000111111111111111111111111111100001010000010110001111111010011111111100000000000
2634228: 1010010110100101101001011010011000001010101000010
2664969: 00111111000001111111111111100011111100001011111111111110001111110001001111111111111100111111000110111111111111110011111100100111111111111111001111110010101111111111111100111111001100111111111111110011111100111011111111111111001111110100011111111111111100111111010010111111111111110011111101010011111111111111001111110101101111111111111100111111011001111111111111110011111101101000010100000011001111110111000001001111010100111111011110111111111111000011111110000000000000001000001111111000100000000000100100111111100101111111111111100011111110011011111111111110001111111010011111111111111100111111101011111111111111110011111110110111111111111111001111111011111111111111111100111111110000110000101000010011111111001111111010101001001111111101011111111111111100111111110111111111111111110011111111100011111111111111001111111110111111111111111100111111111100000101000001010011111111111110001111111011
2699086: 1010010110100101101001011010011000001010101000010
2743782: 1010010110100101101001011010011100001010101000010
2774546: 111111111111110000101000000100001001111010011111111111100011111101100000000000000000000001000000000000010011111111111111111111111111110011111110000000000000011000010100001111110101010011111111111111111111111111110011111111000000000000111111111111111111111111111100001010000010110001111111010011111111100000000000
Exec.bin: 00000001110000 10111100000000 00000110000010 11111111101101 00000110001011 11111111101110 00000110011010 10111110000000 00000110011011 10111100011100 00000110000011 11111111111110 10101011111111 11000001010100 11111111101101 00101110000001 01111110010001 10111100000101 00101110000000 01101011010000 11000000010011 01111110010000 00000001100011 11000000010110 01000110000000 11000000010110 01110110010000 01100011010000 11000000011011 10111100000001 01100101010000 10111111111111 00110000000001 00000110001011 00101110000001 01101011010000 11000000100011 01101101010000 11000001001111 10111100000100 00000110001000 01100011010000 11000000101001 10111100000010 00000110000010 01001100000100 01001100000101 10111101101110 00101110000010 10111100000000 00101110000011 00000000000110 00101100000100 00000000000111 00100000000101 01010110000100 01011010000101 01000000000100 01001010000010 01000010000011 01101001000000 11000000110011 01111110010000 01101011010000 11000000111111 01010110000100 01011010000101 00010110010000 01100011010000 11000001000100 01100101010000 11000000111111 01110110010000 01101011010000 11000001001001 01100011010000 11000001001011 01101101010000 11000000101011 01100011010000 11000001001111 01101101010000 11000000010001 11000001010011 00000110001011 01111011010001 01111011010000 10111100000011 00101111000001 10111110001010 00101111000000 10111101010110 00000001100011 11000001011100 01000111000000 11000001011100 01000111000001 11000001011100 01110011010000 10111100000011 00101111000001 10111110001010 00101111000000 10111101010110 00000001100011 11000001101000 01000111000000 11000001101000 01000111000001 11000001101000 11000001010110 11111111111111
1620117: 00000001110000 10111100000000 00000110000010 11111111101101 0000000000000000000000 00000110001011 11111111101110 00000110011010 10111110000000 0000000000100000000000 00000110011011 10111100011100 00000110000011 11111111111110 0000000001000000000000 10101011111111 11000001010100 11111111101101 00101110000001 0000000001100000000000 01111110010001 10111100000101 00101110000000 01101011010000 0000000010000000000000 11000000010011 01111110010000 00000001100011 11000000010110 0000000010100000000000 01000110000000 11000000010110 01110110010000 01100011010000 0000000011000000000000 11000000011011 10111100000001 01100101010000 10111111111111 0000000011100000000000 00110000000001 00000110001011 00101110000001 01101011010000 0000000100000000000000 11000000100011 01101101010000 11000001001111 10111100000100 0000000100100000000000 00000110001000 01100011010000 11000000101001 10111100000010 0000000101000000000000 00000110000010 01001100000100 01001100000101 10111101101110 0000000101100000000000 00101110000010 10111100000000 00101110000011 00000000000110 0000000110000000000000 00101100000100 00000000000111 00100000000101 01010110000100 0000000110100000000000 01011010000101 01000000000100 01001010000010 01000010000011 0000000111000000000000 01101001000000 11000000110011 01111110010000 01101011010000 0000000111100000000000 11000000111111 01010110000100 01011010000101 00010110010000 0000001000000000000000 01100011010000 11000001000100 01100101010000 11000000111111 0000001000100000000000 01110110010000 01101011010000 11000001001001 01100011010000 0000001001000000000000 11000001001011 01101101010000 11000000101011 01100011010000 0000001001100000000000 11000001001111 01101101010000 11000000010001 11000001010011 0000001010000000000000 00000110001011 01111011010001 01111011010000 10111100000011 0000001010100000000000 00101111000001 10111110001010 00101111000000 10111101010110 0000001011000000000000 00000001100011 11000001011100 01000111000000 11000001011100 0000001011100000000000 01000111000001 11000001011100 01110011010000 10111100000011 0000001100000000000000 00101111000001 10111110001010 00101111000000 10111101010110 0000001100100000000000 00000001100011 11000001101000 01000111000000 11000001101000 0000001101000000000000 01000111000001 11000001101000 11000001010110 11111111111111 0000001101100000000000
1009 : 1010010110100101101001011010011000001010101000010
55103 READ: 1010010110100101101001011010011000011010101000010 001111110111101111111111110000111111100000000000000001100011111110001000000000000111
92201 : 1010010110100101101001011010001100011010101000010 0000
158597 : 1010010110100101101001011010011001111010101000010
737022 : 1010010110100101101001011010011100001010101000010 000000000001001111111111111111111111111111111111111111110011111110000000000000
784240 : 1010010110100101101001011010011000001010101000010
820818 : 1010010110100101101001011010011100001010101000010 111111111111110000000000010011111111111111111111111111110011111110000000000000
868054 : 1010010110100101101001011010011000001010101000010
904632 : 1010010110100101101001011010011000001010101000010
949230 : 1010010110100101101001011010011000001010101000010 00111111000001111111111111100011111100001011111111111110001111110001001111111111111100111111000110111111111111110011111100100111111111111111001111110010101111111111111100111111001100111111111111110011111100111011111111111111001111110100011111111111111100111111010010111111111111110011111101010011111111111111001111110101111111111111111100111111011001111111111111110011111101101000010100000011001111110111000001001111010100111111011110111111111111000011111110000000000000001000001111111000100000000000100100111111100101111111111111100011111110011111111111111110001111111010011111111111111100111111101011111111111111110011111110110111111111111111001111111011111111111111111100111111110000111111111111110011111111001111111111111111001111111101001111111111111100111111110111111111111111110011111111100011111111111111001111111110111111111111111100111111111100111111111111110011111111111111111111111111
1004046 READ: 1010010110100101101001011010011000011010101000010
1589373 WRITE: 1010010110100101101001011010011100011010101000010 000000011100001011110000000000000110000010111111111011010000000000000000000000000001100010111111111110111000000110011010101111100000000000000000100000000000000001100110111011110001110000000110000011111111111111100000000001000000000000101010111111111100000101010011111111101101001011100000010000000001100000000000011111100100011011110000010100101110000000011010110100000000000010000000000000110000000100110111111001000000000001100011110000000101100000000010100000000000010001100000001100000001011001110110010000011000110100000000000011000000000000110000000110111011110000000101100101010000101111111111110000000011100000000000001100000000010000011000101100101110000001011010110100000000000100000000000000110000001000110110110101000011000001001111101111000001000000000100100000000000000001100010000110001101000011000000101001101111000000100000000101000000000000000001100000100100110000010001001100000101101111011011100000000101100000000000001011100000101011110000000000101110000011000000000001100000000110000000000000001011000001000000000000011100100000000101010101100001000000000110100000000000010110100001010100000000010001001010000010010000100000110000000111000000000000011010010000001100000011001101111110010000011010110100000000000111100000000000110000001111110101011000010001011010000101000101100100000000001000000000000000011000110100001100000100010001100101010000110000001111110000001000100000000000011101100100000110101101000011000001001001011000110100000000001001000000000000110000010010110110110101000011000000101011011000110100000000001001100000000000110000010011110110110101000011000000010001110000010100110000001010000000000000000001100010110111101101000101111011010000101111000000110000001010100000000000001011110000011011111000101000101111000000101111010101100000001011000000000000000000011000111100000101110001000111000000110000010111000000001011100000000000010001110000011100000101110001110011010000101111000000110000001100000000000000001011110000011011111000101000101111000000101111010101100000001100100000000000000000011000111100000110100001000111000000110000011010000000001101000000000000010001110000011100000110100011000001010110111111111111110000001101100000000000
1669266 : 1010010110100101101001011010011100001010101000010 111111111111110000101000000100001001111010011111111111100011111101100000000000000000000001000000000000010011111111111111111111111111110011111110000000000000011000010100001111110101010011111111111111111111111111110011111111000000000000111111111111111111111111111100001011111111110001111111010011111111100000000000
1746862 : 1010010110100101101001011010011000001010101000010 00111111000001111111111111100011111100001111111111111110001111110001011111111111111100111111000111111111111111110011111100100111111111111111001111110010101111111111111100111111001101111111111111110011111100111011111111111111001111110100011111111111111100111111010010111111111111110011111101010111111111111111001111110101101111111111111100111111011001111111111111110011111101101000010100000011001111110111000001001111010100111111011110111111111111000011111110000000000000001000001111111000100000000000100100111111100101111111111111100011111110011111111111111110001111111010011111111111111100111111101011111111111111110011111110110111111111111111001111111011111111111111111100111111110000110000101000010011111111001111111010101001001111111101011111111111111100111111110111111111111111110011111111100011111111111111001111111110111111111111111100111111111100000101111111110011111111111110001111111011
1801641 READ: 1010010110100101101001011010011000011010101000010 0000000000000000000011100000000000000000110111100000000000000000000100000011000001000000000000011111111111011010000000000010000000110001011000000000001011111111110111010000000000110000001100110100000000000011110111110000000100000000010000000011001101100000000001001101111000111000000000000101000000110000011000000000010110111111111111000000000001100101010111111110000000000110101000001010100100000000011101111111110110100000000001111001011100000011000000001000001111110010001100000000100010011110000010100000000010010001011100000001000000001001101101011010000000000000101001100000001001100000000010101011111100100001000000001011000000001100011100000000101111100000001011010000000011000010001100000000000000001100101000000010110100000000110100111011001000010000000011011011000110100001000000001110001000000011011100000000111011011110000000110000000011110011001010100001000000001111110111111111111000000001000000011000000000110000000100001000001100010110000000010001000101110000001000000001000110110101101000000000000100100010000001000110000000010010101101101010000100000001001101100000100111110000000100111101111000001001000000010100000000110001000100000001010010110001101000000000000101010010000001010010000000010101110111100000010100000001011000000011000001010000000101101010011000001000000000010111001001100000101000000001011111011110110111010000000110000001011100000101000000011000110111100000000000000001100100010111000001100000000110011000000000001100000000011010000101100000100000000001101010000000000011100000000110110001000000001010000000011011101010110000100000000001110000101101000010100000000111001010000000001001000000011101001001010000010100000001110110100001000001110000000111100011010010000001000000011110111000000110011100000001111100111111001000010000000111111011010110100001000000100000011000000111111100000010000010101011000010010000001000010010110100001011000000100001100010110010000100000010001000110001101000010000001000101010000010001000000000100011001100101010000100000010001110100000011111110000001001000011101100100001000000100100101101011010000100000010010100100000100100110000001001011011000110100001000000100110011000001001011100000010011010110110101000010000001001110010000001010111000000100111101100011010000100000010100001100000100111110000001010001011011010100001000000101001001000000010001100000010100110100000101001110000001010100000001100010111000000101010101111011010001100000010101100111101101000000000001010111101111000000111000000101100000101111000001100000010110011011111000101000000001011010001011110000000000000101101110111101010110000000010111000000000110001100000001011101110000010111000000000101111001000111000000000000010111111100000101110010000001100000010001110000011000000110000111000001011100100000011000100111001101000010000001100011101111000000111000000110010000101111000001100000011001011011111000101000000001100110001011110000000000000110011110111101010110000000011010000000000110001100000001101001110000011010000000000110101001000111000000000000011010111100000110100010000001101100010001110000011000000110110111000001101000100000011011101100000101011010000001101111111111111111111
1890615 READ: 1010010110100101101001011010011000011010101000010
1935310 : 1010010110100101101001011010011000001010101000010
2004366 WRITE: 1010010110100101101001011010011100011010101000010 000000011100001011110000000000000110000010111111111011010000000000000000000000000001100010111111111110111000000110011010101111100000000000000000100000000000000001100110111011110001110000000110000011111111111111100000000001000000000000101010111111111100000101010011111111101101001011100000010000000001100000000000011111100100011011110000010100101110000000011010110100000000000010000000000000110000000100110111111001000000000001100011110000000101100000000010100000000000010001100000001100000001011001110110010000011000110100000000000011000000000000110000000110111011110000000101100101010000101111111111110000000011100000000000001100000000010000011000101100101110000001011010110100000000000100000000000000110000001000110110110101000011000001001111101111000001000000000100100000000000000001100010000110001101000011000000101001101111000000100000000101000000000000000001100000100100110000010001001100000101101111011011100000000101100000000000001011100000101011110000000000101110000011000000000001100000000110000000000000001011000001000000000000011100100000000101010101100001000000000110100000000000010110100001010100000000010001001010000010010000100000110000000111000000000000011010010000001100000011001101111110010000011010110100000000000111100000000000110000001111110101011000010001011010000101000101100100000000001000000000000000011000110100001100000100010001100101010000110000001111110000001000100000000000011101100100000110101101000011000001001001011000110100000000001001000000000000110000010010110110110101000011000000101011011000110100000000001001100000000000110000010011110110110101000011000000010001110000010100110000001010000000000000000001100010110111101101000101111011010000101111000000110000001010100000000000001011110000011011111000101000101111000000101111010101100000001011000000000000000000011000111100000101110001000111000000110000010111000000001011100000000000010001110000011100000101110001110011010000101111000000110000001100000000000000001011110000011011111000101000101111000000101111010101100000001100100000000000000000011000111100000110100001000111000000110000011010000000001101000000000000010001110000011100000110100011000001010110111111111111110000001101100000000000
2110976 : 0000001101001010001110011010010100011100
2333060 : 0000001101001010001110011010010100011100
2584511 : 1010010110100101101001011010011100001010101000010 111111111111110000101000000100001001111010011111111111100011111101100000000000000000000001000000000000010011111111111111111111111111110011111110000000000000011000010100001111110101010011111111111111111111111111110011111111000000000000111111111111111111111111111100001010000010110001111111010011111111100000000000
2634228 : 1010010110100101101001011010011000001010101000010 00111111000001111111111111100011111100001011111111111110001111110001001111111111111100111111000110111111111111110011111100100111111111111111001111110010101111111111111100111111001100111111111111110011111100111011111111111111001111110100011111111111111100111111010010111111111111110011111101010011111111111111001111110101101111111111111100111111011001111111111111110011111101101000010100000011001111110111000001001111010100111111011110111111111111000011111110000000000000001000001111111000100000000000100100111111100101111111111111100011111110011011111111111110001111111010011111111111111100111111101011111111111111110011111110110111111111111111001111111011111111111111111100111111110000110000101000010011111111001111111010101001001111111101011111111111111100111111110111111111111111110011111111100011111111111111001111111110111111111111111100111111111100000101000001010011111111111110001111111011
2699086 : 1010010110100101101001011010011000001010101000010
2743782 : 1010010110100101101001011010011100001010101000010 111111111111110000101000000100001001111010011111111111100011111101100000000000000000000001000000000000010011111111111111111111111111110011111110000000000000011000010100001111110101010011111111111111111111111111110011111111000000000000111111111111111111111111111100001010000010110001111111010011111111100000000000
COMMAND:
1010010110100101101001011010011000011010101000010
ADDRESS DATA ?
0000000000000 00000001110000 0
0000000000001 10111100000000 0
0000000000010 00000110000010 0
0000000000011 11111111101101 0
0000000000100 00000110001011 0
0000000000101 11111111101110 1
0000000000110 00000110011010 0
0000000000111 10111110000000 1
0000000001000 00000110011011 0
0000000001001 10111100011100 0
0000000001010 00000110000011 0
0000000001011 01111111111110 0
0000000001100 10101011111111 0
0000000001101 01000001010100 1
0000000001110 11111111101101 0
0000000001111 00101110000001 1
0000000010000 01111110010001 1
0000000010001 00111100000101 0
0000000010010 00101110000000 1
0000000010011 01101011010000 0
0000000010100 11000000010011 0
0000000010101 01111110010000 1
0000000010110 00000001100011 1
0000000010111 11000000010110 1
0000000011000 01000110000000 0
0000000011001 01000000010110 1
0000000011010 01110110010000 1
0000000011011 01100011010000 1
0000000011100 01000000011011 1
0000000011101 10111100000001 1
0000000011110 01100101010000 1
0000000011111 10111111111111 0
0000000100000 00110000000001 1
0000000100001 00000110001011 0
0000000100010 00101110000001 0
0000000100011 01101011010000 0
0000000100100 01000000100011 0
0000000100101 01101101010000 1
0000000100110 11000001001111 1
0000000100111 10111100000100 1
0000000101000 00000110001000 1
0000000101001 01100011010000 0
0000000101010 01000000101001 0
0000000101011 10111100000010 1
0000000101100 00000110000010 1
0000000101101 01001100000100 0
0000000101110 01001100000101 0
0000000101111 10111101101110 1
0000000110000 00101110000010 1
0000000110001 10111100000000 0
0000000110010 00101110000011 0
0000000110011 00000000000110 0
0000000110100 00101100000100 0
0000000110101 00000000000111 0
0000000110110 00100000000101 0
0000000110111 01010110000100 0
0000000111000 01011010000101 0
0000000111001 01000000000100 1
0000000111010 01001010000010 1
0000000111011 01000010000011 1
0000000111100 01101001000000 1
0000000111101 11000000110011 1
0000000111110 01111110010000 1
0000000111111 01101011010000 1
0000001000000 11000000111111 1
0000001000001 01010110000100 1
0000001000010 01011010000101 1
0000001000011 00010110010000 1
0000001000100 01100011010000 1
0000001000101 01000001000100 0
0000001000110 01100101010000 1
0000001000111 01000000111111 1
0000001001000 01110110010000 1
0000001001001 01101011010000 1
0000001001010 01000001001001 1
0000001001011 01100011010000 1
0000001001100 11000001001011 1
0000001001101 01101101010000 1
0000001001110 01000000101011 1
0000001001111 01100011010000 1
0000001010000 11000001001111 1
0000001010001 01101101010000 1
0000001010010 01000000010001 1
0000001010011 01000001010011 1
0000001010100 00000110001011 1
0000001010101 01111011010001 1
0000001010110 01111011010000 0
0000001010111 10111100000011 1
0000001011000 00101111000001 1
0000001011001 10111110001010 0
0000001011010 00101111000000 0
0000001011011 10111101010110 0
0000001011100 00000001100011 0
0000001011101 11000001011100 0
0000001011110 01000111000000 0
0000001011111 11000001011100 1
0000001100000 01000111000001 1
0000001100001 11000001011100 1
0000001100010 01110011010000 1
0000001100011 10111100000011 1
0000001100100 00101111000001 1
0000001100101 10111110001010 0
0000001100110 00101111000000 0
0000001100111 10111101010110 0
0000001101000 00000001100011 0
0000001101001 11000001101000 0
0000001101010 01000111000000 0
0000001101011 11000001101000 1
0000001101100 01000111000001 1
0000001101101 11000001101000 1
0000001101110 11000001010110 1
0000001101111 11111111111111 1
COMMAND:
1010010110100101101001011010011000011010101000010
ADDRESS DATA ?
0011111101111 01111111111110 0
0011111110000 00000000000011 0
0011111110001 00000000000011 1
I wonder what's with 2110976 and 2333060, as they are not following the format of the rest - maybe it's something running on the microcontroller?
I am not sure what the last bit could be, but the "data" is 1:1 the binary code that had just been programmed previously in the flash.
1207: FLASH_READ_1
No data (dummy read)
27385: FLASH_READ_2
No data (dummy read)
72043: FLASH_READ_2
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 1FFF 1
07E4 3FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 3FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0025 0
07F1 0025 1
07F2 3FFF 0
07F3 1FFF 0
07F4 3FFF 1
07F5 1FFF 1
07F6 3FFF 1
07F7 1FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 1FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
126900: FLASH_READ_2
No data (dummy read)
1209: FLASH_READ_B
No data (dummy read)
55304: FLASH_READ_B
ADDR DATA ?
-----------
07EF 1FFE 0
07F0 0021 0
07F1 0021 1
102483: ??? (1010010110100101101001011010001100001010101000010)
178976: ??? (1010010110100101101001011010011001111010101000010)
747185: FLASH_WRITE
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 0022 3FFF 3FFF 3FFF
794400: FLASH_READ_A
No data (dummy read)
830958: ??? (1010010110100101101001011010011100001010101000010)
878196: FLASH_READ_B
No data (dummy read)
914794: FLASH_READ_A
No data (dummy read)
959391: FLASH_READ_B
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0022 0
07F1 0022 1
07F2 3FFF 0
07F3 1FFF 0
07F4 3FFF 1
07F5 1FFF 1
07F6 1FFF 1
07F7 1FFF 1
07F8 3FFF 1
07F9 1FFF 1
07FA 1FFF 1
07FB 1FFF 1
07FC 3FFF 1
07FD 1FFF 1
07FE 3FFF 1
07FF 3FFF 1
1014210: FLASH_READ_B
No data (dummy read)
1209: FLASH_READ_B
No data (dummy read)
27386: FLASH_READ_B
No data (dummy read)
72043: FLASH_READ_A
ADDR DATA ?
-----------
07E0 1FFF 0
07E1 1FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 1FFF 1
07E7 3FFF 1
07E8 1FFF 1
07E9 3FFF 1
07EA 1FFF 1
07EB 3FFF 1
07EC 1FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 001F 0
07F1 001F 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
136979: FLASH_READ_A
No data (dummy read)
695006: FLASH_READ_B
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 3FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 3FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 001F 0
07F1 001F 1
07F2 3FFF 0
07F3 1FFF 0
07F4 3FFF 1
07F5 1FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 1FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
749723: FLASH_READ_B
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 3FFF 1
07E5 1FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 001F 0
07F1 001F 1
07F2 3FFF 0
07F3 3FFF 0
07F4 1FFF 1
07F5 3FFF 1
07F6 1FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 1FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
804580: FLASH_READ_A
ADDR DATA ?
-----------
0000 0070 0
0001 2F00 0
0002 0182 0
0003 3FED 0
0004 018B 0
0005 3FEE 1
0006 019A 0
0007 2F80 1
0008 019B 0
0009 2F1C 0
000A 0183 0
000B 3FFE 0
000C 0AFF 0
000D 3054 1
000E 1FED 0
000F 0B81 1
0010 1F91 1
0011 2F05 0
0012 0B80 1
0013 1AD0 0
0014 3013 0
0015 1F90 1
0016 0063 1
0017 3016 1
0018 1180 0
0019 3016 1
001A 1D90 1
001B 18D0 1
001C 301B 1
001D 2F01 1
001E 1950 1
001F 2FFF 0
0020 0C01 1
0021 018B 0
0022 0B81 0
0023 1AD0 0
0024 3023 0
0025 1B50 1
0026 304F 1
0027 2F04 1
0028 0188 1
0029 18D0 0
002A 3029 0
002B 0F02 1
002C 0182 1
002D 1304 0
002E 1305 0
002F 0F6E 1
0030 0B82 1
0031 0F00 0
0032 0B83 0
0033 0006 0
0034 0B04 0
0035 0007 0
0036 0805 0
0037 1584 0
0038 1685 0
0039 1004 1
003A 1282 1
003B 1083 1
003C 1A40 1
003D 3033 1
003E 1F90 1
003F 1AD0 1
0040 303F 1
0041 1584 1
0042 1685 1
0043 0590 1
0044 18D0 1
0045 3044 0
0046 1950 1
0047 303F 1
0048 1D90 1
0049 1AD0 1
004A 3049 1
004B 18D0 1
004C 104B 1
004D 1B50 1
004E 302B 1
004F 18D0 1
0050 104F 1
0051 1B50 1
0052 3011 1
0053 3053 1
0054 018B 1
0055 1ED1 1
0056 1ED0 0
0057 2F03 1
0058 0BC1 1
0059 2F8A 0
005A 0BC0 0
005B 2F56 0
005C 0063 0
005D 305C 0
005E 11C0 0
005F 305C 1
0060 11C1 1
0061 305C 1
0062 1CD0 1
0063 2F03 1
0064 0BC1 1
0065 2F8A 0
0066 0BC0 0
0067 2F56 0
0068 0063 0
0069 1068 0
006A 11C0 0
006B 3068 1
006C 11C1 1
006D 3068 1
006E 1056 1
006F 1FFF 1
0070 3FFF 1
0071 1FFF 1
0072 3FFF 1
0073 1FFF 1
0074 3FFF 1
0075 1FFF 1
0076 3FFF 1
0077 1FFF 1
0078 3FFF 1
0079 1FFF 1
007A 3FFF 1
007B 1FFF 1
007C 3FFF 1
007D 1FFF 1
007E 3FFF 1
007F 3FFF 1
0080 1FFF 1
0081 3FFF 1
0082 1FFF 1
0083 3FFF 1
0084 1FFF 1
0085 3FFF 1
0086 1FFF 1
0087 3FFF 1
0088 1FFF 1
0089 3FFF 1
008A 3FFF 1
008B 3FFF 1
008C 1FFF 1
008D 3FFF 1
008E 3FFF 1
008F 3FFF 1
0090 1FFF 1
0091 3FFF 1
0092 3FFF 1
0093 3FFF 1
0094 1FFF 1
0095 3FFF 1
0096 3FFF 1
0097 3FFF 1
0098 3FFF 1
0099 3FFF 1
009A 3FFF 1
009B 3FFF 1
009C 3FFF 1
009D 3FFF 1
009E 3FFF 1
009F 3FFF 1
00A0 3FFF 1
00A1 3FFF 1
00A2 3FFF 1
00A3 3FFF 1
00A4 3FFF 1
00A5 3FFF 1
00A6 3FFF 1
00A7 3FFF 1
00A8 3FFF 1
00A9 3FFF 1
00AA 3FFF 1
00AB 3FFF 1
00AC 3FFF 1
00AD 3FFF 1
00AE 3FFF 1
00AF 1FFF 1
00B0 3FFF 1
00B1 1FFF 1
00B2 1FFF 1
00B3 1FFF 1
00B4 3FFF 1
00B5 1FFF 1
00B6 1FFF 1
00B7 1FFF 1
00B8 3FFF 1
00B9 1FFF 1
00BA 1FFF 1
00BB 1FFF 1
00BC 3FFF 1
00BD 1FFF 1
00BE 1FFF 1
00BF 3FFF 1
00C0 1FFF 1
00C1 1FFF 1
00C2 1FFF 1
00C3 3FFF 1
00C4 1FFF 1
00C5 3FFF 1
00C6 1FFF 1
00C7 3FFF 1
00C8 1FFF 1
00C9 3FFF 1
00CA 3FFF 1
00CB 3FFF 1
00CC 1FFF 1
00CD 3FFF 1
00CE 3FFF 1
00CF 3FFF 1
00D0 1FFF 1
00D1 3FFF 1
00D2 3FFF 1
00D3 3FFF 1
00D4 1FFF 1
00D5 3FFF 1
00D6 3FFF 1
00D7 3FFF 1
00D8 1FFF 1
00D9 3FFF 1
00DA 3FFF 1
00DB 3FFF 1
00DC 3FFF 1
00DD 3FFF 1
00DE 3FFF 1
00DF 3FFF 1
00E0 3FFF 1
00E1 3FFF 1
00E2 3FFF 1
00E3 3FFF 1
00E4 3FFF 1
00E5 3FFF 1
00E6 3FFF 1
00E7 3FFF 1
00E8 3FFF 1
00E9 3FFF 1
00EA 3FFF 1
00EB 3FFF 1
00EC 3FFF 1
00ED 3FFF 1
00EE 3FFF 1
00EF 3FFF 1
00F0 3FFF 1
00F1 1FFF 1
00F2 1FFF 1
00F3 1FFF 1
00F4 3FFF 1
00F5 1FFF 1
00F6 1FFF 1
00F7 1FFF 1
00F8 3FFF 1
00F9 1FFF 1
00FA 1FFF 1
00FB 1FFF 1
00FC 3FFF 1
00FD 1FFF 1
00FE 1FFF 1
00FF 1FFF 1
0100 1FFF 1
0101 1FFF 1
0102 1FFF 1
0103 1FFF 1
0104 1FFF 1
0105 3FFF 1
0106 1FFF 1
0107 3FFF 1
0108 3FFF 1
0109 3FFF 1
010A 3FFF 1
010B 3FFF 1
010C 1FFF 1
010D 3FFF 1
010E 3FFF 1
010F 3FFF 1
0110 1FFF 1
0111 3FFF 1
0112 3FFF 1
0113 3FFF 1
0114 1FFF 1
0115 3FFF 1
0116 3FFF 1
0117 3FFF 1
0118 1FFF 1
0119 3FFF 1
011A 3FFF 1
011B 3FFF 1
011C 3FFF 1
011D 3FFF 1
011E 3FFF 1
011F 3FFF 1
0120 3FFF 1
0121 3FFF 1
0122 3FFF 1
0123 3FFF 1
0124 3FFF 1
0125 3FFF 1
0126 3FFF 1
0127 3FFF 1
0128 3FFF 1
0129 3FFF 1
012A 3FFF 1
012B 3FFF 1
012C 3FFF 1
012D 3FFF 1
012E 3FFF 1
012F 3FFF 1
0130 3FFF 1
0131 3FFF 1
0132 3FFF 1
0133 3FFF 1
0134 3FFF 1
0135 1FFF 1
0136 1FFF 1
0137 1FFF 1
0138 3FFF 1
0139 1FFF 1
013A 1FFF 1
013B 1FFF 1
013C 3FFF 1
013D 1FFF 1
013E 1FFF 1
013F 1FFF 1
0140 3FFF 1
0141 1FFF 1
0142 1FFF 1
0143 1FFF 1
0144 1FFF 1
0145 1FFF 1
0146 1FFF 1
0147 1FFF 1
0148 3FFF 1
0149 3FFF 1
014A 3FFF 1
014B 3FFF 1
014C 3FFF 1
014D 3FFF 1
014E 3FFF 1
014F 3FFF 1
0150 1FFF 1
0151 3FFF 1
0152 3FFF 1
0153 3FFF 1
0154 1FFF 1
0155 3FFF 1
0156 3FFF 1
0157 3FFF 1
0158 1FFF 1
0159 3FFF 1
015A 3FFF 1
015B 3FFF 1
015C 1FFF 1
015D 3FFF 1
015E 3FFF 1
015F 3FFF 1
0160 3FFF 1
0161 3FFF 1
0162 3FFF 1
0163 3FFF 1
0164 3FFF 1
0165 3FFF 1
0166 3FFF 1
0167 3FFF 1
0168 3FFF 1
0169 3FFF 1
016A 3FFF 1
016B 3FFF 1
016C 3FFF 1
016D 3FFF 1
016E 3FFF 1
016F 3FFF 1
0170 3FFF 1
0171 3FFF 1
0172 3FFF 1
0173 3FFF 1
0174 3FFF 1
0175 3FFF 1
0176 3FFF 1
0177 1FFF 1
0178 3FFF 1
0179 1FFF 1
017A 1FFF 1
017B 1FFF 1
017C 3FFF 1
017D 1FFF 1
017E 1FFF 1
017F 1FFF 1
0180 3FFF 1
0181 1FFF 1
0182 3FFF 1
0183 1FFF 1
0184 3FFF 1
0185 1FFF 1
0186 1FFF 1
0187 1FFF 1
0188 3FFF 1
0189 3FFF 1
018A 3FFF 1
018B 3FFF 1
018C 3FFF 1
018D 3FFF 1
018E 3FFF 1
018F 3FFF 1
0190 1FFF 1
0191 3FFF 1
0192 3FFF 1
0193 3FFF 1
0194 1FFF 1
0195 3FFF 1
0196 3FFF 1
0197 3FFF 1
0198 1FFF 1
0199 3FFF 1
019A 3FFF 1
019B 3FFF 1
019C 1FFF 1
019D 3FFF 1
019E 3FFF 1
019F 3FFF 1
01A0 1FFF 1
01A1 3FFF 1
01A2 3FFF 1
01A3 3FFF 1
01A4 3FFF 1
01A5 3FFF 1
01A6 3FFF 1
01A7 3FFF 1
01A8 3FFF 1
01A9 3FFF 1
01AA 3FFF 1
01AB 3FFF 1
01AC 3FFF 1
01AD 3FFF 1
01AE 3FFF 1
01AF 3FFF 1
01B0 3FFF 1
01B1 3FFF 1
01B2 3FFF 1
01B3 3FFF 1
01B4 3FFF 1
01B5 3FFF 1
01B6 3FFF 1
01B7 3FFF 1
01B8 3FFF 1
01B9 1FFF 1
01BA 1FFF 1
01BB 1FFF 1
01BC 3FFF 1
01BD 1FFF 1
01BE 1FFF 1
01BF 1FFF 1
01C0 3FFF 1
01C1 1FFF 1
01C2 3FFF 1
01C3 1FFF 1
01C4 3FFF 1
01C5 1FFF 1
01C6 3FFF 1
01C7 1FFF 1
01C8 3FFF 1
01C9 1FFF 1
01CA 3FFF 1
01CB 3FFF 1
01CC 3FFF 1
01CD 3FFF 1
01CE 3FFF 1
01CF 3FFF 1
01D0 3FFF 1
01D1 3FFF 1
01D2 3FFF 1
01D3 3FFF 1
01D4 1FFF 1
01D5 3FFF 1
01D6 3FFF 1
01D7 3FFF 1
01D8 1FFF 1
01D9 3FFF 1
01DA 3FFF 1
01DB 3FFF 1
01DC 1FFF 1
01DD 3FFF 1
01DE 3FFF 1
01DF 3FFF 1
01E0 1FFF 1
01E1 3FFF 1
01E2 3FFF 1
01E3 3FFF 1
01E4 3FFF 1
01E5 3FFF 1
01E6 3FFF 1
01E7 3FFF 1
01E8 3FFF 1
01E9 3FFF 1
01EA 3FFF 1
01EB 3FFF 1
01EC 3FFF 1
01ED 3FFF 1
01EE 3FFF 1
01EF 3FFF 1
01F0 3FFF 1
01F1 3FFF 1
01F2 3FFF 1
01F3 3FFF 1
01F4 3FFF 1
01F5 3FFF 1
01F6 3FFF 1
01F7 3FFF 1
01F8 3FFF 1
01F9 3FFF 1
01FA 3FFF 1
01FB 3FFF 1
01FC 3FFF 1
01FD 1FFF 1
01FE 1FFF 1
01FF 1FFF 1
0200 3FFF 1
0201 1FFF 1
0202 3FFF 1
0203 1FFF 1
0204 3FFF 1
0205 1FFF 1
0206 3FFF 1
0207 1FFF 1
0208 3FFF 1
0209 1FFF 1
020A 1FFF 1
020B 1FFF 1
020C 3FFF 1
020D 3FFF 1
020E 3FFF 1
020F 3FFF 1
0210 3FFF 1
0211 3FFF 1
0212 3FFF 1
0213 3FFF 1
0214 3FFF 1
0215 3FFF 1
0216 3FFF 1
0217 3FFF 1
0218 1FFF 1
0219 3FFF 1
021A 3FFF 1
021B 3FFF 1
021C 1FFF 1
021D 3FFF 1
021E 3FFF 1
021F 3FFF 1
0220 1FFF 1
0221 3FFF 1
0222 3FFF 1
0223 3FFF 1
0224 1FFF 1
0225 3FFF 1
0226 3FFF 1
0227 3FFF 1
0228 3FFF 1
0229 3FFF 1
022A 3FFF 1
022B 3FFF 1
022C 3FFF 1
022D 3FFF 1
022E 3FFF 1
022F 3FFF 1
0230 3FFF 1
0231 3FFF 1
0232 3FFF 1
0233 3FFF 1
0234 3FFF 1
0235 3FFF 1
0236 3FFF 1
0237 3FFF 1
0238 3FFF 1
0239 3FFF 1
023A 3FFF 1
023B 3FFF 1
023C 3FFF 1
023D 3FFF 1
023E 3FFF 1
023F 1FFF 1
0240 3FFF 1
0241 3FFF 1
0242 3FFF 1
0243 1FFF 1
0244 3FFF 1
0245 1FFF 1
0246 3FFF 1
0247 1FFF 1
0248 3FFF 1
0249 1FFF 1
024A 1FFF 1
024B 1FFF 1
024C 3FFF 1
024D 1FFF 1
024E 1FFF 1
024F 1FFF 1
0250 3FFF 1
0251 3FFF 1
0252 3FFF 1
0253 3FFF 1
0254 3FFF 1
0255 3FFF 1
0256 3FFF 1
0257 3FFF 1
0258 1FFF 1
0259 3FFF 1
025A 3FFF 1
025B 3FFF 1
025C 1FFF 1
025D 3FFF 1
025E 3FFF 1
025F 3FFF 1
0260 1FFF 1
0261 3FFF 1
0262 3FFF 1
0263 3FFF 1
0264 1FFF 1
0265 3FFF 1
0266 3FFF 1
0267 3FFF 1
0268 1FFF 1
0269 3FFF 1
026A 3FFF 1
026B 3FFF 1
026C 3FFF 1
026D 3FFF 1
026E 3FFF 1
026F 3FFF 1
0270 3FFF 1
0271 3FFF 1
0272 3FFF 1
0273 3FFF 1
0274 3FFF 1
0275 3FFF 1
0276 3FFF 1
0277 3FFF 1
0278 3FFF 1
0279 3FFF 1
027A 3FFF 1
027B 3FFF 1
027C 3FFF 1
027D 3FFF 1
027E 3FFF 1
027F 3FFF 1
0280 3FFF 1
0281 3FFF 1
0282 3FFF 1
0283 3FFF 1
0284 3FFF 1
0285 1FFF 1
0286 3FFF 1
0287 1FFF 1
0288 3FFF 1
0289 1FFF 1
028A 1FFF 1
028B 1FFF 1
028C 3FFF 1
028D 1FFF 1
028E 1FFF 1
028F 1FFF 1
0290 3FFF 1
0291 1FFF 1
0292 1FFF 1
0293 3FFF 1
0294 3FFF 1
0295 3FFF 1
0296 3FFF 1
0297 3FFF 1
0298 3FFF 1
0299 3FFF 1
029A 3FFF 1
029B 3FFF 1
029C 1FFF 1
029D 3FFF 1
029E 3FFF 1
029F 3FFF 1
02A0 1FFF 1
02A1 3FFF 1
02A2 3FFF 1
02A3 3FFF 1
02A4 1FFF 1
02A5 3FFF 1
02A6 3FFF 1
02A7 3FFF 1
02A8 1FFF 1
02A9 3FFF 1
02AA 3FFF 1
02AB 3FFF 1
02AC 3FFF 1
02AD 3FFF 1
02AE 3FFF 1
02AF 3FFF 1
02B0 3FFF 1
02B1 3FFF 1
02B2 3FFF 1
02B3 3FFF 1
02B4 3FFF 1
02B5 3FFF 1
02B6 3FFF 1
02B7 3FFF 1
02B8 3FFF 1
02B9 3FFF 1
02BA 3FFF 1
02BB 3FFF 1
02BC 3FFF 1
02BD 3FFF 1
02BE 3FFF 1
02BF 3FFF 1
02C0 3FFF 1
02C1 3FFF 1
02C2 3FFF 1
02C3 3FFF 1
02C4 3FFF 1
02C5 3FFF 1
02C6 3FFF 1
02C7 1FFF 1
02C8 3FFF 1
02C9 1FFF 1
02CA 1FFF 1
02CB 1FFF 1
02CC 3FFF 1
02CD 1FFF 1
02CE 1FFF 1
02CF 1FFF 1
02D0 3FFF 1
02D1 1FFF 1
02D2 1FFF 1
02D3 1FFF 1
02D4 3FFF 1
02D5 3FFF 1
02D6 3FFF 1
02D7 3FFF 1
02D8 3FFF 1
02D9 3FFF 1
02DA 3FFF 1
02DB 3FFF 1
02DC 3FFF 1
02DD 3FFF 1
02DE 3FFF 1
02DF 3FFF 1
02E0 1FFF 1
02E1 3FFF 1
02E2 3FFF 1
02E3 3FFF 1
02E4 1FFF 1
02E5 3FFF 1
02E6 3FFF 1
02E7 3FFF 1
02E8 1FFF 1
02E9 3FFF 1
02EA 3FFF 1
02EB 3FFF 1
02EC 1FFF 1
02ED 3FFF 1
02EE 3FFF 1
02EF 3FFF 1
02F0 3FFF 1
02F1 3FFF 1
02F2 3FFF 1
02F3 3FFF 1
02F4 3FFF 1
02F5 3FFF 1
02F6 3FFF 1
02F7 3FFF 1
02F8 3FFF 1
02F9 3FFF 1
02FA 3FFF 1
02FB 3FFF 1
02FC 3FFF 1
02FD 3FFF 1
02FE 3FFF 1
02FF 3FFF 1
0300 3FFF 1
0301 3FFF 1
0302 3FFF 1
0303 3FFF 1
0304 3FFF 1
0305 3FFF 1
0306 3FFF 1
0307 3FFF 1
0308 3FFF 1
0309 1FFF 1
030A 1FFF 1
030B 1FFF 1
030C 3FFF 1
030D 1FFF 1
030E 1FFF 1
030F 1FFF 1
0310 3FFF 1
0311 1FFF 1
0312 1FFF 1
0313 1FFF 1
0314 3FFF 1
0315 1FFF 1
0316 1FFF 1
0317 1FFF 1
0318 3FFF 1
0319 3FFF 1
031A 3FFF 1
031B 3FFF 1
031C 3FFF 1
031D 3FFF 1
031E 3FFF 1
031F 3FFF 1
0320 1FFF 1
0321 3FFF 1
0322 3FFF 1
0323 3FFF 1
0324 1FFF 1
0325 3FFF 1
0326 3FFF 1
0327 3FFF 1
0328 1FFF 1
0329 3FFF 1
032A 3FFF 1
032B 3FFF 1
032C 1FFF 1
032D 3FFF 1
032E 3FFF 1
032F 3FFF 1
0330 1FFF 1
0331 3FFF 1
0332 3FFF 1
0333 3FFF 1
0334 3FFF 1
0335 3FFF 1
0336 3FFF 1
1009: FLASH_READ_B
No data (dummy read)
55103: FLASH_READ_A
ADDR DATA ?
-----------
07EF 1FFE 0
07F0 0003 0
07F1 0003 1
92201: ??? (1010010110100101101001011010001100011010101000010)
158597: ??? (1010010110100101101001011010011001111010101000010)
737022: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 0004 3FFF 3FFF 3FFF
784240: FLASH_READ_B
No data (dummy read)
820818: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 3FFF 0004 3FFF 3FFF
868054: FLASH_READ_B
No data (dummy read)
904632: FLASH_READ_B
No data (dummy read)
949230: FLASH_READ_B
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 3FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 3FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0004 0
07F1 0004 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1FFF 1
07F9 3FFF 1
07FA 1FFF 1
07FB 3FFF 1
07FC 1FFF 1
07FD 3FFF 1
07FE 1FFF 1
07FF 3FFF 1
1004046: FLASH_READ_A
No data (dummy read)
1589373: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
0000 0070 2F00 0182 3FED
0004 018B 3FEE 019A 2F80
0008 019B 2F1C 0183 3FFE
000C 2AFF 3054 3FED 0B81
0010 1F91 2F05 0B80 1AD0
0014 3013 1F90 0063 3016
0018 1180 3016 1D90 18D0
001C 301B 2F01 1950 2FFF
0020 0C01 018B 0B81 1AD0
0024 3023 1B50 304F 2F04
0028 0188 18D0 3029 2F02
002C 0182 1304 1305 2F6E
0030 0B82 2F00 0B83 0006
0034 0B04 0007 0805 1584
0038 1685 1004 1282 1083
003C 1A40 3033 1F90 1AD0
0040 303F 1584 1685 0590
0044 18D0 3044 1950 303F
0048 1D90 1AD0 3049 18D0
004C 304B 1B50 302B 18D0
0050 304F 1B50 3011 3053
0054 018B 1ED1 1ED0 2F03
0058 0BC1 2F8A 0BC0 2F56
005C 0063 305C 11C0 305C
0060 11C1 305C 1CD0 2F03
0064 0BC1 2F8A 0BC0 2F56
0068 0063 3068 11C0 3068
006C 11C1 3068 3056 3FFF
1669266: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0004 0004 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 02FF 31FD
1746862: FLASH_READ_B
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 1FFF 1
07E6 3FFF 1
07E7 1FFF 1
07E8 3FFF 1
07E9 1FFF 1
07EA 3FFF 1
07EB 1FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0004 0
07F1 0004 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 1FFF 1
07FD 3FFF 1
07FE 02FF 1
07FF 31FD 1
1801641: FLASH_READ_A
ADDR DATA ?
-----------
0000 0070 0
0001 2F00 0
0002 0182 0
0003 3FED 0
0004 018B 0
0005 3FEE 1
0006 019A 0
0007 2F80 1
0008 019B 0
0009 2F1C 0
000A 0183 0
000B 1FFE 0
000C 2AFF 0
000D 1054 1
000E 3FED 0
000F 0B81 1
0010 1F91 1
0011 0F05 0
0012 0B80 1
0013 1AD0 0
0014 3013 0
0015 1F90 1
0016 0063 1
0017 3016 1
0018 1180 0
0019 1016 1
001A 1D90 1
001B 18D0 1
001C 101B 1
001D 2F01 1
001E 1950 1
001F 2FFF 0
0020 0C01 1
0021 018B 0
0022 0B81 0
0023 1AD0 0
0024 1023 0
0025 1B50 1
0026 304F 1
0027 2F04 1
0028 0188 1
0029 18D0 0
002A 1029 0
002B 2F02 1
002C 0182 1
002D 1304 0
002E 1305 0
002F 2F6E 1
0030 0B82 1
0031 2F00 0
0032 0B83 0
0033 0006 0
0034 0B04 0
0035 0007 0
0036 0805 0
0037 1584 0
0038 1685 0
0039 1004 1
003A 1282 1
003B 1083 1
003C 1A40 1
003D 3033 1
003E 1F90 1
003F 1AD0 1
0040 303F 1
0041 1584 1
0042 1685 1
0043 0590 1
0044 18D0 1
0045 1044 0
0046 1950 1
0047 103F 1
0048 1D90 1
0049 1AD0 1
004A 1049 1
004B 18D0 1
004C 304B 1
004D 1B50 1
004E 102B 1
004F 18D0 1
0050 304F 1
0051 1B50 1
0052 1011 1
0053 1053 1
0054 018B 1
0055 1ED1 1
0056 1ED0 0
0057 2F03 1
0058 0BC1 1
0059 2F8A 0
005A 0BC0 0
005B 2F56 0
005C 0063 0
005D 305C 0
005E 11C0 0
005F 305C 1
0060 11C1 1
0061 305C 1
0062 1CD0 1
0063 2F03 1
0064 0BC1 1
0065 2F8A 0
0066 0BC0 0
0067 2F56 0
0068 0063 0
0069 3068 0
006A 11C0 0
006B 3068 1
006C 11C1 1
006D 3068 1
006E 3056 1
006F 3FFF 1
1890615: FLASH_READ_A
No data (dummy read)
1935310: FLASH_READ_B
No data (dummy read)
2004366: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
0000 0070 2F00 0182 3FED
0004 018B 3FEE 019A 2F80
0008 019B 2F1C 0183 3FFE
000C 2AFF 3054 3FED 0B81
0010 1F91 2F05 0B80 1AD0
0014 3013 1F90 0063 3016
0018 1180 3016 1D90 18D0
001C 301B 2F01 1950 2FFF
0020 0C01 018B 0B81 1AD0
0024 3023 1B50 304F 2F04
0028 0188 18D0 3029 2F02
002C 0182 1304 1305 2F6E
0030 0B82 2F00 0B83 0006
0034 0B04 0007 0805 1584
0038 1685 1004 1282 1083
003C 1A40 3033 1F90 1AD0
0040 303F 1584 1685 0590
0044 18D0 3044 1950 303F
0048 1D90 1AD0 3049 18D0
004C 304B 1B50 302B 18D0
0050 304F 1B50 3011 3053
0054 018B 1ED1 1ED0 2F03
0058 0BC1 2F8A 0BC0 2F56
005C 0063 305C 11C0 305C
0060 11C1 305C 1CD0 2F03
0064 0BC1 2F8A 0BC0 2F56
0068 0063 3068 11C0 3068
006C 11C1 3068 3056 3FFF
2110976: 0000001101001010001110011010010100011100
2333060: 0000001101001010001110011010010100011100
2584511: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0004 0004 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 0282 31FD
2634228: FLASH_READ_B
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 3FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 3FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0004 0
07F1 0004 1
07F2 3FFF 0
07F3 1FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 1FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
2699086: FLASH_READ_B
No data (dummy read)
2743782: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0004 0004 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 0282 31FD
There seems to be two Flash read commands and two Flash write commands - why? I have absolutely no idea.
1010010110100101101001011010011100011010101000010: FLASH write A
1010010110100101101001011010011100001010101000010: FLASH write B
1010010110100101101001011010011000011010101000010: FLASH read A
1010010110100101101001011010011000001010101000010: FLASH read B
55103: FLASH_READ_A
ADDR DATA ?
-----------
07EF 1FFE 0
07F0 0003 0
07F1 0003 1
92201: 1010010110100101101001011010001100011010101000010 0000
158597: 1010010110100101101001011010011001111010101000010
737022: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 0004 3FFF 3FFF 3FFF
820818: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 3FFF 0004 3FFF 3FFF
949230: FLASH_READ_B
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 3FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 3FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0004 0
07F1 0004 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1FFF 1
07F9 3FFF 1
07FA 1FFF 1
07FB 3FFF 1
07FC 1FFF 1
07FD 3FFF 1
07FE 1FFF 1
07FF 3FFF 1
EDIT2: I don't know how to use the ZEROPLUS tool, so I don't really know how to see the VPP voltages.
Then, it does two writes:Code: [Select]737022: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 0004 3FFF 3FFF 3FFF
820818: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 3FFF 0004 3FFF 3FFF
My point was that before the mysterious commands, 07F0 held 0003 and 07F1 held 0003. After them, they seem to held FFFF, which are subsequently changed into 0004 by those two writes.Then, it does two writes:Code: [Select]737022: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 0004 3FFF 3FFF 3FFF
820818: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 3FFF 0004 3FFF 3FFF
This looks pretty normal. To understand this you must know how a OTP / flash write is usually working.
Blank IC / After Erase => all memory cells are holding a '1' bit value
Programing = change some of the '1' bits to '0' bits. You only can change '1' to '0' not the other way around. If you want to write something new you must erase the chip first (is possible) which makes *ALL* memory cells to a '1'.
So
- writing '11111111' somewhere does in reality: NOTHING (all stays same, you can do this as many times as you want)
- writing '0' somewhere changes this bit to '0'. If you later write a '1' it will do NOTHING (the 0 will stay).
==> Since the IC seems to require to write 4 WORDS at once a simple solution just to write 1 WORD or even only some bits from it is to write the unused WORDS with all '1'.
- writing "ABCD 3FFF 3FFF 3FFF" only will change the first word
- writing "3FFF EFGH 3FFF 3FFF" only will change the second word
==> It looks like WRITER just wants to write 2 WORDS in 2 single operations.
JS
EDIT2: I don't know how to use the ZEROPLUS tool, so I don't really know how to see the VPP voltages.
I grouped the 2 channels into a bus each (VDD_AN and PA5_ICVPP_AN, bottom of Zero Plus) which decodes to decimal values (right click on the hex values and select "Numeric Base->Decimal").
In case you want to do it manually:
C0...C7 = 8 bit of analog value VDD_AN (in 100mV, ==> 30 decimal = 3.0V, 45 decimal = 4.5V, ...)
D0...D7 = 8 bit of analog value PA5_ICVPP_AN
example line from text export:
PA0_UNUSED | Bus1 *VDD*SCLK*DATA PA4 PA5 PA7 GND | VDD_AN *C0...*C7 | PA5_ICVPP_AN *D0...*D7
91330 0 | Data=0X1F 1 0 0 0 1 0 0 | 0X2B 11010100 | 0X38 00011100
VDD_AN = 11010100 = 0x2B = 43 ==> 4.3V
PA5_ICVPP_AN = 00011100 = 0x38 = 56 ==> 5.6V
:)
JS
My point was that before the mysterious commands, 07F0 held 0003 and 07F1 held 0003. After them, they seem to held FFFF, which are subsequently changed into 0004 by those two writes.
However, you can see on 949230: FLASH_READ_B, that 07ED holds 0281. This means that "66" followed by four 0 bits, or "31" doesn't actually wipe all the flash, but if it actually actually wipes anything, it only clears a few bytes.
My point was that before the mysterious commands, 07F0 held 0003 and 07F1 held 0003. After them, they seem to held FFFF, which are subsequently changed into 0004 by those two writes.
However, you can see on 949230: FLASH_READ_B, that 07ED holds 0281. This means that "66" followed by four 0 bits, or "31" doesn't actually wipe all the flash, but if it actually actually wipes anything, it only clears a few bytes.
BTW: This 0x1FFF read backs are for sure not correct. I know for sure that 0x3FFF is at most places there (in a previous posting I used LDSPTL/LDSPTH and soft SPI to read back the content of a real IC).I am not sure, but it could be possible that data from writer to IC is sampled on the rising edge, but on the falling edge for the IC? maybe that's why I'm getting those weird, useless trailing bits and why they are sometimes read as 1FFF instead of 3FFF.
I think those values (0x7ED, 0x7EE) might be FIXED for IC identification??. So they just can not get erased.That actually makes sense.
804582: FLASH_READ_A_N2
ADDR DATA ?
-----------
0000 0060 0
0001 1F00 0
0002 0300 0
0003 3FFA 0
0004 0306 0
0005 3FFC 1
0006 0330 0
0007 1F80 1
0008 03B2 0
0009 0E38 0
000A 0302 0
000B 3FFC 0
000C 07FF 0
000D 20E0 1
000E 3FD8 0
000F 1783 1
0010 1F23 1
0011 1E0B 0
0012 1781 1
0013 3C80 0
0014 2023 0
0015 1F01 1
0016 00C3 1
0017 300C 1
0018 0180 0
0019 2037 1
001A 1F90 1
001B 11D0 1
001C 301B 1
001D 2E03 1
001E 19C0 1
001F 2FFE 0
0020 0C03 1
0021 038F 0
0022 0381 0
0023 13F0 0
0024 3022 0
0025 3FC0 1
0026 300F 1
0027 2F0D 1
0028 0118 1
0029 3890 0
002A 303B 0
002B 2E00 1
002C 0386 1
002D 360C 0
002E 230C 0
002F 1EDF 1
0030 1785 1
0031 1F00 0
0032 1F06 0
0033 000C 0
0034 1708 0
0035 000E 0
0036 100A 0
0037 2B08 0
0038 2D0A 0
0039 2000 1
003A 2405 1
003B 2103 1
003C 3481 1
003D 2027 1
003E 3F21 1
003F 3DA1 1
0040 207F 1
0041 3B0D 1
0042 250B 1
0043 0B21 1
0044 38A1 1
0045 2008 0
0046 3231 1
0047 203F 1
0048 3921 1
0049 3C81 1
004A 2001 1
004B 31E1 1
004C 2007 1
004D 3F81 1
004E 2047 1
004F 3881 1
0050 201F 1
0051 3F81 1
0052 2023 1
0053 20B7 1
0054 0197 1
0055 1FE3 1
0056 1EC0 0
0057 3E03 1
0058 0F83 1
0059 2F82 0
005A 03C0 0
005B 2E16 0
005C 0063 0
005D 301C 0
005E 03C0 0
005F 30D8 1
0060 11C3 1
0061 30D8 1
0062 3C90 1
0063 2F03 1
0064 1BC3 1
0065 2F8E 0
0066 0FC0 0
0067 2E76 0
0068 0062 0
0069 3078 0
006A 2380 0
006B 30F8 1
006C 2381 1
006D 30F9 1
006E 303F 1
006F 3FFF 1
0070 3FFF 1
0071 3FFF 1
0072 3FFF 1
0073 3FFF 1
0074 3FFF 1
0075 3FFF 1
0076 3FFF 1
0077 3FFF 1
0078 3FFF 1
0079 3FFF 1
007A 3FFF 1
007B 3FFF 1
007C 3FFF 1
007D 3FFF 1
007E 3FFF 1
007F 3FFF 1
0080 3FFF 1
0081 3FFF 1
0082 3FFF 1
0083 3FFF 1
0084 3FFF 1
0085 3FFF 1
0086 3FFF 1
0087 3FFF 1
0088 3FFF 1
0089 3FFF 1
008A 3FFF 1
008B 3FFF 1
008C 3FFF 1
008D 3FFF 1
008E 3FFF 1
008F 3FFF 1
0090 3FFF 1
0091 3FFF 1
0092 3FFF 1
0093 3FFF 1
0094 3FFF 1
0095 3FFF 1
0096 3FFF 1
0097 3FFF 1
0098 3FFF 1
0099 3FFF 1
009A 3FFF 1
009B 3FFF 1
009C 3FFF 1
009D 3FFF 1
009E 3FFF 1
009F 3FFF 1
00A0 3FFF 1
00A1 3FFF 1
00A2 3FFF 1
00A3 3FFF 1
00A4 3FFF 1
00A5 3FFF 1
00A6 3FFF 1
00A7 3FFF 1
00A8 3FFF 1
00A9 3FFF 1
00AA 3FFF 1
00AB 3FFF 1
00AC 3FFF 1
00AD 3FFF 1
00AE 3FFF 1
00AF 3FFF 1
00B0 3FFF 1
00B1 3FFF 1
00B2 3FFF 1
00B3 3FFF 1
00B4 3FFF 1
00B5 3FFF 1
00B6 3FFF 1
00B7 3FFF 1
00B8 3FFF 1
00B9 3FFF 1
00BA 3FFF 1
00BB 3FFF 1
00BC 3FFF 1
00BD 3FFF 1
00BE 3FFF 1
00BF 3FFF 1
00C0 3FFF 1
00C1 3FFF 1
00C2 3FFF 1
00C3 3FFF 1
00C4 3FFF 1
00C5 3FFF 1
00C6 3FFF 1
00C7 3FFF 1
00C8 3FFF 1
00C9 3FFF 1
00CA 3FFF 1
00CB 3FFF 1
00CC 3FFF 1
00CD 3FFF 1
00CE 3FFF 1
00CF 3FFF 1
00D0 3FFF 1
00D1 3FFF 1
00D2 3FFF 1
00D3 3FFF 1
00D4 3FFF 1
00D5 3FFF 1
00D6 3FFF 1
00D7 3FFF 1
00D8 3FFF 1
00D9 3FFF 1
00DA 3FFF 1
00DB 3FFF 1
00DC 3FFF 1
00DD 3FFF 1
00DE 3FFF 1
00DF 3FFF 1
00E0 3FFF 1
00E1 3FFF 1
00E2 3FFF 1
00E3 3FFF 1
00E4 3FFF 1
00E5 3FFF 1
00E6 3FFF 1
00E7 3FFF 1
00E8 3FFF 1
00E9 3FFF 1
00EA 3FFF 1
00EB 3FFF 1
00EC 3FFF 1
00ED 3FFF 1
00EE 3FFF 1
00EF 3FFF 1
00F0 3FFF 1
00F1 3FFF 1
00F2 3FFF 1
00F3 3FFF 1
00F4 3FFF 1
00F5 3FFF 1
00F6 3FFF 1
00F7 3FFF 1
00F8 3FFF 1
00F9 3FFF 1
00FA 3FFF 1
00FB 3FFF 1
00FC 3FFF 1
00FD 3FFF 1
00FE 3FFF 1
00FF 3FFF 1
0100 3FFF 1
0101 3FFF 1
0102 3FFF 1
0103 3FFF 1
0104 3FFF 1
0105 3FFF 1
0106 3FFF 1
0107 3FFF 1
0108 3FFF 1
0109 3FFF 1
010A 3FFF 1
010B 3FFF 1
010C 3FFF 1
010D 3FFF 1
010E 3FFF 1
010F 3FFF 1
0110 3FFF 1
0111 3FFF 1
0112 3FFF 1
0113 3FFF 1
0114 3FFF 1
0115 3FFF 1
0116 3FFF 1
0117 3FFF 1
0118 3FFF 1
0119 3FFF 1
011A 3FFF 1
011B 3FFF 1
011C 3FFF 1
011D 3FFF 1
011E 3FFF 1
011F 3FFF 1
0120 3FFF 1
0121 3FFF 1
0122 3FFF 1
0123 3FFF 1
0124 3FFF 1
0125 3FFF 1
0126 3FFF 1
0127 3FFF 1
0128 3FFF 1
0129 3FFF 1
012A 3FFF 1
012B 3FFF 1
012C 3FFF 1
012D 3FFF 1
012E 3FFF 1
012F 3FFF 1
0130 3FFF 1
0131 3FFF 1
0132 3FFF 1
0133 3FFF 1
0134 3FFF 1
0135 3FFF 1
0136 3FFF 1
0137 3FFF 1
0138 3FFF 1
0139 3FFF 1
013A 3FFF 1
013B 3FFF 1
013C 3FFF 1
013D 3FFF 1
013E 3FFF 1
013F 3FFF 1
0140 3FFF 1
0141 3FFF 1
0142 3FFF 1
0143 3FFF 1
0144 3FFF 1
0145 3FFF 1
0146 3FFF 1
0147 3FFF 1
0148 3FFF 1
0149 3FFF 1
014A 3FFF 1
014B 3FFF 1
014C 3FFF 1
014D 3FFF 1
014E 3FFF 1
014F 3FFF 1
0150 3FFF 1
0151 3FFF 1
0152 3FFF 1
0153 3FFF 1
0154 3FFF 1
0155 3FFF 1
0156 3FFF 1
0157 3FFF 1
0158 3FFF 1
0159 3FFF 1
015A 3FFF 1
015B 3FFF 1
015C 3FFF 1
015D 3FFF 1
015E 3FFF 1
015F 3FFF 1
0160 3FFF 1
0161 3FFF 1
0162 3FFF 1
0163 3FFF 1
0164 3FFF 1
0165 3FFF 1
0166 3FFF 1
0167 3FFF 1
0168 3FFF 1
0169 3FFF 1
016A 3FFF 1
016B 3FFF 1
016C 3FFF 1
016D 3FFF 1
016E 3FFF 1
016F 3FFF 1
0170 3FFF 1
0171 3FFF 1
0172 3FFF 1
0173 3FFF 1
0174 3FFF 1
0175 3FFF 1
0176 3FFF 1
0177 3FFF 1
0178 3FFF 1
0179 3FFF 1
017A 3FFF 1
017B 3FFF 1
017C 3FFF 1
017D 3FFF 1
017E 3FFF 1
017F 3FFF 1
0180 3FFF 1
0181 3FFF 1
0182 3FFF 1
0183 3FFF 1
0184 3FFF 1
0185 3FFF 1
0186 3FFF 1
0187 3FFF 1
0188 3FFF 1
0189 3FFF 1
018A 3FFF 1
018B 3FFF 1
018C 3FFF 1
018D 3FFF 1
018E 3FFF 1
018F 3FFF 1
0190 3FFF 1
0191 3FFF 1
0192 3FFF 1
0193 3FFF 1
0194 3FFF 1
0195 3FFF 1
0196 3FFF 1
0197 3FFF 1
0198 3FFF 1
0199 3FFF 1
019A 3FFF 1
019B 3FFF 1
019C 3FFF 1
019D 3FFF 1
019E 3FFF 1
019F 3FFF 1
01A0 3FFF 1
01A1 3FFF 1
01A2 3FFF 1
01A3 3FFF 1
01A4 3FFF 1
01A5 3FFF 1
01A6 3FFF 1
01A7 3FFF 1
01A8 3FFF 1
01A9 3FFF 1
01AA 3FFF 1
01AB 3FFF 1
01AC 3FFF 1
01AD 3FFF 1
01AE 3FFF 1
01AF 3FFF 1
01B0 3FFF 1
01B1 3FFF 1
01B2 3FFF 1
01B3 3FFF 1
01B4 3FFF 1
01B5 3FFF 1
01B6 3FFF 1
01B7 3FFF 1
01B8 3FFF 1
01B9 3FFF 1
01BA 3FFF 1
01BB 3FFF 1
01BC 3FFF 1
01BD 3FFF 1
01BE 3FFF 1
01BF 3FFF 1
01C0 3FFF 1
01C1 3FFF 1
01C2 3FFF 1
01C3 3FFF 1
01C4 3FFF 1
01C5 3FFF 1
01C6 3FFF 1
01C7 3FFF 1
01C8 3FFF 1
01C9 3FFF 1
01CA 3FFF 1
01CB 3FFF 1
01CC 3FFF 1
01CD 3FFF 1
01CE 3FFF 1
01CF 3FFF 1
01D0 3FFF 1
01D1 3FFF 1
01D2 3FFF 1
01D3 3FFF 1
01D4 3FFF 1
01D5 3FFF 1
01D6 3FFF 1
01D7 3FFF 1
01D8 3FFF 1
01D9 3FFF 1
01DA 3FFF 1
01DB 3FFF 1
01DC 3FFF 1
01DD 3FFF 1
01DE 3FFF 1
01DF 3FFF 1
01E0 3FFF 1
01E1 3FFF 1
01E2 3FFF 1
01E3 3FFF 1
01E4 3FFF 1
01E5 3FFF 1
01E6 3FFF 1
01E7 3FFF 1
01E8 3FFF 1
01E9 3FFF 1
01EA 3FFF 1
01EB 3FFF 1
01EC 3FFF 1
01ED 3FFF 1
01EE 3FFF 1
01EF 3FFF 1
01F0 3FFF 1
01F1 3FFF 1
01F2 3FFF 1
01F3 3FFF 1
01F4 3FFF 1
01F5 3FFF 1
01F6 3FFF 1
01F7 3FFF 1
01F8 3FFF 1
01F9 3FFF 1
01FA 3FFF 1
01FB 3FFF 1
01FC 3FFF 1
01FD 3FFF 1
01FE 3FFF 1
01FF 3FFF 1
0200 3FFF 1
0201 3FFF 1
0202 3FFF 1
0203 3FFF 1
0204 3FFF 1
0205 3FFF 1
0206 3FFF 1
0207 3FFF 1
0208 3FFF 1
0209 3FFF 1
020A 3FFF 1
020B 3FFF 1
020C 3FFF 1
020D 3FFF 1
020E 3FFF 1
020F 3FFF 1
0210 3FFF 1
0211 3FFF 1
0212 3FFF 1
0213 3FFF 1
0214 3FFF 1
0215 3FFF 1
0216 3FFF 1
0217 3FFF 1
0218 3FFF 1
0219 3FFF 1
021A 3FFF 1
021B 3FFF 1
021C 3FFF 1
021D 3FFF 1
021E 3FFF 1
021F 3FFF 1
0220 3FFF 1
0221 3FFF 1
0222 3FFF 1
0223 3FFF 1
0224 3FFF 1
0225 3FFF 1
0226 3FFF 1
0227 3FFF 1
0228 3FFF 1
0229 3FFF 1
022A 3FFF 1
022B 3FFF 1
022C 3FFF 1
022D 3FFF 1
022E 3FFF 1
022F 3FFF 1
0230 3FFF 1
0231 3FFF 1
0232 3FFF 1
0233 3FFF 1
0234 3FFF 1
0235 3FFF 1
0236 3FFF 1
0237 3FFF 1
0238 3FFF 1
0239 3FFF 1
023A 3FFF 1
023B 3FFF 1
023C 3FFF 1
023D 3FFF 1
023E 3FFF 1
023F 3FFF 1
0240 3FFF 1
0241 3FFF 1
0242 3FFF 1
0243 3FFF 1
0244 3FFF 1
0245 3FFF 1
0246 3FFF 1
0247 3FFF 1
0248 3FFF 1
0249 3FFF 1
024A 3FFF 1
024B 3FFF 1
024C 3FFF 1
024D 3FFF 1
024E 3FFF 1
024F 3FFF 1
0250 3FFF 1
0251 3FFF 1
0252 3FFF 1
0253 3FFF 1
0254 3FFF 1
0255 3FFF 1
0256 3FFF 1
0257 3FFF 1
0258 3FFF 1
0259 3FFF 1
025A 3FFF 1
025B 3FFF 1
025C 3FFF 1
025D 3FFF 1
025E 3FFF 1
025F 3FFF 1
0260 3FFF 1
0261 3FFF 1
0262 3FFF 1
0263 3FFF 1
0264 3FFF 1
0265 3FFF 1
0266 3FFF 1
0267 3FFF 1
0268 3FFF 1
0269 3FFF 1
026A 3FFF 1
026B 3FFF 1
026C 3FFF 1
026D 3FFF 1
026E 3FFF 1
026F 3FFF 1
0270 3FFF 1
0271 3FFF 1
0272 3FFF 1
0273 3FFF 1
0274 3FFF 1
0275 3FFF 1
0276 3FFF 1
0277 3FFF 1
0278 3FFF 1
0279 3FFF 1
027A 3FFF 1
027B 3FFF 1
027C 3FFF 1
027D 3FFF 1
027E 3FFF 1
027F 3FFF 1
0280 3FFF 1
0281 3FFF 1
0282 3FFF 1
0283 3FFF 1
0284 3FFF 1
0285 3FFF 1
0286 3FFF 1
0287 3FFF 1
0288 3FFF 1
0289 3FFF 1
028A 3FFF 1
028B 3FFF 1
028C 3FFF 1
028D 3FFF 1
028E 3FFF 1
028F 3FFF 1
0290 3FFF 1
0291 3FFF 1
0292 3FFF 1
0293 3FFF 1
0294 3FFF 1
0295 3FFF 1
0296 3FFF 1
0297 3FFF 1
0298 3FFF 1
0299 3FFF 1
029A 3FFF 1
029B 3FFF 1
029C 3FFF 1
029D 3FFF 1
029E 3FFF 1
029F 3FFF 1
02A0 3FFF 1
02A1 3FFF 1
02A2 3FFF 1
02A3 3FFF 1
02A4 3FFF 1
02A5 3FFF 1
02A6 3FFF 1
02A7 3FFF 1
02A8 3FFF 1
02A9 3FFF 1
02AA 3FFF 1
02AB 3FFF 1
02AC 3FFF 1
02AD 3FFF 1
02AE 3FFF 1
02AF 3FFF 1
02B0 3FFF 1
02B1 3FFF 1
02B2 3FFF 1
02B3 3FFF 1
02B4 3FFF 1
02B5 3FFF 1
02B6 3FFF 1
02B7 3FFF 1
02B8 3FFF 1
02B9 3FFF 1
02BA 3FFF 1
02BB 3FFF 1
02BC 3FFF 1
02BD 3FFF 1
02BE 3FFF 1
02BF 3FFF 1
02C0 3FFF 1
02C1 3FFF 1
02C2 3FFF 1
02C3 3FFF 1
02C4 3FFF 1
02C5 3FFF 1
02C6 3FFF 1
02C7 3FFF 1
02C8 3FFF 1
02C9 3FFF 1
02CA 3FFF 1
02CB 3FFF 1
02CC 3FFF 1
02CD 3FFF 1
02CE 3FFF 1
02CF 3FFF 1
02D0 3FFF 1
02D1 3FFF 1
02D2 3FFF 1
02D3 3FFF 1
02D4 3FFF 1
02D5 3FFF 1
02D6 3FFF 1
02D7 3FFF 1
02D8 3FFF 1
02D9 3FFF 1
02DA 3FFF 1
02DB 3FFF 1
02DC 3FFF 1
02DD 3FFF 1
02DE 3FFF 1
02DF 3FFF 1
02E0 3FFF 1
02E1 3FFF 1
02E2 3FFF 1
02E3 3FFF 1
02E4 3FFF 1
02E5 3FFF 1
02E6 3FFF 1
02E7 3FFF 1
02E8 3FFF 1
02E9 3FFF 1
02EA 3FFF 1
02EB 3FFF 1
02EC 3FFF 1
02ED 3FFF 1
02EE 3FFF 1
02EF 3FFF 1
02F0 3FFF 1
02F1 3FFF 1
02F2 3FFF 1
02F3 3FFF 1
02F4 3FFF 1
02F5 3FFF 1
02F6 3FFF 1
02F7 3FFF 1
02F8 3FFF 1
02F9 3FFF 1
02FA 3FFF 1
02FB 3FFF 1
02FC 3FFF 1
02FD 3FFF 1
02FE 3FFF 1
02FF 3FFF 1
0300 3FFF 1
0301 3FFF 1
0302 3FFF 1
0303 3FFF 1
0304 3FFF 1
0305 3FFF 1
0306 3FFF 1
0307 3FFF 1
0308 3FFF 1
0309 3FFF 1
030A 3FFF 1
030B 3FFF 1
030C 3FFF 1
030D 3FFF 1
030E 3FFF 1
030F 3FFF 1
0310 3FFF 1
0311 3FFF 1
0312 3FFF 1
0313 3FFF 1
0314 3FFF 1
0315 3FFF 1
0316 3FFF 1
0317 3FFF 1
0318 3FFF 1
0319 3FFF 1
031A 3FFF 1
031B 3FFF 1
031C 3FFF 1
031D 3FFF 1
031E 3FFF 1
031F 3FFF 1
0320 3FFF 1
0321 3FFF 1
0322 3FFF 1
0323 3FFF 1
0324 3FFF 1
0325 3FFF 1
0326 3FFF 1
0327 3FFF 1
0328 3FFF 1
0329 3FFF 1
032A 3FFF 1
032B 3FFF 1
032C 3FFF 1
032D 3FFF 1
032E 3FFF 1
032F 3FFF 1
0330 3FFF 1
0331 3FFF 1
0332 3FFF 1
0333 3FFF 1
0334 3FFF 1
0335 3FFF 1
0336 3FFF 1
pin | signal |
5 | VDD |
6 | PA7 |
7 | PA6 |
8 | PA5 |
33 | PA3 |
34 | PA4 |
35 | PA0 |
36 | GND |
.writer package 14, 4, 32, 8, 9, 7, 6, 32, 11, 0x0000, 0x0000, 1
So apparently yes, the data from writer to IC gets sampled on rising edge, but from IC to writer gets sampled on the falling edge.
If we parse "Verify" on the falling edge we get:Code: [Select]804582: FLASH_READ_A_N2
ADDR DATA ?
-----------
0000 0060 0
0001 1F00 0
0002 0300 0
...
The unknown bit is thus probably just garbage from switching from input to output.
PS: how were the nice chip diagrams at https://free-pdk.github.io drawn? I used KiCad for my diagram and copied it to Gimp and then edited it there, but I guess there is some software out there which makes it easier?
{
Name : 'PFS154-S16/D16',
Package: '2SIDED' ,
Pins : 16 ,
PRC : { Vcc:5, Gnd:12, Reset: 8, XTAL1: 6, XTAL2:7 },
PWM : [1,2,3,4,8,9,10,11,15,16],
PA : [11,0,0,9,10,8,7,6],
PB : [13,14,15,16,1,2,3,4],
Analog : [],
Peripherals: { }
}
So apparently yes, the data from writer to IC gets sampled on rising edge, but from IC to writer gets sampled on the falling edge.
If we parse "Verify" on the falling edge we get:Code: [Select]804582: FLASH_READ_A_N2
ADDR DATA ?
-----------
0000 0060 0
0001 1F00 0
0002 0300 0
...
The unknown bit is thus probably just garbage from switching from input to output.
Unfortunately this does not seem right as well. "Verify" should read back the same content as in SimpleBlink PDK starting with "0070 ...".
I made a new capture of "Verify" using higher sampling frequency (5MHz). Maybe this will solve the "read" instability.
To increase buffer size I removed the analog voltage capture.
JS
2527: FLASH_READ_A
No data (dummy read)
67967: FLASH_READ_A
No data (dummy read)
179611: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0027 0
07F1 0025 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F74 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
316754: FLASH_READ_A
No data (dummy read)
1711828: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0681 1
07EE 027E 1
07EF 1FFE 0
07F0 0065 0
07F1 0025 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F74 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
1848671: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027E 1
07EF 3FFE 0
07F0 006D 0
07F1 006D 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
1985807: FLASH_READ_A
ADDR DATA ?
-----------
0000 0070 0
0001 2F00 0
0002 0182 0
0003 3FED 0
0004 018B 0
0005 3FEE 1
0006 019E 0
0007 2F81 1
0008 019B 0
0009 2F1C 0
000A 0183 0
000B 3FFE 0
000C 2BFF 0
000D 30D4 1
000E 3FED 0
000F 0B81 1
0010 1F91 1
0011 2F05 0
0012 0B80 1
0013 1AD0 0
0014 3013 0
0015 1F90 1
0016 0063 1
0017 3016 1
0018 1180 0
0019 3016 1
001A 3D90 1
001B 18D0 1
001C 301B 1
001D 2F01 1
001E 1950 1
001F 2FFF 0
0020 1C01 1
0021 018B 0
0022 0B83 0
0023 3AD0 0
0024 3023 0
0025 1B50 1
0026 304F 1
0027 2F04 1
0028 0188 1
0029 18D0 0
002A 3029 0
002B 2F02 1
002C 0182 1
002D 1304 0
002E 1305 0
002F 2F6E 1
0030 0B82 1
0031 2F00 0
0032 0B83 0
0033 0006 0
0034 0B04 0
0035 0007 0
0036 0805 0
0037 1584 0
0038 1685 0
0039 1004 1
003A 1282 1
003B 3083 1
003C 1A40 1
003D 3077 1
003E 1FB0 1
003F 1ED1 1
0040 303F 1
0041 1D84 1
0042 1685 1
0043 0591 1
0044 18D0 1
0045 3044 0
0046 1950 1
0047 303F 1
0048 1D90 1
0049 1BF0 1
004A 3049 1
004B 18D0 1
004C 304B 1
004D 1B50 1
004E 302B 1
004F 18D0 1
0050 304F 1
0051 1B50 1
0052 3011 1
0053 3053 1
0054 018B 1
0055 1ED1 1
0056 1ED0 0
0057 2F07 1
0058 0BC1 1
0059 2F8A 0
005A 1BC0 0
005B 2FD6 0
005C 0063 0
005D 30DC 0
005E 11C0 0
005F 305C 1
0060 11C1 1
0061 305C 1
0062 1CD0 1
0063 2F03 1
0064 0BC1 1
0065 2F8E 0
0066 0BC0 0
0067 2F56 0
0068 0063 0
0069 3068 0
006A 11C0 0
006B 3068 1
006C 31C1 1
006D 3068 1
006E 3056 1
006F 3FFF 1
0070 3FFF 1
0071 3FFF 1
0072 3FFF 1
0073 3FFF 1
0074 3FFF 1
0075 3FFF 1
0076 3FFF 1
0077 3FFF 1
0078 3FFF 1
0079 3FFF 1
007A 3FFF 1
007B 3FFF 1
007C 3FFF 1
007D 3FFF 1
007E 3FFF 1
007F 3FFF 1
0080 3FFF 1
0081 3FFF 1
0082 3FFF 1
0083 3FFF 1
0084 3FFF 1
0085 3FFF 1
0086 3FFF 1
0087 3FFF 1
0088 3FFF 1
0089 3FFF 1
008A 3FFF 1
008B 3FFF 1
008C 3FFF 1
008D 3FFF 1
008E 3FFF 1
008F 3FFF 1
0090 3FFF 1
0091 3FFF 1
0092 3FFF 1
0093 3FFF 1
0094 3FFF 1
0095 3FFF 1
0096 3FFF 1
0097 3FFF 1
0098 3FFF 1
0099 3FFF 1
009A 3FFF 1
009B 3FFF 1
009C 3FFF 1
009D 3FFF 1
009E 3FFF 1
009F 3FFF 1
00A0 3FFF 1
00A1 3FFF 1
00A2 3FFF 1
00A3 3FFF 1
00A4 3FFF 1
00A5 3FFF 1
00A6 3FFF 1
00A7 3FFF 1
00A8 3FFF 1
00A9 3FFF 1
00AA 3FFF 1
00AB 3FFF 1
00AC 3FFF 1
00AD 3FFF 1
00AE 3FFF 1
00AF 3FFF 1
00B0 3FFF 1
00B1 3FFF 1
00B2 3FFF 1
00B3 3FFF 1
00B4 3FFF 1
00B5 3FFF 1
00B6 3FFF 1
00B7 3FFF 1
00B8 3FFF 1
00B9 3FFF 1
00BA 3FFF 1
00BB 3FFF 1
00BC 3FFF 1
00BD 3FFF 1
00BE 3FFF 1
00BF 3FFF 1
00C0 3FFF 1
00C1 3FFF 1
00C2 3FFF 1
00C3 3FFF 1
00C4 3FFF 1
00C5 3FFF 1
00C6 3FFF 1
00C7 3FFF 1
00C8 3FFF 1
00C9 3FFF 1
00CA 3FFF 1
00CB 3FFF 1
00CC 3FFF 1
00CD 3FFF 1
00CE 3FFF 1
00CF 3FFF 1
00D0 3FFF 1
00D1 3FFF 1
00D2 3FFF 1
00D3 3FFF 1
00D4 3FFF 1
00D5 3FFF 1
00D6 3FFF 1
00D7 3FFF 1
00D8 3FFF 1
00D9 3FFF 1
00DA 3FFF 1
00DB 3FFF 1
00DC 3FFF 1
00DD 3FFF 1
00DE 3FFF 1
00DF 3FFF 1
00E0 3FFF 1
00E1 3FFF 1
00E2 3FFF 1
00E3 3FFF 1
00E4 3FFF 1
00E5 3FFF 1
00E6 3FFF 1
00E7 3FFF 1
00E8 3FFF 1
00E9 3FFF 1
00EA 3FFF 1
00EB 3FFF 1
00EC 3FFF 1
00ED 3FFF 1
00EE 3FFF 1
00EF 3FFF 1
00F0 3FFF 1
00F1 3FFF 1
00F2 3FFF 1
00F3 3FFF 1
00F4 3FFF 1
00F5 3FFF 1
00F6 3FFF 1
00F7 3FFF 1
00F8 3FFF 1
00F9 3FFF 1
00FA 3FFF 1
00FB 3FFF 1
00FC 3FFF 1
00FD 3FFF 1
00FE 3FFF 1
00FF 3FFF 1
0100 3FFF 1
0101 3FFF 1
0102 3FFF 1
0103 3FFF 1
0104 3FFF 1
0105 3FFF 1
0106 3FFF 1
0107 3FFF 1
0108 3FFF 1
0109 3FFF 1
010A 3FFF 1
010B 3FFF 1
010C 3FFF 1
010D 3FFF 1
010E 3FFF 1
010F 3FFF 1
0110 3FFF 1
0111 3FFF 1
0112 3FFF 1
0113 3FFF 1
0114 3FFF 1
0115 3FFF 1
0116 3FFF 1
0117 3FFF 1
0118 3FFF 1
0119 3FFF 1
011A 3FFF 1
011B 3FFF 1
011C 3FFF 1
011D 3FFF 1
011E 3FFF 1
011F 3FFF 1
0120 3FFF 1
0121 3FFF 1
0122 3FFF 1
0123 3FFF 1
0124 3FFF 1
0125 3FFF 1
0126 3FFF 1
0127 3FFF 1
0128 3FFF 1
0129 3FFF 1
012A 3FFF 1
012B 3FFF 1
012C 3FFF 1
012D 3FFF 1
012E 3FFF 1
012F 3FFF 1
0130 3FFF 1
0131 3FFF 1
0132 3FFF 1
0133 3FFF 1
0134 3FFF 1
0135 3FFF 1
0136 3FFF 1
0137 3FFF 1
0138 3FFF 1
0139 3FFF 1
013A 3FFF 1
013B 3FFF 1
013C 3FFF 1
013D 3FFF 1
013E 3FFF 1
013F 3FFF 1
0140 3FFF 1
0141 3FFF 1
0142 3FFF 1
0143 3FFF 1
0144 3FFF 1
0145 3FFF 1
0146 3FFF 1
0147 3FFF 1
0148 3FFF 1
0149 3FFF 1
014A 3FFF 1
014B 3FFF 1
014C 3FFF 1
014D 3FFF 1
014E 3FFF 1
014F 3FFF 1
0150 3FFF 1
0151 3FFF 1
0152 3FFF 1
0153 3FFF 1
0154 3FFF 1
0155 3FFF 1
0156 3FFF 1
0157 3FFF 1
0158 3FFF 1
0159 3FFF 1
015A 3FFF 1
015B 3FFF 1
015C 3FFF 1
015D 3FFF 1
015E 3FFF 1
015F 3FFF 1
0160 3FFF 1
0161 3FFF 1
0162 3FFF 1
0163 3FFF 1
0164 3FFF 1
0165 3FFF 1
0166 3FFF 1
0167 3FFF 1
0168 3FFF 1
0169 3FFF 1
016A 3FFF 1
016B 3FFF 1
016C 3FFF 1
016D 3FFF 1
016E 3FFF 1
016F 3FFF 1
0170 3FFF 1
0171 3FFF 1
0172 3FFF 1
0173 3FFF 1
0174 3FFF 1
0175 3FFF 1
0176 3FFF 1
0177 3FFF 1
0178 3FFF 1
0179 3FFF 1
017A 3FFF 1
017B 3FFF 1
017C 3FFF 1
017D 3FFF 1
017E 3FFF 1
017F 3FFF 1
0180 3FFF 1
0181 3FFF 1
0182 3FFF 1
0183 3FFF 1
0184 3FFF 1
0185 3FFF 1
0186 3FFF 1
0187 3FFF 1
0188 3FFF 1
0189 3FFF 1
018A 3FFF 1
018B 3FFF 1
018C 3FFF 1
018D 3FFF 1
018E 3FFF 1
018F 3FFF 1
0190 3FFF 1
0191 3FFF 1
0192 3FFF 1
0193 3FFF 1
0194 3FFF 1
0195 3FFF 1
0196 3FFF 1
0197 3FFF 1
0198 3FFF 1
0199 3FFF 1
019A 3FFF 1
019B 3FFF 1
019C 3FFF 1
019D 3FFF 1
019E 3FFF 1
019F 3FFF 1
01A0 3FFF 1
01A1 3FFF 1
01A2 3FFF 1
01A3 3FFF 1
01A4 3FFF 1
01A5 3FFF 1
01A6 3FFF 1
01A7 3FFF 1
01A8 3FFF 1
01A9 3FFF 1
01AA 3FFF 1
01AB 3FFF 1
01AC 3FFF 1
01AD 3FFF 1
01AE 3FFF 1
01AF 3FFF 1
01B0 3FFF 1
01B1 3FFF 1
01B2 3FFF 1
01B3 3FFF 1
01B4 3FFF 1
01B5 3FFF 1
01B6 3FFF 1
01B7 3FFF 1
01B8 3FFF 1
01B9 3FFF 1
01BA 3FFF 1
01BB 3FFF 1
01BC 3FFF 1
01BD 3FFF 1
01BE 3FFF 1
01BF 3FFF 1
01C0 3FFF 1
01C1 3FFF 1
01C2 3FFF 1
01C3 3FFF 1
01C4 3FFF 1
01C5 3FFF 1
01C6 3FFF 1
01C7 3FFF 1
01C8 3FFF 1
01C9 3FFF 1
01CA 3FFF 1
01CB 3FFF 1
01CC 3FFF 1
01CD 3FFF 1
01CE 3FFF 1
01CF 3FFF 1
01D0 3FFF 1
01D1 3FFF 1
01D2 3FFF 1
01D3 3FFF 1
01D4 3FFF 1
01D5 3FFF 1
01D6 3FFF 1
01D7 3FFF 1
01D8 3FFF 1
01D9 3FFF 1
01DA 3FFF 1
01DB 3FFF 1
01DC 3FFF 1
01DD 3FFF 1
01DE 3FFF 1
01DF 3FFF 1
01E0 3FFF 1
01E1 3FFF 1
01E2 3FFF 1
01E3 3FFF 1
01E4 3FFF 1
01E5 3FFF 1
01E6 3FFF 1
01E7 3FFF 1
01E8 3FFF 1
01E9 3FFF 1
01EA 3FFF 1
01EB 3FFF 1
01EC 3FFF 1
01ED 3FFF 1
01EE 3FFF 1
01EF 3FFF 1
01F0 3FFF 1
01F1 3FFF 1
01F2 3FFF 1
01F3 3FFF 1
01F4 3FFF 1
01F5 3FFF 1
01F6 3FFF 1
01F7 3FFF 1
01F8 3FFF 1
01F9 3FFF 1
01FA 3FFF 1
01FB 3FFF 1
01FC 3FFF 1
01FD 3FFF 1
01FE 3FFF 1
01FF 3FFF 1
0200 3FFF 1
0201 3FFF 1
0202 3FFF 1
0203 3FFF 1
0204 3FFF 1
0205 3FFF 1
0206 3FFF 1
0207 3FFF 1
0208 3FFF 1
0209 3FFF 1
020A 3FFF 1
020B 3FFF 1
020C 3FFF 1
020D 3FFF 1
020E 3FFF 1
020F 3FFF 1
0210 3FFF 1
0211 3FFF 1
0212 3FFF 1
0213 3FFF 1
0214 3FFF 1
0215 3FFF 1
0216 3FFF 1
0217 3FFF 1
0218 3FFF 1
0219 3FFF 1
021A 3FFF 1
021B 3FFF 1
021C 3FFF 1
021D 3FFF 1
021E 3FFF 1
021F 3FFF 1
0220 3FFF 1
0221 3FFF 1
0222 3FFF 1
0223 3FFF 1
0224 3FFF 1
0225 3FFF 1
0226 3FFF 1
0227 3FFF 1
0228 3FFF 1
0229 3FFF 1
022A 3FFF 1
022B 3FFF 1
022C 3FFF 1
022D 3FFF 1
022E 3FFF 1
022F 3FFF 1
0230 3FFF 1
0231 3FFF 1
0232 3FFF 1
0233 3FFF 1
0234 3FFF 1
0235 3FFF 1
0236 3FFF 1
0237 3FFF 1
0238 3FFF 1
0239 3FFF 1
023A 3FFF 1
023B 3FFF 1
023C 3FFF 1
023D 3FFF 1
023E 3FFF 1
023F 3FFF 1
0240 3FFF 1
0241 3FFF 1
0242 3FFF 1
0243 3FFF 1
0244 3FFF 1
0245 3FFF 1
0246 3FFF 1
0247 3FFF 1
0248 3FFF 1
0249 3FFF 1
024A 3FFF 1
024B 3FFF 1
024C 3FFF 1
024D 3FFF 1
024E 3FFF 1
024F 3FFF 1
0250 3FFF 1
0251 3FFF 1
0252 3FFF 1
0253 3FFF 1
0254 3FFF 1
0255 3FFF 1
0256 3FFF 1
0257 3FFF 1
0258 3FFF 1
0259 3FFF 1
025A 3FFF 1
025B 3FFF 1
025C 3FFF 1
025D 3FFF 1
025E 3FFF 1
025F 3FFF 1
0260 3FFF 1
0261 3FFF 1
0262 3FFF 1
0263 3FFF 1
0264 3FFF 1
0265 3FFF 1
0266 3FFF 1
0267 3FFF 1
0268 3FFF 1
0269 3FFF 1
026A 3FFF 1
026B 3FFF 1
026C 3FFF 1
026D 3FFF 1
026E 3FFF 1
026F 3FFF 1
0270 3FFF 1
0271 3FFF 1
0272 3FFF 1
0273 3FFF 1
0274 3FFF 1
0275 3FFF 1
0276 3FFF 1
0277 3FFF 1
0278 3FFF 1
0279 3FFF 1
027A 3FFF 1
027B 3FFF 1
027C 3FFF 1
027D 3FFF 1
027E 3FFF 1
027F 3FFF 1
0280 3FFF 1
0281 3FFF 1
0282 3FFF 1
0283 3FFF 1
0284 3FFF 1
0285 3FFF 1
0286 3FFF 1
0287 3FFF 1
0288 3FFF 1
0289 3FFF 1
028A 3FFF 1
028B 3FFF 1
028C 3FFF 1
028D 3FFF 1
028E 3FFF 1
028F 3FFF 1
0290 3FFF 1
0291 3FFF 1
0292 3FFF 1
0293 3FFF 1
0294 3FFF 1
0295 3FFF 1
0296 3FFF 1
0297 3FFF 1
0298 3FFF 1
0299 3FFF 1
029A 3FFF 1
029B 3FFF 1
029C 3FFF 1
029D 3FFF 1
029E 3FFF 1
029F 3FFF 1
02A0 3FFF 1
02A1 3FFF 1
02A2 3FFF 1
02A3 3FFF 1
02A4 3FFF 1
02A5 3FFF 1
02A6 3FFF 1
02A7 3FFF 1
02A8 3FFF 1
02A9 3FFF 1
02AA 3FFF 1
02AB 3FFF 1
02AC 3FFF 1
02AD 3FFF 1
02AE 3FFF 1
02AF 3FFF 1
02B0 3FFF 1
02B1 3FFF 1
02B2 3FFF 1
02B3 3FFF 1
02B4 3FFF 1
02B5 3FFF 1
02B6 3FFF 1
02B7 3FFF 1
02B8 3FFF 1
02B9 3FFF 1
02BA 3FFF 1
02BB 3FFF 1
02BC 3FFF 1
02BD 3FFF 1
02BE 3FFF 1
02BF 3FFF 1
02C0 3FFF 1
02C1 3FFF 1
02C2 3FFF 1
02C3 3FFF 1
02C4 3FFF 1
02C5 3FFF 1
02C6 3FFF 1
02C7 3FFF 1
02C8 3FFF 1
02C9 3FFF 1
02CA 3FFF 1
02CB 3FFF 1
02CC 3FFF 1
02CD 3FFF 1
02CE 3FFF 1
02CF 3FFF 1
02D0 3FFF 1
02D1 3FFF 1
02D2 3FFF 1
02D3 3FFF 1
02D4 3FFF 1
02D5 3FFF 1
02D6 3FFF 1
02D7 3FFF 1
02D8 3FFF 1
02D9 3FFF 1
02DA 3FFF 1
02DB 3FFF 1
02DC 3FFF 1
02DD 3FFF 1
02DE 3FFF 1
02DF 3FFF 1
02E0 3FFF 1
02E1 3FFF 1
02E2 3FFF 1
02E3 3FFF 1
02E4 3FFF 1
02E5 3FFF 1
02E6 3FFF 1
02E7 3FFF 1
02E8 3FFF 1
02E9 3FFF 1
02EA 3FFF 1
02EB 3FFF 1
02EC 3FFF 1
02ED 3FFF 1
02EE 3FFF 1
02EF 3FFF 1
02F0 3FFF 1
02F1 3FFF 1
02F2 3FFF 1
02F3 3FFF 1
02F4 3FFF 1
02F5 3FFF 1
02F6 3FFF 1
02F7 3FFF 1
02F8 3FFF 1
02F9 3FFF 1
02FA 3FFF 1
02FB 3FFF 1
02FC 3FFF 1
02FD 3FFF 1
02FE 3FFF 1
02FF 3FFF 1
0300 3FFF 1
0301 3FFF 1
0302 3FFF 1
0303 3FFF 1
0304 3FFF 1
0305 3FFF 1
0306 3FFF 1
0307 3FFF 1
0308 3FFF 1
0309 3FFF 1
030A 3FFF 1
030B 3FFF 1
030C 3FFF 1
030D 3FFF 1
030E 3FFF 1
030F 3FFF 1
0310 3FFF 1
0311 3FFF 1
0312 3FFF 1
0313 3FFF 1
0314 3FFF 1
0315 3FFF 1
0316 3FFF 1
0317 3FFF 1
0318 3FFF 1
0319 3FFF 1
031A 3FFF 1
031B 3FFF 1
031C 3FFF 1
031D 3FFF 1
031E 3FFF 1
031F 3FFF 1
0320 3FFF 1
0321 3FFF 1
0322 3FFF 1
0323 3FFF 1
0324 3FFF 1
0325 3FFF 1
0326 3FFF 1
0327 3FFF 1
0328 3FFF 1
0329 3FFF 1
032A 3FFF 1
032B 3FFF 1
032C 3FFF 1
032D 3FFF 1
032E 3FFF 1
032F 3FFF 1
0330 3FFF 1
0331 3FFF 1
0332 3FFF 1
0333 3FFF 1
0334 3FFF 1
0335 3FFF 1
0336 3FFF 1
0337 3FFF 1
0338 3FFF 1
0339 3FFF 1
033A 3FFF 1
033B 3FFF 1
033C 3FFF 1
033D 3FFF 1
033E 3FFF 1
033F 3FFF 1
0340 3FFF 1
0341 3FFF 1
0342 3FFF 1
0343 3FFF 1
0344 3FFF 1
0345 3FFF 1
0346 3FFF 1
0347 3FFF 1
0348 3FFF 1
0349 3FFF 1
034A 3FFF 1
034B 3FFF 1
034C 3FFF 1
034D 3FFF 1
034E 3FFF 1
034F 3FFF 1
0350 3FFF 1
0351 3FFF 1
0352 3FFF 1
0353 3FFF 1
0354 3FFF 1
0355 3FFF 1
0356 3FFF 1
0357 3FFF 1
0358 3FFF 1
0359 3FFF 1
035A 3FFF 1
035B 3FFF 1
035C 3FFF 1
035D 3FFF 1
035E 3FFF 1
035F 3FFF 1
0360 3FFF 1
0361 3FFF 1
0362 3FFF 1
0363 3FFF 1
0364 3FFF 1
0365 3FFF 1
0366 3FFF 1
0367 3FFF 1
0368 3FFF 1
0369 3FFF 1
036A 3FFF 1
036B 3FFF 1
036C 3FFF 1
036D 3FFF 1
036E 3FFF 1
036F 3FFF 1
0370 3FFF 1
0371 3FFF 1
0372 3FFF 1
0373 3FFF 1
0374 3FFF 1
0375 3FFF 1
0376 3FFF 1
0377 3FFF 1
0378 3FFF 1
0379 3FFF 1
037A 3FFF 1
037B 3FFF 1
037C 3FFF 1
037D 3FFF 1
037E 3FFF 1
037F 3FFF 1
0380 3FFF 1
0381 3FFF 1
0382 3FFF 1
0383 3FFF 1
0384 3FFF 1
0385 3FFF 1
0386 3FFF 1
0387 3FFF 1
0388 3FFF 1
0389 3FFF 1
038A 3FFF 1
038B 3FFF 1
038C 3FFF 1
038D 3FFF 1
038E 3FFF 1
038F 3FFF 1
0390 3FFF 1
0391 3FFF 1
0392 3FFF 1
0393 3FFF 1
0394 3FFF 1
0395 3FFF 1
0396 3FFF 1
0397 3FFF 1
0398 3FFF 1
0399 3FFF 1
039A 3FFF 1
039B 3FFF 1
039C 3FFF 1
039D 3FFF 1
039E 3FFF 1
039F 3FFF 1
03A0 3FFF 1
03A1 3FFF 1
03A2 3FFF 1
03A3 3FFF 1
03A4 3FFF 1
03A5 3FFF 1
03A6 3FFF 1
03A7 3FFF 1
03A8 3FFF 1
03A9 3FFF 1
03AA 3FFF 1
03AB 3FFF 1
03AC 3FFF 1
03AD 3FFF 1
03AE 3FFF 1
03AF 3FFF 1
03B0 3FFF 1
03B1 3FFF 1
03B2 3FFF 1
03B3 3FFF 1
03B4 3FFF 1
03B5 3FFF 1
03B6 3FFF 1
03B7 3FFF 1
03B8 3FFF 1
03B9 3FFF 1
03BA 3FFF 1
03BB 3FFF 1
03BC 3FFF 1
03BD 3FFF 1
03BE 3FFF 1
03BF 3FFF 1
03C0 3FFF 1
03C1 3FFF 1
03C2 3FFF 1
03C3 3FFF 1
03C4 3FFF 1
03C5 3FFF 1
03C6 3FFF 1
03C7 3FFF 1
03C8 3FFF 1
--- everything after this are just more 3FFF ---
./parsespivdd.py --txt verify_5mhz.txt --data PA6_ICPDA --clock PA3_ICPCK --enable VDD --falling | tee verify_5mhz_frames_falling.txt
Remove --falling to sample on the rising edge.cat verify_5mhz_frames_falling.txt | ./parsecommands.py
Nope, after analyzing properly the .bin being read back I'm still getting one bit offs. I've attached the correct .bin and the two .bins read on falling and rising edges :palm:
EDIT: It looks like this could be still too slow for correct sampling:
(https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/?action=dlattach;attach=605575)
One big problem is to capture the output image. Right now I print it to PDF or just take a screenshot from browser.
I plan to automate this by adding a canvas capture and save to image function later.
When all is fixed I will release the generator on github.
The voltage levels look suspiciously like zener voltages.
Could it be that they are 2.7V, 5.6V and 8.2V upon closer inspection?
Anybody has a an idea how to create a cheap circuit to create different voltages (12V / 8.5V / 6.5 V / 5V / 3V ...) based on MCU output (using some digital outputs).
This would be easy, just a LM317 and 2 resistors per voltage (and a decoupling capacitor). Then maybe some FETs to switch the output on and off, if it needs more power than a 4051 multiplexer can do.
Meanwhile I got one channel of my ADC working. I can now sample with 8 bit resolution, -10 V to +10 V, and 25 MHz samplerate:
https://www.eevblog.com/forum/projects/4-channel-adc-10-mhz-8-bit-design/msg2073310/#msg2073310 (https://www.eevblog.com/forum/projects/4-channel-adc-10-mhz-8-bit-design/msg2073310/#msg2073310)
Will solder the other 3 channels and finish the FPGA programming, then I can record a full programming cycle, with 25 MHz sampling rate for all 4 channels, and optionally 8 channels with a second board and still 25 MHz, if the bandwidth to the DDR3 RAM works out. Even if we don't need it anymore, was still fun to build it :)
The ULN2003 switches to GND.
For generating VDD and VPP I'd just use any random linear regulator, with NMOS for switching the divider resistor, one for each pin.
They're not that fast, you can actually see it settling on the Verify file that was uploaded with the analog Vpp.For generating VDD and VPP I'd just use any random linear regulator, with NMOS for switching the divider resistor, one for each pin.
I dont know how fast the voltage transitions have to be.
From the pictures in Davids video they seem to be rather fast.
Voltage regulators typically have settling times that are rather long.
It would be nice to have the feature to set any voltage from 2.0V to 12.0V
2.0V - 5.0V are needed for calibration later (at least with 0.1V steps).How is that? What are those used for?
After writing the firmware, the IC can be calibrated. Due to manufacturing differences the internal clock might need some tuning (up or down) to produce the exact desired frequency of e.g. 16MHz. This also depends on the supply voltage (VDD). So if you plan to use the IC with 3.1V later you need to calibrate it using 3.1V for VDD. Calibration itself is a very simple process. You just let the IC run a loop with e.g. 5000000 cycles, The IC outputs a signal when it starts and when it finishs. The flasher captures the time it took and then can increase or decrease the clock a tiny tiny bit to calibrate it.2.0V - 5.0V are needed for calibration later (at least with 0.1V steps).How is that? What are those used for?
I was looking at something like PWM output and LM371T but the refernce schematic looks big (lots of components and an opamp).
You could also do a variation ofThat's exactly what I thought about in my previous post, but that won't work if you also need to calibrate it running from 3 to 5V. It may work if you don't really give a damn about calibrating and use it only for programming, or allow calibrating only at preset voltages (which to be honest, would be the case - aside from 3.3, 3.6 and 5V, who really needs any other voltages?)
http://www.circuitstoday.com/few-lm317-voltage-regulator-circuits (http://www.circuitstoday.com/few-lm317-voltage-regulator-circuits)
look for "Adjustable regulator with digitally selected output"
Replace the transistors with a ULN2003.
I think they cost USD 0.15 plus a few resistors.
You could also do a variation ofThat's exactly what I thought about in my previous post, but that won't work if you also need to calibrate it running from 3 to 5V. It may work if you don't really give a damn about calibrating and use it only for programming, or allow calibrating only at preset voltages (which to be honest, would be the case - aside from 3.3, 3.6 and 5V, who really needs any other voltages?)
http://www.circuitstoday.com/few-lm317-voltage-regulator-circuits (http://www.circuitstoday.com/few-lm317-voltage-regulator-circuits)
look for "Adjustable regulator with digitally selected output"
Replace the transistors with a ULN2003.
I think they cost USD 0.15 plus a few resistors.
You may consider a PWM DAC - below one gives you almost any Vout from 0-12V.
I did a new capture of VERIFY.
This time I lowered the voltage to detect a 1 down to 1.2V (was 1.5V).
I also found a way to capture the complete VERIFY command at 200MHz (the logic analyzer has a compression feature).
This messed up my trigger a bit (you see the scanning spikes before and after the command, which are used by writer to detect IC presence).
I hope now we can read the signal 100% ok without any tricks.
JS
116050251: FLASH_READ_B
No data (dummy read)
121460163: FLASH_READ_B
ADDR DATA ?
-----------
07EF 1FFE 0
07F0 0025 0
07F1 0025 1
125171746: ??? (1010010110100101101001011010001100001010101000010)
132819271: ??? (1010010110100101101001011010011001101010101000010)
189653978: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 0026 3FFF 3FFF 3FFF
194375712: FLASH_READ_B
ADDR DATA ?
-----------
07F0 0026 0
198033461: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 3FFF 0026 3FFF 3FFF
202755194: FLASH_READ_B
ADDR DATA ?
-----------
07F1 0002 1
206415006: FLASH_READ_B
ADDR DATA ?
-----------
07E0 1FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 1FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 1FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 1FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0002 0
07F1 0002 1
07F2 1FFF 0
07F3 1FFF 0
07F4 1FFF 1
07F5 1FFF 1
07F6 1FFF 1
07F7 1FFF 1
07F8 1FFF 1
07F9 1FFF 1
07FA 1FFF 1
07FB 1FFF 1
07FC 1FFF 1
07FD 1FFF 1
07FE 1FFF 1
07FF 1FFF 1
210876950: FLASH_READ_B
ADDR DATA ?
-----------
07E0 1FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 1FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 1FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 1FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 1FFF 0
07F3 1FFF 0
07F4 1FFF 1
07F5 1FFF 1
07F6 1FFF 1
07F7 1FFF 1
07F8 1FFF 1
07F9 1FFF 1
07FA 1FFF 1
07FB 1FFF 1
07FC 1FFF 1
07FD 1FFF 1
07FE 1FFF 1
07FF 1FFF 1
216360622: FLASH_READ_B
ADDR DATA ?
-----------
0000 1FFF 0
0001 1FFF 0
0002 1FFF 1
0003 1FFF 1
0004 1FFF 1
0005 1FFF 1
0006 1FFF 1
0007 1FFF 1
0008 1FFF 1
0009 1FFF 1
000A 1FFF 1
000B 1FFF 1
000C 1FFF 1
000D 1FFF 1
000E 1FFF 1
000F 1FFF 1
0010 1FFF 1
0011 1FFF 1
0012 1FFF 1
0013 1FFF 1
0014 1FFF 1
0015 1FFF 1
0016 1FFF 1
0017 1FFF 1
0018 1FFF 1
0019 1FFF 1
001A 1FFF 1
001B 1FFF 1
001C 1FFF 1
001D 1FFF 1
001E 1FFF 1
001F 1FFF 1
0020 1FFF 1
0021 1FFF 1
0022 1FFF 1
0023 1FFF 1
0024 1FFF 1
0025 1FFF 1
0026 1FFF 1
0027 1FFF 1
0028 1FFF 1
0029 1FFF 1
002A 1FFF 1
002B 1FFF 1
002C 1FFF 1
002D 1FFF 1
002E 1FFF 1
002F 1FFF 1
0030 1FFF 1
0031 1FFF 1
0032 1FFF 1
0033 1FFF 1
0034 1FFF 1
0035 1FFF 1
0036 1FFF 1
0037 1FFF 1
0038 1FFF 1
0039 1FFF 1
003A 1FFF 1
003B 1FFF 1
003C 1FFF 1
003D 1FFF 1
003E 1FFF 1
003F 1FFF 1
0040 1FFF 1
0041 1FFF 1
0042 1FFF 1
0043 1FFF 1
0044 1FFF 1
0045 1FFF 1
0046 1FFF 1
0047 1FFF 1
0048 1FFF 1
0049 1FFF 1
004A 1FFF 1
004B 1FFF 1
004C 1FFF 1
004D 1FFF 1
004E 1FFF 1
004F 1FFF 1
0050 1FFF 1
0051 1FFF 1
0052 1FFF 1
0053 1FFF 1
0054 1FFF 1
0055 1FFF 1
0056 1FFF 1
0057 1FFF 1
0058 1FFF 1
0059 1FFF 1
005A 1FFF 1
005B 1FFF 1
005C 1FFF 1
005D 1FFF 1
005E 1FFF 1
005F 1FFF 1
0060 1FFF 1
0061 1FFF 1
0062 1FFF 1
0063 1FFF 1
0064 1FFF 1
0065 1FFF 1
0066 1FFF 1
0067 1FFF 1
0068 1FFF 1
0069 1FFF 1
006A 1FFF 1
006B 1FFF 1
006C 1FFF 1
006D 1FFF 1
006E 1FFF 1
006F 1FFF 1
0070 1FFF 1
0071 1FFF 1
0072 1FFF 1
0073 1FFF 1
0074 1FFF 1
0075 1FFF 1
0076 1FFF 1
0077 1FFF 1
0078 1FFF 1
0079 1FFF 1
007A 1FFF 1
007B 1FFF 1
007C 1FFF 1
007D 1FFF 1
007E 1FFF 1
007F 1FFF 1
0080 1FFF 1
0081 1FFF 1
0082 1FFF 1
0083 1FFF 1
0084 1FFF 1
0085 1FFF 1
0086 1FFF 1
0087 1FFF 1
0088 1FFF 1
0089 1FFF 1
008A 1FFF 1
008B 1FFF 1
008C 1FFF 1
008D 1FFF 1
008E 1FFF 1
008F 1FFF 1
0090 1FFF 1
0091 1FFF 1
0092 1FFF 1
0093 1FFF 1
0094 1FFF 1
0095 1FFF 1
0096 1FFF 1
0097 1FFF 1
0098 1FFF 1
0099 1FFF 1
009A 1FFF 1
009B 1FFF 1
009C 1FFF 1
009D 1FFF 1
009E 1FFF 1
009F 1FFF 1
00A0 1FFF 1
00A1 1FFF 1
00A2 1FFF 1
00A3 1FFF 1
00A4 1FFF 1
00A5 1FFF 1
00A6 1FFF 1
00A7 1FFF 1
00A8 1FFF 1
00A9 1FFF 1
00AA 1FFF 1
00AB 1FFF 1
00AC 1FFF 1
00AD 1FFF 1
00AE 1FFF 1
00AF 1FFF 1
00B0 1FFF 1
00B1 1FFF 1
00B2 1FFF 1
00B3 1FFF 1
00B4 1FFF 1
00B5 1FFF 1
00B6 1FFF 1
00B7 1FFF 1
00B8 1FFF 1
00B9 1FFF 1
00BA 1FFF 1
00BB 1FFF 1
00BC 1FFF 1
00BD 1FFF 1
00BE 1FFF 1
00BF 1FFF 1
00C0 1FFF 1
00C1 1FFF 1
00C2 1FFF 1
00C3 1FFF 1
00C4 1FFF 1
00C5 1FFF 1
00C6 1FFF 1
00C7 1FFF 1
00C8 1FFF 1
00C9 1FFF 1
00CA 1FFF 1
00CB 1FFF 1
00CC 1FFF 1
00CD 1FFF 1
00CE 1FFF 1
00CF 1FFF 1
00D0 1FFF 1
00D1 1FFF 1
00D2 1FFF 1
00D3 1FFF 1
00D4 1FFF 1
00D5 1FFF 1
00D6 1FFF 1
00D7 1FFF 1
00D8 1FFF 1
00D9 1FFF 1
00DA 1FFF 1
00DB 1FFF 1
00DC 1FFF 1
00DD 1FFF 1
00DE 1FFF 1
00DF 1FFF 1
00E0 1FFF 1
00E1 1FFF 1
00E2 1FFF 1
00E3 1FFF 1
00E4 1FFF 1
00E5 1FFF 1
00E6 1FFF 1
00E7 1FFF 1
00E8 1FFF 1
00E9 1FFF 1
00EA 1FFF 1
00EB 1FFF 1
00EC 1FFF 1
00ED 1FFF 1
00EE 1FFF 1
00EF 1FFF 1
00F0 1FFF 1
00F1 1FFF 1
00F2 1FFF 1
00F3 1FFF 1
00F4 1FFF 1
00F5 1FFF 1
00F6 1FFF 1
00F7 1FFF 1
00F8 1FFF 1
00F9 1FFF 1
00FA 1FFF 1
00FB 1FFF 1
00FC 1FFF 1
00FD 1FFF 1
00FE 1FFF 1
00FF 1FFF 1
0100 1FFF 1
0101 1FFF 1
0102 1FFF 1
0103 1FFF 1
0104 1FFF 1
0105 1FFF 1
0106 1FFF 1
0107 1FFF 1
0108 1FFF 1
0109 1FFF 1
010A 1FFF 1
010B 1FFF 1
010C 1FFF 1
010D 1FFF 1
010E 1FFF 1
010F 1FFF 1
0110 1FFF 1
0111 1FFF 1
0112 1FFF 1
0113 1FFF 1
0114 1FFF 1
0115 1FFF 1
0116 1FFF 1
0117 1FFF 1
0118 1FFF 1
0119 1FFF 1
011A 1FFF 1
011B 1FFF 1
011C 1FFF 1
011D 1FFF 1
011E 1FFF 1
011F 1FFF 1
0120 1FFF 1
0121 1FFF 1
0122 1FFF 1
0123 1FFF 1
0124 1FFF 1
0125 1FFF 1
0126 1FFF 1
0127 1FFF 1
0128 1FFF 1
0129 1FFF 1
012A 1FFF 1
012B 1FFF 1
012C 1FFF 1
012D 1FFF 1
012E 1FFF 1
012F 1FFF 1
0130 1FFF 1
0131 1FFF 1
0132 1FFF 1
0133 1FFF 1
0134 1FFF 1
0135 1FFF 1
0136 1FFF 1
0137 1FFF 1
0138 1FFF 1
0139 1FFF 1
013A 1FFF 1
013B 1FFF 1
013C 1FFF 1
013D 1FFF 1
013E 1FFF 1
013F 1FFF 1
0140 1FFF 1
0141 1FFF 1
0142 1FFF 1
0143 1FFF 1
0144 1FFF 1
0145 1FFF 1
0146 1FFF 1
0147 1FFF 1
0148 1FFF 1
0149 1FFF 1
014A 1FFF 1
014B 1FFF 1
014C 1FFF 1
014D 1FFF 1
014E 1FFF 1
014F 1FFF 1
0150 1FFF 1
0151 1FFF 1
0152 1FFF 1
0153 1FFF 1
0154 1FFF 1
0155 1FFF 1
0156 1FFF 1
0157 1FFF 1
0158 1FFF 1
0159 1FFF 1
015A 1FFF 1
015B 1FFF 1
015C 1FFF 1
015D 1FFF 1
015E 1FFF 1
015F 1FFF 1
0160 1FFF 1
0161 1FFF 1
0162 1FFF 1
0163 1FFF 1
0164 1FFF 1
0165 1FFF 1
0166 1FFF 1
0167 1FFF 1
0168 1FFF 1
0169 1FFF 1
016A 1FFF 1
016B 1FFF 1
016C 1FFF 1
016D 1FFF 1
016E 1FFF 1
016F 1FFF 1
0170 1FFF 1
0171 1FFF 1
0172 1FFF 1
0173 1FFF 1
0174 1FFF 1
0175 1FFF 1
0176 1FFF 1
0177 1FFF 1
0178 1FFF 1
0179 1FFF 1
017A 1FFF 1
017B 1FFF 1
017C 1FFF 1
017D 1FFF 1
017E 1FFF 1
017F 1FFF 1
[cut to keep message under 50k chars - they're all 1FFF anyway]
07C0 1FFF 1
07C1 1FFF 1
07C2 1FFF 1
07C3 1FFF 1
07C4 1FFF 1
07C5 1FFF 1
07C6 1FFF 1
07C7 1FFF 1
07C8 1FFF 1
07C9 1FFF 1
07CA 1FFF 1
07CB 1FFF 1
07CC 1FFF 1
07CD 1FFF 1
07CE 1FFF 1
07CF 1FFF 1
07D0 1FFF 1
07D1 1FFF 1
07D2 1FFF 1
07D3 1FFF 1
07D4 1FFF 1
07D5 1FFF 1
07D6 1FFF 1
07D7 1FFF 1
07D8 1FFF 1
07D9 1FFF 1
07DA 1FFF 1
07DB 1FFF 1
07DC 1FFF 1
07DD 1FFF 1
07DE 1FFF 1
07DF 1FFF 1
274899016: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
0000 0070 2F00 0182 3FED
0004 018B 3FEE 019A 2F80
0008 019B 2F1C 0183 3FFE
000C 2AFF 3054 3FED 0B81
0010 1F91 2F05 0B80 1AD0
0014 3013 1F90 0063 3016
0018 1180 3016 1D90 18D0
001C 301B 2F01 1950 2FFF
0020 0C01 018B 0B81 1AD0
0024 3023 1B50 304F 2F04
0028 0188 18D0 3029 2F02
002C 0182 1304 1305 2F6E
0030 0B82 2F00 0B83 0006
0034 0B04 0007 0805 1584
0038 1685 1004 1282 1083
003C 1A40 3033 1F90 1AD0
0040 303F 1584 1685 0590
0044 18D0 3044 1950 303F
0048 1D90 1AD0 3049 18D0
004C 304B 1B50 302B 18D0
0050 304F 1B50 3011 3053
0054 018B 1ED1 1ED0 2F03
0058 0BC1 2F8A 0BC0 2F56
005C 0063 305C 11C0 305C
0060 11C1 305C 1CD0 2F03
0064 0BC1 2F8A 0BC0 2F56
0068 0063 3068 11C0 3068
006C 11C1 3068 3056 3FFF
282886516: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0026 0026 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 02FF 31FD
290648067: FLASH_READ_B
ADDR DATA ?
-----------
07E0 1FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 1FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 1FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 1FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 1FFF 0
07F3 1FFF 0
07F4 1FFF 1
07F5 1FFF 1
07F6 1FFF 1
07F7 1FFF 1
07F8 1850 1
07F9 1F54 1
07FA 1FFF 1
07FB 1FFF 1
07FC 1FFF 1
07FD 1FFF 1
07FE 02FF 1
07FF 11FD 1
296125972: FLASH_READ_B
ADDR DATA ?
-----------
0000 0070 0
0001 0F00 0
0002 0182 0
0003 1FED 0
0004 018B 0
0005 1FEE 1
0006 019A 0
0007 0F80 1
0008 019B 0
0009 0F1C 0
000A 0183 0
000B 1FFE 0
000C 0AFF 0
000D 1054 1
000E 1FED 0
000F 0B81 1
0010 1F91 1
0011 0F05 0
0012 0B80 1
0013 1AD0 0
0014 1013 0
0015 1F90 1
0016 0063 1
0017 1016 1
0018 1180 0
0019 1016 1
001A 1D90 1
001B 18D0 1
001C 101B 1
001D 0F01 1
001E 1950 1
001F 0FFF 0
0020 0C01 1
0021 018B 0
0022 0B81 0
0023 1AD0 0
0024 1023 0
0025 1B50 1
0026 104F 1
0027 0F04 1
0028 0188 1
0029 18D0 0
002A 1029 0
002B 0F02 1
002C 0182 1
002D 1304 0
002E 1305 0
002F 0F6E 1
0030 0B82 1
0031 0F00 0
0032 0B83 0
0033 0006 0
0034 0B04 0
0035 0007 0
0036 0805 0
0037 1584 0
0038 1685 0
0039 1004 1
003A 1282 1
003B 1083 1
003C 1A40 1
003D 1033 1
003E 1F90 1
003F 1AD0 1
0040 103F 1
0041 1584 1
0042 1685 1
0043 0590 1
0044 18D0 1
0045 1044 0
0046 1950 1
0047 103F 1
0048 1D90 1
0049 1AD0 1
004A 1049 1
004B 18D0 1
004C 104B 1
004D 1B50 1
004E 102B 1
004F 18D0 1
0050 104F 1
0051 1B50 1
0052 1011 1
0053 1053 1
0054 018B 1
0055 1ED1 1
0056 1ED0 0
0057 0F03 1
0058 0BC1 1
0059 0F8A 0
005A 0BC0 0
005B 0F56 0
005C 0063 0
005D 105C 0
005E 11C0 0
005F 105C 1
0060 11C1 1
0061 105C 1
0062 1CD0 1
0063 0F03 1
0064 0BC1 1
0065 0F8A 0
0066 0BC0 0
0067 0F56 0
0068 0063 0
0069 1068 0
006A 11C0 0
006B 1068 1
006C 11C1 1
006D 1068 1
006E 1056 1
006F 1FFF 1
304013520: FLASH_READ_B
ADDR DATA ?
-----------
07E0 1FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 1FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 1FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 1FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0002 0
07F1 0002 1
07F2 1FFF 0
07F3 1FFF 0
07F4 1FFF 1
07F5 1FFF 1
07F6 1FFF 1
07F7 1FFF 1
07F8 1850 1
07F9 1F54 1
07FA 1FFF 1
07FB 1FFF 1
07FC 1FFF 1
07FD 1FFF 1
07FE 027F 1
07FF 11FD 1
308485046: FLASH_READ_B
ADDR DATA ?
-----------
0000 0070 0
0001 0F00 0
0002 0180 0
0003 1FED 0
0004 0183 0
0005 1FEE 0
0006 0198 0
0007 0F80 0
0008 0199 0
0009 071C 0
000A 0181 0
000B 1FFE 0
000C 02FF 0
000D 1054 0
000E 1FED 0
000F 0981 1
0010 1F91 1
0011 0701 0
0012 0380 0
0013 1AD0 0
0014 1013 0
0015 1F90 1
0016 0063 1
0017 1012 1
0018 1180 0
0019 1006 0
001A 1D90 1
001B 1850 1
001C 101B 1
001D 0F00 1
001E 1910 1
001F 0FFF 0
0020 0C00 1
0021 008B 0
0022 0B81 0
0023 1AD0 0
0024 1023 0
0025 1950 1
0026 104F 1
0027 0F00 0
0028 0180 1
0029 18D0 0
002A 1020 0
002B 0F02 1
002C 0080 1
002D 1304 0
002E 1301 0
002F 0F6E 0
0030 0B80 1
0031 0F00 0
0032 0B83 0
0033 0006 0
0034 0900 0
0035 0003 0
0036 0005 0
0037 1584 0
0038 1685 0
0039 1000 0
003A 1202 1
003B 1081 1
003C 1A40 1
003D 1013 1
003E 1F90 1
003F 1AD0 1
0040 103F 1
0041 1584 1
0042 1285 1
0043 0590 1
0044 1850 1
0045 1004 0
0046 1910 1
0047 101F 1
0048 1C90 1
0049 1AD0 1
004A 1000 1
004B 18D0 1
004C 1003 1
004D 1B50 1
004E 1023 1
004F 1850 1
0050 1007 1
0051 1B50 1
0052 1011 1
0053 1013 1
0054 0183 1
0055 1ED1 1
0056 1ED0 0
0057 0F03 1
0058 0BC0 1
0059 0F8A 0
005A 0BC0 0
005B 0F56 0
005C 0063 0
005D 105C 0
005E 10C0 0
005F 101C 1
0060 11C0 1
0061 101C 1
0062 1CD0 1
0063 0F03 1
0064 03C0 1
0065 0F8A 0
0066 0BC0 0
0067 0F56 0
0068 0063 0
0069 1060 0
006A 10C0 0
006B 1028 1
006C 10C1 1
006D 1028 1
006E 1056 1
006F 1FFF 1
315382652: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
0000 0070 2F00 0182 3FED
0004 018B 3FEE 019A 2F80
0008 019B 2F1C 0183 3FFE
000C 2AFF 3054 3FED 0B81
0010 1F91 2F05 0B80 1AD0
0014 3013 1F90 0063 3016
0018 1180 3016 1D90 18D0
001C 301B 2F01 1950 2FFF
0020 0C01 018B 0B81 1AD0
0024 3023 1B50 304F 2F04
0028 0188 18D0 3029 2F02
002C 0182 1304 1305 2F6E
0030 0B82 2F00 0B83 0006
0034 0B04 0007 0805 1584
0038 1685 1004 1282 1083
003C 1A40 3033 1F90 1AD0
0040 303F 1584 1685 0590
0044 18D0 3044 1950 303F
0048 1D90 1AD0 3049 18D0
004C 304B 1B50 302B 18D0
0050 304F 1B50 3011 3053
0054 018B 1ED1 1ED0 2F03
0058 0BC1 2F8A 0BC0 2F56
005C 0063 305C 11C0 305C
0060 11C1 305C 1CD0 2F03
0064 0BC1 2F8A 0BC0 2F56
0068 0063 3068 11C0 3068
006C 11C1 3068 3056 3FFF
326049413: 0000001101001010001110011010010100011100
348308113: 0000001101001010001110011010010100011100
373491264: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0026 0026 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 0282 31FD
378464965: FLASH_READ_B
ADDR DATA ?
-----------
07E0 1FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 1FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 1FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 1FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 1FFF 0
07F3 1FFF 0
07F4 1FFF 1
07F5 1FFF 1
07F6 1FFF 1
07F7 1FFF 1
07F8 1850 1
07F9 1F54 1
07FA 1FFF 1
07FB 1FFF 1
07FC 1FFF 1
07FD 1FFF 1
07FE 0282 1
07FF 11FD 1
383944624: FLASH_READ_B
ADDR DATA ?
-----------
07E0 1FFF 0
07E1 1FFF 0
07E2 1FFF 1
07E3 1FFF 1
07E4 1FFF 1
07E5 1FFF 1
07E6 1FFF 1
07E7 1FFF 1
07E8 1FFF 1
07E9 1FFF 1
07EA 1FFF 1
07EB 1FFF 1
07EC 1FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0002 0
07F1 0002 1
07F2 1FFF 0
07F3 1FFF 0
07F4 1FFF 1
07F5 1FFF 1
07F6 1FFF 1
07F7 1FFF 1
07F8 1850 1
07F9 1F54 1
07FA 1FFF 1
07FB 1FFF 1
07FC 1FFF 1
07FD 1FFF 1
07FE 0202 1
07FF 11FD 1
388416397: FLASH_WRITE_B
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0026 0026 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 0282 31FD
116050423: FLASH_READ_A
No data (dummy read)
121460335: FLASH_READ_A
ADDR DATA ?
-----------
07EF 1FFE 0
07F0 0025 0
07F1 0025 1
125171918: ??? (1010010110100101101001011010001100011010101000010)
132819443: ??? (1010010110100101101001011010011001111010101000010)
189654150: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 0026 3FFF 3FFF 3FFF
194375883: FLASH_READ_A
ADDR DATA ?
-----------
07F0 0026 0
198033633: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
07F0 3FFF 0026 3FFF 3FFF
202755366: FLASH_READ_A
ADDR DATA ?
-----------
07F1 0026 1
206415178: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 3FFF 1
07F9 3FFF 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 3FFF 1
07FF 3FFF 1
210877122: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 3FFF 1
07F9 3FFF 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 3FFF 1
07FF 3FFF 1
216360794: FLASH_READ_A
ADDR DATA ?
-----------
0000 3FFF 0
0001 3FFF 0
0002 3FFF 1
0003 3FFF 1
0004 3FFF 1
0005 3FFF 1
0006 3FFF 1
0007 3FFF 1
0008 3FFF 1
0009 3FFF 1
000A 3FFF 1
000B 3FFF 1
000C 3FFF 1
000D 3FFF 1
000E 3FFF 1
000F 3FFF 1
0010 3FFF 1
0011 3FFF 1
0012 3FFF 1
0013 3FFF 1
0014 3FFF 1
0015 3FFF 1
0016 3FFF 1
0017 3FFF 1
0018 3FFF 1
0019 3FFF 1
001A 3FFF 1
001B 3FFF 1
001C 3FFF 1
001D 3FFF 1
001E 3FFF 1
001F 3FFF 1
0020 3FFF 1
0021 3FFF 1
0022 3FFF 1
0023 3FFF 1
0024 3FFF 1
0025 3FFF 1
0026 3FFF 1
0027 3FFF 1
0028 3FFF 1
0029 3FFF 1
002A 3FFF 1
002B 3FFF 1
002C 3FFF 1
002D 3FFF 1
002E 3FFF 1
002F 3FFF 1
0030 3FFF 1
0031 3FFF 1
0032 3FFF 1
0033 3FFF 1
0034 3FFF 1
0035 3FFF 1
0036 3FFF 1
0037 3FFF 1
0038 3FFF 1
0039 3FFF 1
003A 3FFF 1
003B 3FFF 1
003C 3FFF 1
003D 3FFF 1
003E 3FFF 1
003F 3FFF 1
0040 3FFF 1
0041 3FFF 1
0042 3FFF 1
0043 3FFF 1
0044 3FFF 1
0045 3FFF 1
0046 3FFF 1
0047 3FFF 1
0048 3FFF 1
0049 3FFF 1
004A 3FFF 1
004B 3FFF 1
004C 3FFF 1
004D 3FFF 1
004E 3FFF 1
004F 3FFF 1
0050 3FFF 1
0051 3FFF 1
0052 3FFF 1
0053 3FFF 1
0054 3FFF 1
0055 3FFF 1
0056 3FFF 1
0057 3FFF 1
0058 3FFF 1
0059 3FFF 1
005A 3FFF 1
005B 3FFF 1
005C 3FFF 1
005D 3FFF 1
005E 3FFF 1
005F 3FFF 1
0060 3FFF 1
0061 3FFF 1
0062 3FFF 1
0063 3FFF 1
0064 3FFF 1
0065 3FFF 1
0066 3FFF 1
0067 3FFF 1
0068 3FFF 1
0069 3FFF 1
006A 3FFF 1
006B 3FFF 1
006C 3FFF 1
006D 3FFF 1
006E 3FFF 1
006F 3FFF 1
0070 3FFF 1
0071 3FFF 1
0072 3FFF 1
0073 3FFF 1
0074 3FFF 1
0075 3FFF 1
0076 3FFF 1
0077 3FFF 1
0078 3FFF 1
0079 3FFF 1
007A 3FFF 1
007B 3FFF 1
007C 3FFF 1
007D 3FFF 1
007E 3FFF 1
007F 3FFF 1
0080 3FFF 1
0081 3FFF 1
0082 3FFF 1
0083 3FFF 1
0084 3FFF 1
0085 3FFF 1
0086 3FFF 1
0087 3FFF 1
0088 3FFF 1
0089 3FFF 1
008A 3FFF 1
008B 3FFF 1
008C 3FFF 1
008D 3FFF 1
008E 3FFF 1
008F 3FFF 1
0090 3FFF 1
0091 3FFF 1
0092 3FFF 1
0093 3FFF 1
0094 3FFF 1
0095 3FFF 1
0096 3FFF 1
0097 3FFF 1
0098 3FFF 1
0099 3FFF 1
009A 3FFF 1
009B 3FFF 1
009C 3FFF 1
009D 3FFF 1
009E 3FFF 1
009F 3FFF 1
00A0 3FFF 1
00A1 3FFF 1
00A2 3FFF 1
00A3 3FFF 1
00A4 3FFF 1
00A5 3FFF 1
00A6 3FFF 1
00A7 3FFF 1
00A8 3FFF 1
00A9 3FFF 1
00AA 3FFF 1
00AB 3FFF 1
00AC 3FFF 1
00AD 3FFF 1
00AE 3FFF 1
00AF 3FFF 1
00B0 3FFF 1
00B1 3FFF 1
00B2 3FFF 1
00B3 3FFF 1
00B4 3FFF 1
00B5 3FFF 1
00B6 3FFF 1
00B7 3FFF 1
00B8 3FFF 1
00B9 3FFF 1
00BA 3FFF 1
00BB 3FFF 1
00BC 3FFF 1
00BD 3FFF 1
00BE 3FFF 1
00BF 3FFF 1
00C0 3FFF 1
00C1 3FFF 1
00C2 3FFF 1
00C3 3FFF 1
00C4 3FFF 1
00C5 3FFF 1
00C6 3FFF 1
00C7 3FFF 1
00C8 3FFF 1
00C9 3FFF 1
00CA 3FFF 1
00CB 3FFF 1
00CC 3FFF 1
00CD 3FFF 1
00CE 3FFF 1
00CF 3FFF 1
00D0 3FFF 1
00D1 3FFF 1
00D2 3FFF 1
00D3 3FFF 1
00D4 3FFF 1
00D5 3FFF 1
00D6 3FFF 1
00D7 3FFF 1
00D8 3FFF 1
00D9 3FFF 1
00DA 3FFF 1
00DB 3FFF 1
00DC 3FFF 1
00DD 3FFF 1
00DE 3FFF 1
00DF 3FFF 1
00E0 3FFF 1
00E1 3FFF 1
00E2 3FFF 1
00E3 3FFF 1
00E4 3FFF 1
00E5 3FFF 1
00E6 3FFF 1
00E7 3FFF 1
00E8 3FFF 1
00E9 3FFF 1
00EA 3FFF 1
00EB 3FFF 1
00EC 3FFF 1
00ED 3FFF 1
00EE 3FFF 1
00EF 3FFF 1
00F0 3FFF 1
00F1 3FFF 1
00F2 3FFF 1
00F3 3FFF 1
00F4 3FFF 1
00F5 3FFF 1
00F6 3FFF 1
00F7 3FFF 1
00F8 3FFF 1
00F9 3FFF 1
00FA 3FFF 1
00FB 3FFF 1
00FC 3FFF 1
00FD 3FFF 1
00FE 3FFF 1
00FF 3FFF 1
0100 3FFF 1
0101 3FFF 1
0102 3FFF 1
0103 3FFF 1
0104 3FFF 1
0105 3FFF 1
0106 3FFF 1
0107 3FFF 1
0108 3FFF 1
0109 3FFF 1
010A 3FFF 1
010B 3FFF 1
010C 3FFF 1
010D 3FFF 1
010E 3FFF 1
010F 3FFF 1
0110 3FFF 1
0111 3FFF 1
0112 3FFF 1
0113 3FFF 1
0114 3FFF 1
0115 3FFF 1
0116 3FFF 1
0117 3FFF 1
0118 3FFF 1
0119 3FFF 1
011A 3FFF 1
011B 3FFF 1
011C 3FFF 1
011D 3FFF 1
011E 3FFF 1
011F 3FFF 1
0120 3FFF 1
0121 3FFF 1
0122 3FFF 1
0123 3FFF 1
0124 3FFF 1
0125 3FFF 1
0126 3FFF 1
0127 3FFF 1
0128 3FFF 1
0129 3FFF 1
012A 3FFF 1
012B 3FFF 1
012C 3FFF 1
012D 3FFF 1
012E 3FFF 1
012F 3FFF 1
0130 3FFF 1
0131 3FFF 1
0132 3FFF 1
0133 3FFF 1
0134 3FFF 1
0135 3FFF 1
0136 3FFF 1
0137 3FFF 1
0138 3FFF 1
0139 3FFF 1
013A 3FFF 1
013B 3FFF 1
013C 3FFF 1
013D 3FFF 1
013E 3FFF 1
013F 3FFF 1
0140 3FFF 1
0141 3FFF 1
0142 3FFF 1
0143 3FFF 1
0144 3FFF 1
0145 3FFF 1
0146 3FFF 1
0147 3FFF 1
0148 3FFF 1
0149 3FFF 1
014A 3FFF 1
014B 3FFF 1
014C 3FFF 1
014D 3FFF 1
014E 3FFF 1
014F 3FFF 1
0150 3FFF 1
0151 3FFF 1
0152 3FFF 1
0153 3FFF 1
0154 3FFF 1
0155 3FFF 1
0156 3FFF 1
0157 3FFF 1
0158 3FFF 1
0159 3FFF 1
015A 3FFF 1
015B 3FFF 1
015C 3FFF 1
015D 3FFF 1
015E 3FFF 1
015F 3FFF 1
0160 3FFF 1
0161 3FFF 1
0162 3FFF 1
0163 3FFF 1
0164 3FFF 1
0165 3FFF 1
0166 3FFF 1
0167 3FFF 1
0168 3FFF 1
0169 3FFF 1
016A 3FFF 1
016B 3FFF 1
016C 3FFF 1
016D 3FFF 1
016E 3FFF 1
016F 3FFF 1
0170 3FFF 1
0171 3FFF 1
0172 3FFF 1
0173 3FFF 1
0174 3FFF 1
0175 3FFF 1
0176 3FFF 1
0177 3FFF 1
0178 3FFF 1
0179 3FFF 1
017A 3FFF 1
017B 3FFF 1
017C 3FFF 1
017D 3FFF 1
017E 3FFF 1
017F 3FFF 1
[cut to keep under 50k chars - all is 3FFF]
07C0 3FFF 1
07C1 3FFF 1
07C2 3FFF 1
07C3 3FFF 1
07C4 3FFF 1
07C5 3FFF 1
07C6 3FFF 1
07C7 3FFF 1
07C8 3FFF 1
07C9 3FFF 1
07CA 3FFF 1
07CB 3FFF 1
07CC 3FFF 1
07CD 3FFF 1
07CE 3FFF 1
07CF 3FFF 1
07D0 3FFF 1
07D1 3FFF 1
07D2 3FFF 1
07D3 3FFF 1
07D4 3FFF 1
07D5 3FFF 1
07D6 3FFF 1
07D7 3FFF 1
07D8 3FFF 1
07D9 3FFF 1
07DA 3FFF 1
07DB 3FFF 1
07DC 3FFF 1
07DD 3FFF 1
07DE 3FFF 1
07DF 3FFF 1
274899188: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
0000 0070 2F00 0182 3FED
0004 018B 3FEE 019A 2F80
0008 019B 2F1C 0183 3FFE
000C 2AFF 3054 3FED 0B81
0010 1F91 2F05 0B80 1AD0
0014 3013 1F90 0063 3016
0018 1180 3016 1D90 18D0
001C 301B 2F01 1950 2FFF
0020 0C01 018B 0B81 1AD0
0024 3023 1B50 304F 2F04
0028 0188 18D0 3029 2F02
002C 0182 1304 1305 2F6E
0030 0B82 2F00 0B83 0006
0034 0B04 0007 0805 1584
0038 1685 1004 1282 1083
003C 1A40 3033 1F90 1AD0
0040 303F 1584 1685 0590
0044 18D0 3044 1950 303F
0048 1D90 1AD0 3049 18D0
004C 304B 1B50 302B 18D0
0050 304F 1B50 3011 3053
0054 018B 1ED1 1ED0 2F03
0058 0BC1 2F8A 0BC0 2F56
005C 0063 305C 11C0 305C
0060 11C1 305C 1CD0 2F03
0064 0BC1 2F8A 0BC0 2F56
0068 0063 3068 11C0 3068
006C 11C1 3068 3056 3FFF
282886688: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0026 0026 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 02FF 31FD
290648239: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 02FF 1
07FF 31FD 1
296126144: FLASH_READ_A
ADDR DATA ?
-----------
0000 0070 0
0001 2F00 0
0002 0182 0
0003 3FED 0
0004 018B 0
0005 3FEE 1
0006 019A 0
0007 2F80 1
0008 019B 0
0009 2F1C 0
000A 0183 0
000B 3FFE 0
000C 2AFF 0
000D 3054 1
000E 3FED 0
000F 0B81 1
0010 1F91 1
0011 2F05 0
0012 0B80 1
0013 1AD0 0
0014 3013 0
0015 1F90 1
0016 0063 1
0017 3016 1
0018 1180 0
0019 3016 1
001A 1D90 1
001B 18D0 1
001C 301B 1
001D 2F01 1
001E 1950 1
001F 2FFF 0
0020 0C01 1
0021 018B 0
0022 0B81 0
0023 1AD0 0
0024 3023 0
0025 1B50 1
0026 304F 1
0027 2F04 1
0028 0188 1
0029 18D0 0
002A 3029 0
002B 2F02 1
002C 0182 1
002D 1304 0
002E 1305 0
002F 2F6E 1
0030 0B82 1
0031 2F00 0
0032 0B83 0
0033 0006 0
0034 0B04 0
0035 0007 0
0036 0805 0
0037 1584 0
0038 1685 0
0039 1004 1
003A 1282 1
003B 1083 1
003C 1A40 1
003D 3033 1
003E 1F90 1
003F 1AD0 1
0040 303F 1
0041 1584 1
0042 1685 1
0043 0590 1
0044 18D0 1
0045 3044 0
0046 1950 1
0047 303F 1
0048 1D90 1
0049 1AD0 1
004A 3049 1
004B 18D0 1
004C 304B 1
004D 1B50 1
004E 302B 1
004F 18D0 1
0050 304F 1
0051 1B50 1
0052 3011 1
0053 3053 1
0054 018B 1
0055 1ED1 1
0056 1ED0 0
0057 2F03 1
0058 0BC1 1
0059 2F8A 0
005A 0BC0 0
005B 2F56 0
005C 0063 0
005D 305C 0
005E 11C0 0
005F 305C 1
0060 11C1 1
0061 305C 1
0062 1CD0 1
0063 2F03 1
0064 0BC1 1
0065 2F8A 0
0066 0BC0 0
0067 2F56 0
0068 0063 0
0069 3068 0
006A 11C0 0
006B 3068 1
006C 11C1 1
006D 3068 1
006E 3056 1
006F 3FFF 1
304013692: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 02FF 1
07FF 31FD 1
308485218: FLASH_READ_A
ADDR DATA ?
-----------
0000 0070 0
0001 2F00 0
0002 0182 0
0003 3FED 0
0004 018B 0
0005 3FEE 0
0006 019A 0
0007 2F80 0
0008 019B 0
0009 2F1C 0
000A 0183 0
000B 3FFE 0
000C 2AFF 0
000D 3054 0
000E 3FED 0
000F 0B81 1
0010 1F91 1
0011 2F05 0
0012 0B80 0
0013 1AD0 0
0014 3013 0
0015 1F90 1
0016 0063 1
0017 3016 1
0018 1180 0
0019 3016 0
001A 1D90 1
001B 18D0 1
001C 301B 1
001D 2F01 1
001E 1950 1
001F 2FFF 0
0020 0C01 1
0021 018B 0
0022 0B81 0
0023 1AD0 0
0024 3023 0
0025 1B50 1
0026 304F 1
0027 2F04 0
0028 0188 1
0029 18D0 0
002A 3029 0
002B 2F02 1
002C 0182 1
002D 1304 0
002E 1305 0
002F 2F6E 0
0030 0B82 1
0031 2F00 0
0032 0B83 0
0033 0006 0
0034 0B04 0
0035 0007 0
0036 0805 0
0037 1584 0
0038 1685 0
0039 1004 0
003A 1282 1
003B 1083 1
003C 1A40 1
003D 3033 1
003E 1F90 1
003F 1AD0 1
0040 303F 1
0041 1584 1
0042 1685 1
0043 0590 1
0044 18D0 1
0045 3044 0
0046 1950 1
0047 303F 1
0048 1D90 1
0049 1AD0 1
004A 3049 1
004B 18D0 1
004C 304B 1
004D 1B50 1
004E 302B 1
004F 18D0 1
0050 304F 1
0051 1B50 1
0052 3011 1
0053 3053 1
0054 018B 1
0055 1ED1 1
0056 1ED0 0
0057 2F03 1
0058 0BC1 1
0059 2F8A 0
005A 0BC0 0
005B 2F56 0
005C 0063 0
005D 305C 0
005E 11C0 0
005F 305C 1
0060 11C1 1
0061 305C 1
0062 1CD0 1
0063 2F03 1
0064 0BC1 1
0065 2F8A 0
0066 0BC0 0
0067 2F56 0
0068 0063 0
0069 3068 0
006A 11C0 0
006B 3068 1
006C 11C1 1
006D 3068 1
006E 3056 1
006F 3FFF 1
315382824: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
0000 0070 2F00 0182 3FED
0004 018B 3FEE 019A 2F80
0008 019B 2F1C 0183 3FFE
000C 2AFF 3054 3FED 0B81
0010 1F91 2F05 0B80 1AD0
0014 3013 1F90 0063 3016
0018 1180 3016 1D90 18D0
001C 301B 2F01 1950 2FFF
0020 0C01 018B 0B81 1AD0
0024 3023 1B50 304F 2F04
0028 0188 18D0 3029 2F02
002C 0182 1304 1305 2F6E
0030 0B82 2F00 0B83 0006
0034 0B04 0007 0805 1584
0038 1685 1004 1282 1083
003C 1A40 3033 1F90 1AD0
0040 303F 1584 1685 0590
0044 18D0 3044 1950 303F
0048 1D90 1AD0 3049 18D0
004C 304B 1B50 302B 18D0
0050 304F 1B50 3011 3053
0054 018B 1ED1 1ED0 2F03
0058 0BC1 2F8A 0BC0 2F56
005C 0063 305C 11C0 305C
0060 11C1 305C 1CD0 2F03
0064 0BC1 2F8A 0BC0 2F56
0068 0063 3068 11C0 3068
006C 11C1 3068 3056 3FFF
337347740: 0000001010010100011101010100101000111010
359606267: 0000001010010100011101010100101000111010
373491436: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0026 0026 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 0282 31FD
378465137: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
383944796: FLASH_READ_A
ADDR DATA ?
-----------
07E0 3FFF 0
07E1 3FFF 0
07E2 3FFF 1
07E3 3FFF 1
07E4 3FFF 1
07E5 3FFF 1
07E6 3FFF 1
07E7 3FFF 1
07E8 3FFF 1
07E9 3FFF 1
07EA 3FFF 1
07EB 3FFF 1
07EC 3FFF 1
07ED 0281 1
07EE 027A 1
07EF 1FFE 0
07F0 0026 0
07F1 0026 1
07F2 3FFF 0
07F3 3FFF 0
07F4 3FFF 1
07F5 3FFF 1
07F6 3FFF 1
07F7 3FFF 1
07F8 1850 1
07F9 3F54 1
07FA 3FFF 1
07FB 3FFF 1
07FC 3FFF 1
07FD 3FFF 1
07FE 0282 1
07FF 31FD 1
388416569: FLASH_WRITE_A
ADDR -W1- -W2- -W3- -W4-
------------------------
07EC 3FFF 0281 027A 1FFE
07F0 0026 0026 3FFF 3FFF
07F8 1850 3F54 3FFF 3FFF
07FC 3FFF 3FFF 0282 31FD
There was a slightly problem while I was exporting the TXT file for processing, apparently the LAP-C program didn't like exporting a 20GB file and crashed before finishing ;D
So I'm not sure if the file contains all the commands and all the messages. The program doesn't display what percentage of the file it has processed, so I'm not sure how much data was still remaining to be exported.
I will assume that VDD/VPP = 3.3V will be ok for this. Then I just can connect the input/output of the host MCU to padauk IC directly.
First test result:I'd try 3.3V on VDD rather than VPP.
VPP 3.3V seems NOT to work. IC starts exactly same as when VPP is not applied (52.40ms till blink out starts on PA.3)
Need to add transistor now to toggle 5V.
Great job! The IC seems to be sampling the data pin on falling edge, then, is that right? While it seems the incoming data must be sampled on the rising edge.
>A5A5A5A60
<AA1
>? ? ?
<? ? ?
Not there yet ... in command mode it looks like I can sample either on rising or on falling edge.Sure.
Could you describe the READ command (0x60) in detail?
Enter read mode:
>A5A5A5A61 (36 bits)
<1010 1010 0001 0 (13 bits)
Voltage is on VDD now raised to 4.3V
Read word:
>address (13 bits)
<word (14 bits)
>unknown, seemingly always 1 (1 bit)
Note command seems to be 61 instead of 60, or at least that what I got from the 200 MHz dump, and from previous using the "sticky" (ie one if it's high on either falling or rising) approach.
>A5A5A5A71 (36 bits)
<1010 1010 0001 0 (13 bits)
VPP is raised to 8.3V
<word1 (14 bits)
<word2 (14 bits)
<word3 (14 bits)
<word4 (14 bits)
<address (13 bits)
<000000000 (padding? not sure about the direction of this one - 9 bits)
<000000000 (padding? not sure about the direction of this one - 9 bits)
Write command format, in case you want to try it:Code: [Select]>A5A5A5A71 (36 bits)
<1010 1010 0001 0 (13 bits)
VPP is raised to 8.3V
<word1 (14 bits)
<word2 (14 bits)
<word3 (14 bits)
<word4 (14 bits)
<address (13 bits)
<000000000 (padding? not sure about the direction of this one - 9 bits)
Write command format, in case you want to try it:Code: [Select]>A5A5A5A71 (36 bits)
<1010 1010 0001 0 (13 bits)
VPP is raised to 8.3V
<word1 (14 bits)
<word2 (14 bits)
<word3 (14 bits)
<word4 (14 bits)
<address (13 bits)
<000000000 (padding? not sure about the direction of this one - 9 bits)
This is next I will try... (tomorrow maybe).
> VPP is raised to 8.3V
What I found out... READ is also working with VPP 8.3V and VPP 12.0V so maybe just 12V VPP is needed :-) ?
JS
Could you please try also with 0x61? I wonder why I'm getting that if it's 0x60.
That seems correct. It looks like the writer itself is using 0x67 at some point for reading in place of 0x61 and 0x60.Could you please try also with 0x61? I wonder why I'm getting that if it's 0x60.
OK, tested 0x60, 0x61, 0x62, ... 0x6F ... all same result: VALID READ :)
=> seems command is just 0x6 and then 4 dummy clocks are used before switching mode (the 4 clocks are really needed, I thought maybe preamble 28 bit + 4 bit command = nice 32 bit... but nope)
JS
FIRST BIG SUCCESS...
After some try and error I completed Level1 ^-^ ^-^ : CLOCK is ALWAYS sent from WRITER.
- a command is sent with preamble 0xA5A5A5A followed by 8 bit COMMAND
- after last bit from command was sent DATA switches directions
- IC sends back 0xAA and 4 bit status (maybe something like this: b0001 = ok, b0000 = error), clock must be supplied by WRITER
This only works with VPP > 5.5 V.
JS
EDIT: 3.3V was used for VDD.
I tried to replicate your experiment with the 0x60 command (minus powercycling I just switch it on), but I only have blank chips.
They dont respond at all.
Could you try with a blank chip?
void PADAUK_write_bit (unsigned char b) {
digitalWrite(PA6_data, b);
delayMicroseconds(1);
digitalWrite(PA3_clk, 1);
delayMicroseconds(1);
digitalWrite(PA3_clk, 0);
delayMicroseconds(1);
}
unsigned char PADAUK_read_bit () {
digitalWrite(PA3_clk, 1);
delayMicroseconds(1);
unsigned char b = digitalRead(PA6_data);
digitalWrite(PA3_clk, 0);
delayMicroseconds(1);
return b;
}
void PADAUK_command(unsigned char cmd) {
//A
PADAUK_write_bit(1);
PADAUK_write_bit(0);
PADAUK_write_bit(1);
PADAUK_write_bit(0);
//5
PADAUK_write_bit(0);
PADAUK_write_bit(1);
PADAUK_write_bit(0);
PADAUK_write_bit(1);
//A
PADAUK_write_bit(1);
PADAUK_write_bit(0);
PADAUK_write_bit(1);
PADAUK_write_bit(0);
//5
PADAUK_write_bit(0);
PADAUK_write_bit(1);
PADAUK_write_bit(0);
PADAUK_write_bit(1);
//A
PADAUK_write_bit(1);
PADAUK_write_bit(0);
PADAUK_write_bit(1);
PADAUK_write_bit(0);
//5
PADAUK_write_bit(0);
PADAUK_write_bit(1);
PADAUK_write_bit(0);
PADAUK_write_bit(1);
//A
PADAUK_write_bit(1);
PADAUK_write_bit(0);
PADAUK_write_bit(1);
PADAUK_write_bit(0);
//6
PADAUK_write_bit(0);
PADAUK_write_bit(1);
PADAUK_write_bit(1);
PADAUK_write_bit(0);
//0
PADAUK_write_bit(0);
PADAUK_write_bit(0);
PADAUK_write_bit(0);
PADAUK_write_bit(0);
pinMode(PA6_data, INPUT_PULLUP);
delayMicroseconds(1);
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
PADAUK_read_bit();
pinMode(PA6_data, OUTPUT);
digitalWrite(PA6_data, 0);
}
AFAIK that extra clock is needed by all commands. I'm not sure how you are being able to use the read with 12 bit reply in place of the 13 as the scope shows.
Today, I made a first step to inefficently compiling a small subset of C to Padauk asm code. The current version is very restricted and generates very inefficient code; it is untested.
There is no assembler / linker support, so the resulting .asm file has to be assembled in other ways.
[…]
Code in svn at https://svn.code.sf.net/p/sdcc/code/branches/pdk/sdcc, use -mpdk14 to target Padauk (despite the name, the set of instructions emitted is part of the common subset of the Padauk instruction sets).
On the second day, wrt. completeness of implementation of the C standard, this has now far surpassed Mini-C.
Noticeable remaining restrictions:
* Variables can only reside in RAM, not in code space
* Global and static variables are not initialized.
* No floating-point or bit-fields.
* Functions can return at most 2 bytes (i.e. no long or long long).
* Multiplicative operators are not supported.
* Functions are not reentrant.
* No support for variable arguments.
* No standard library.
* struct / union cannot be assigned, passed as arguments or returned.
* No compoundliterals.
* No access to I/O from C.
There is no glue to connect this to assembler / linker yet, so the only useable output is asm code.
The generated asm code is still very inefficient. I will look into improving that a bit soon.
Philipp
A first usable version of the sampling software for my ADC4 board is done with the 1 GB RAM.
VPP is 7.5V during read and ~10.5V during writing. This seems rather low. Are the ADCs calibrated correctly or may there be some offset/gain error?
VDD is 6V during programming, 4V during reading and 2V for verification. I would guess that it should be ok to keep VDD at 5V if you don't want to verify all corner cases.
To understand the protocoll it will be necessary to extract the logs using an SPI protocol analyzer. I will try to use PulseView for that. I am using it for the first time. It looks nice, but seems to be lacking some functionality. For example, how is it possible to display voltage values of specific data points`?
Not to nit-pick, but it seems there is a lot of cross talk and bouncing going on. Also clock and data seem to be out of phase in some areas.
Don't if that is really the case or if the data for the otp is really that different from the pfs154.
Have you tried to sample test signals?
Ie clock of a micro on one channel and look what the rest does?
You are right, cross talk is terrible. But I think the recording should be very accurate regarding the timing and the phase of the signals.
Have you checked what the actual VPP is, instead of 10.5V? I suppose it is 12V or higher?
Please find attached my notes on analysing the programming sequence from Frank.
The different programming voltages shouldn't be a problem. The circuit diagram from @oPossum looks good, the ALM2402 can drive up to 400 mA, so maybe no external transistor amplifier is even needed. But it has only a gain bandwidth of 600 kHz, maybe would be good to use some additional 4051 for the high frequency data lines. Could be all controlled with a cheap Arduino nano, and a simple Python script to control it and send the programming file over serial port.
I wonder why they do all these tests. I guess they don't do much tests when they produce the ICs? So far I've used about 20 PMS150C for testing, programming little things etc. One IC was not programmable. Might be a good idea if a DIY programmer would do all the verifies at different voltage levels etc. as well.
I'm not sure using a STM32 is the best option if it's designed to be hand assembled by hobbyists. TSOP aren't particularly friendly.
The STM32 does only output 3.3V. It might work, but would be better to use a 4053, costs only 35 cent (https://www.digikey.de/short/p7q44b) (probably cheaper at LCSC) and has 3 switches, with which you could select VDD or GND for the data lines. Maybe there are even low cost multi channel voltage converters, but you can get the 4053 everywhere. If it works with 5 V for VDD, then at least you don't need extra ICs when the IC sends data back, because the IOs of the STM32 are 5 V tolerant. But they might might not like the 6.5 V we've seen with the PMS150C. With your current schematic it is possible to set a higher voltage on VDD. Always good to design a circuit in a way that no matter how buggy the firmware is, the hardware doesn't get destroyed :)
from datasheet of STM32F072: 5 volt tolerant pin VMax = VDDIO + 4.0 V, VDDIO = 3.3V ==> absolute maximum is 7.3 volt.
So should be no problem. Right ?
I think something like attached would work perfectly, but might be not needed, if 5 V for VDD works.I think your solution with the 4053 is a good idea.
But the 5V supply is directly from the VUSB. There are often polyfuses in the USB host port, wire resistance,... in the way, so VUSB is often more like 4.6V oder 4.5V in the end. While true 5V might work, I fear the lower real voltage won't.
I'm not sure how to enable/disable individual pins of the output level shifter to stop outputting 0 or 1 when the pins are in input mode for writer. ? ? ?
BTW: @tim_ (cpldcpu): Do you think it is ok to claim that this all your own work, based on captures from FrankBuss?
from page 2: > All of this work is solely based on analyzing datalogs of the programming sequence as provided here: https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2096917/#msg2096917 (https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2096917/#msg2096917)
Maybe next time you could also mention the work of the eevblog forums community members.
Hi,
When I checked STM32F072 was cheapest option:
LCSC:
STM32F072C8T6: 1+ €1.2514, 10+ €1.2096, 100+ €1.0841
STM32F103C8T6: 1+ €1.8233, 10+ €1.3186, 30+ €1.2260
PS: With a 4051, and switching to pullup, pulldown, VDD and GND, and in combination with regulated VDD and using the STM32 pins in analog input mode, it wouldn't be difficult to implement the open/close functionality in software.
I update the wording on the slides a bit to avoid further confusion.
Adding several 4051 will use a lot of board space which I wanted to keep small initially.I can understand that.
Hi,
When I checked STM32F072 was cheapest option:
LCSC:
STM32F072C8T6: 1+ €1.2514, 10+ €1.2096, 100+ €1.0841
STM32F103C8T6: 1+ €1.8233, 10+ €1.3186, 30+ €1.2260
You do know that a whole board with STM32F103C8T6 can be had for $1.60 shipping included?The STM32F103C8T6 doesn't have DACs, the STM32F072 has. You'd need to use PWM with feedback which makes reaching the desired voltages much slower.
How about an Arduino based programmer? :DThat would be much easier, easily built in a breadboard and protoboard with only DIP parts, and it's probably the way I'm gonna try doing this.
You do know that a whole board with STM32F103C8T6 can be had for $1.60 shipping included?The STM32F103C8T6 doesn't have DACs, the STM32F072 has. You'd need to use PWM with feedback which makes reaching the desired voltages much slower.
FWIW I started building and successfully tested a charge pump / PWM based voltage supply for both Vdd and Vpp with feedback by ADC on an arduino.
Its to slow to work without transistors to switch the supplies on/off but otherwise works quite nicely. Even with a simple breadboard.
A charg pump or boost converter? Note that in both cases your could use a (software-) PD controller to speed up the step response significantly.
Initializing...
DeviceID: A16 Vpp Standby: 376
Dumping memory...
Vpp read mode: 547
0000: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0010: 01AA 0155 1FFF 1FFF 1A5A 15A5 1FFF 1FFF 1A5A 15A5 1A5A 15A5 1FFF 1FFF 1FFF 1FFF
0020: 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5
0030: 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5 1A5A 15A5
0040: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0050: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0060: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0070: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0080: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0090: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
00A0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
00B0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
00C0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
00D0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
00E0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
00F0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0100: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0110: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0120: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0130: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0140: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0150: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0160: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0170: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0180: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0190: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
01A0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
01B0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
01C0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
01D0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
01E0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
01F0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0200: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0210: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0220: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0230: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0240: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0250: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0260: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0270: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0280: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0290: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
02A0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
02B0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
02C0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
02D0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
02E0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
02F0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0300: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0310: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0320: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0330: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0340: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0350: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0360: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0370: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0380: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
0390: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
03A0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
03B0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
03C0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
03D0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
03E0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF
03F0: 1FFF 1FFF 1FFF 1FFF 1FFF 1FFF 018A 1FFF 1FFF 1FFF 1FFF 1FFF 0FFF 1FFF 1FFF 0FFD
Writing to memory...
Vpp initial: 541 PWM: 10
Vpp write mode: 792 PWM: 42
Vpp after writing: 793
Vpp off: 396
The HT7991 that you have used, can boost to 12V, it can not make 15V, simply replace it with MT3608, it can go upto 28v and it's super cheap ;)
Just a couple suggestions on the pcb:
- maybe leave unpopulated target footprints on the back, so we can program the most common parts by holding against those.
- maybe add a few pin connectors to the sides of the usb for mechanical support. This would allow target sockets to be firmly mounted on a shield-like pcb on top/bottom of the programmer.
My plan was to use some of this SOT to DIP sockets and connect jumper wires for different types easily:Yes, I think something like this is cheap & conveniant and much more reliable than just a footprint to hold the ic against.
https://detail.tmall.com/item.htm?id=522621435705 (https://detail.tmall.com/item.htm?id=522621435705)
https://www.aliexpress.com/item/SOP28-Adapter-Socket-DIP28-to-SOP16-SOP20-300mil-Chip-Programmer-20pin-Feet/32900927477.html (https://www.aliexpress.com/item/SOP28-Adapter-Socket-DIP28-to-SOP16-SOP20-300mil-Chip-Programmer-20pin-Feet/32900927477.html)
BTW, as I'm mostly interested in the Padauks in SOT-23-6, does anybody know of a cheap SOT-23-6 adapter? The cheapest I could find were these
https://www.aliexpress.com/item//32851813673.html (https://www.aliexpress.com/item//32851813673.html)
https://www.aliexpress.com/item//32811278237.html (https://www.aliexpress.com/item//32811278237.html)
Regarding the IC adapters, if the chips can be in circuit programmed, then they are useless ;DI don't think you want 10V programming voltage anywhere on your regular circuit.
Regarding the IC adapters, if the chips can be in circuit programmed, then they are useless ;DI don't think you want 10V programming voltage anywhere on your regular circuit.
I don't think you want 10V programming voltage anywhere on your regular circuit.hopefully the 10v is on the reset pin and it can be isolated from other parts of the circuit ;)
Thanks for your findings and implementation. :clap:
In fact it matches my experiments but for some reason it does not work on PFS154 yet. After I converted my project to support also the small 13 bit devices I was able to program PMC150 immediately like you did.
So only the shared DAT pin for input and output on PFS154 still troubles me a bit.
EDIT: What you call "Device-ID" seems to be the "ACK" we seen on PFS154.
on PFS154:
after a command is sent you need to send some dummy clocks (4) for the IC to process the command
-> maybe some more clocks are required on PMC150 which you call "dummy write"
then direction changes and and ACK is sent back (12 bit): 0xAA1
-> maybe on PMC150 it is 0xA1
then again a dummy clock is required before you can start sending data
-> maybe the "6" is just garbage since only 4 dummy clocks are needed.
Regarding the pdf: on page 18 you write that the data is clocked out after the first write cycle and believe that its verification data.
I dont think so. The data comes from the internal shift register being used for SPI. The default value seems to be the device ID, after that the bits you shifted in are simply shifted out. Its very unlikely that this is intended for verification purposes.
I think it could be very helpful to take an analog log of the PFS154 writes sequence. Most likely it will also be possible to deduce the write direction from the analog voltages.
Frank, do you think you have a chance to do this? If you don't have any PFS154 I could send some to you.
Initializing...
372 400 425 449 472 491 510 527 543 ACK: FAA1
DeviceID: 0 Vpp Standby: 373
Dumping memory...
372 400 425 449 472 492 510 527 543 ACK: 1AA1
Vpp read mode: 560
0000: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0010: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0020: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0030: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 34BF 3B4F 300F 300F 3FFF 3FFF 3FFF 3FFF
0040: 34BF 3B4F 300F 300F 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0050: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0060: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0070: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0080: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0090: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0100: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0110: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0120: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0130: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0140: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0150: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0160: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0170: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0180: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0190: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0200: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0210: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0220: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0230: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0240: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0250: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0260: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0270: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0280: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0290: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0300: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0310: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0320: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0330: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0340: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0350: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0360: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0370: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0380: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0390: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0400: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0410: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0420: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0430: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0440: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0450: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0460: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0470: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0480: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0490: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0500: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0510: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0520: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0530: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0540: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0550: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0560: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0570: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0580: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0590: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0600: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0610: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0620: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0630: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0640: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0650: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0660: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0670: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0680: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0690: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0700: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0710: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0720: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0730: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0740: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0750: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0760: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0770: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0780: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0790: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 0282 025A 1FFE
07F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
Writing to memory...
374 402 428 453 476 496 515 532 ACK: FAA1
Vpp initial: 536 PWM: 9
553 563 572 Vpp write mode: 595 PWM: 13
Vpp after writing: 580
Vpp off: 312
I think it could be very helpful to take an analog log of the PFS154 writes sequence. Most likely it will also be possible to deduce the write direction from the analog voltages.
Frank, do you think you have a chance to do this? If you don't have any PFS154 I could send some to you.
Yes, I can do this. I have only PMS150C and PMS154B, but I guess a flash version can be very different. If you want to send me a few, my address is on my impressum page: http://www.frank-buss.de/impressum.html (http://www.frank-buss.de/impressum.html) Would be faster than when I'm ordering it at lcsc, if you have already some. How many signals should I sample? Just asking in case I need to solder the second board, for a full 8 channel version of my ADC.
The circuit diagram from @oPossum looks good, the ALM2402 can drive up to 400 mA, so maybe no external transistor amplifier is even needed. But it has only a gain bandwidth of 600 kHz, maybe would be good to use some additional 4051 for the high frequency data lines.
Initializing...
DeviceID: E06 Vpp Standby: 5.4
DeviceID is match to:PMS154C
Dumping memory...
Vpp read mode: 7.7
0000: 37E8 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0010: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0020: 1A5A 15A5 3FFF 3FFF 1A5A 15A5 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0030: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0040: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0050: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0060: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0070: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0080: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0090: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0100: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0110: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0120: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0130: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0140: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0150: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0160: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0170: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0180: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0190: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0200: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0210: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0220: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0230: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0240: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0250: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0260: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0270: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0280: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0290: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0300: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0310: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0320: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0330: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0340: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0350: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0360: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0370: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0380: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0390: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0400: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0410: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0420: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0430: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0440: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0450: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0460: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0470: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0480: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0490: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0500: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0510: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0520: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0530: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0540: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0550: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0560: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0570: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0580: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0590: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0600: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0610: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0620: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0630: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0640: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0650: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0660: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0670: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0680: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0690: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0700: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0710: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0720: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0730: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0740: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0750: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0760: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0770: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0780: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0790: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 2F1C 018B 0183 0191 1950 2FC3 0190 37E8
07F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 026A 3FFF 3FFF 32FF 3FFF 3FFF 3FFF 3FFF 3FFF 1F5D
Writing to memory...
Vpp initial: 7.6 PWM: 10
Vpp write mode: 11.2 PWM: 43
Vpp after writing: 11.1
Vpp off: 5.5
Curiously a lot of memory cells were already written on the fresh device. See dump below. I only wrote to 0x20-0x27. So even at 0x00 there was a prior value programmed. Ideas anyone?
Nop being all zeros seems like a nice way to give an OTP part a couple extra lives. Embedding relocation in the programmer code would be awesome.Curiously a lot of memory cells were already written on the fresh device. See dump below. I only wrote to 0x20-0x27. So even at 0x00 there was a prior value programmed. Ideas anyone?
This looks like the factory testing routine. Might only be present in PMS devices (tested) compared to PMC devices (non tested). PADAUK says PMS devices = "higher yield" in production ... of course if they already check for bad ICs ;), PMC = "better value" (price cheaper since no factory test and you might get several bad ICs)
First instruction is a GOTO to the end of program area where a simple program is stored. I analyzed this program already: https://github.com/free-pdk/fppa-pdk-documentation/blob/master/SpecialCodeFoundInPMS154B.txt
Basically it is an endless loop mirroring the input of PA.5 inverted on PA4,PA.3 and PA.2 ==> WRITER could detect presence of good IC by setting PA.5 High/Low and checking if PA.4,PA.3,PA.2 output inverted signal (we saw this as continuous small spikes from time to time when WRITER is idle)
Later when you program a user program a NOP is placed at first instruction (NOP = all bits 0, like this you can overwrite the old value). The start of the real user program will be at next instruction (I saw this when I dumped a programed 154C).
JS
Initializing...
DeviceID: AA1 Vpp Standby: 5.3 V
DeviceID is match to: PFC154
Dumping memory...
Vpp read mode: 7.7 V
0000: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0010: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0020: 1FFF 0FFF 0FFF 0FFF 1FFA 0182 05E0 0E80 1A5A 0003 0000 0000 1A5A 0004 0000 0000
0030: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0040: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0050: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0060: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0070: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0080: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0090: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0100: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0110: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0120: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0130: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0140: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0150: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0160: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0170: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0180: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0190: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0200: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0210: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0220: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0230: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0240: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0250: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0260: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0270: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0280: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0290: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0300: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0310: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0320: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0330: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0340: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0350: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0360: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0370: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0380: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0390: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0400: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0410: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0420: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0430: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0440: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0450: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0460: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0470: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0480: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0490: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0500: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0510: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0520: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0530: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0540: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0550: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0560: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0570: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0580: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0590: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0600: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0610: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0620: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0630: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0640: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0650: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0660: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0670: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0680: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0690: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0700: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0710: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0720: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0730: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0740: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0750: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0760: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0770: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0780: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0790: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 0282 025A 1FFE
07F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
Erasing device...
Erase init response: 0AA1
Vpp initial: 7.6 V PWM: 9
Vpp erase mode: 8.8 V PWM: 15
Vpp after erase: 8.9 V PWM: 15
Writing to memory...
Vpp initial: 7.8 V PWM: 10
Vpp write mode: 8.5 V PWM: 15
Vpp after writing: 8.5 V
Vpp off: 4.5 V
Hi,
So this looks indeed like part of the OTP_ID. You can find the defines for OTP_ID in the IC specific files in "INC_PDK" folder of the IDE:
OTP_ID DATA from IC after command phase:
PMC150: 0B80
PMS150: 0B80
PMS150B: 1E01
PMS150C: 2A16 -> A16 (OK)
PMS154: 2A06
PMS154B: 2C06
PMS154C: 2C06 -> E06 (maybe include file is wrong or the read was not correct)
PFS154: 2AA1 -> AA1 (OK)
Initializing...
DeviceID: AA1 Vpp Standby: 5.3 V
DeviceID is match to: PFC154
Dumping memory...
Vpp read mode: 7.7 V
0000: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0010: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0020: 1A5A 0001 3FFF 3FFF 1A5A 0002 3FFF 3FFF 1A5A 0003 3FFF 3FFF 1A5A 0004 3FFF 3FFF
0030: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0040: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0050: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0060: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0070: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0080: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0090: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
00F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0100: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0110: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0120: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0130: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0140: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0150: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0160: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0170: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0180: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0190: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
01F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0200: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0210: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0220: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0230: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0240: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0250: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0260: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0270: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0280: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0290: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
02F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0300: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0310: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0320: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0330: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0340: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0350: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0360: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0370: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0380: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0390: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
03F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0400: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0410: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0420: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0430: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0440: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0450: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0460: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0470: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0480: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0490: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
04F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0500: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0510: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0520: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0530: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0540: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0550: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0560: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0570: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0580: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0590: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
05F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0600: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0610: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0620: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0630: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0640: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0650: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0660: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0670: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0680: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0690: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
06F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0700: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0710: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0720: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0730: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0740: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0750: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0760: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0770: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0780: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
0790: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07A0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07B0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07C0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07D0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
07E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 0282 025A 1FFE
07F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
Erasing device...
Erase init response: 0AA1
Vpp initial: 7.9 V PWM: 10
Vpp erase mode: 8.7 V PWM: 14
Vpp after erase: 8.7 V PWM: 14
Writing to memory...
Vpp initial: 7.7 V PWM: 10
Vpp write mode: 8.7 V PWM: 17
Vpp after writing: 9.0 V
Vpp off: 4.6 V
Nop being all zeros seems like a nice way to give an OTP part a couple extra lives. Embedding relocation in the programmer code would be awesome.Actually the IDE has some support for it. See the file PADAUK_Tool/0.84/Help/CHS/MultPro.html . Unfortunately only available in Chinese, but the translation with Chrome is fairly good. It describes how to use .dc -1/0, .virtual and .checksum to burn an OTP IC virtually multiple times.
Ahaha, it's a bug in the chip. When I change words 3 and 4 to 0x3fff, all information is written in the first iteration. Probably there is some kind of internal issue when too many bits have to be written at once.
This explains why only two of four words are written at the same time in the official programmer.
Hi,
So this looks indeed like part of the OTP_ID. You can find the defines for OTP_ID in the IC specific files in "INC_PDK" folder of the IDE:
OTP_ID DATA from IC after command phase:
PMC150: 0B80
PMS150: 0B80
PMS150B: 1E01
PMS150C: 2A16 -> A16 (OK)
PMS154: 2A06
PMS154B: 2C06
PMS154C: 2C06 -> E06 (maybe include file is wrong or the read was not correct)
PFS154: 2AA1 -> AA1 (OK)
Exellent find! The pieces of the puzzle are coming together now. :)
The mismatch between C06 and E06 is strange. The deviating bit is in the middle of the sequence, so it does not seem too likely that it glitched or flipped.
Ahaha, it's a bug in the chip. When I change words 3 and 4 to 0x3fff, all information is written in the first iteration. Probably there is some kind of internal issue when too many bits have to be written at once.
This explains why only two of four words are written at the same time in the official programmer.
The captures from writing PFS154 did not show that. The flash was written in one big go without writing some pages multiple times.
JS
BTW: "DeviceID is match to: PFC154" ==> should be PF*S*154 ;-)
I thought this came up somewhere up in the thread? Well anyways. The issue with not being able to write many zeros at the same time could be a current limitation. The embedded MTP memory is probably written with hot carrier injection or another mechanism that requires a lot of current. The total current consumption during writing depends on the numbers of zeros written. I should maybe try to use a transistor to control VDD instrad of a GPIO...
I thought this came up somewhere up in the thread? Well anyways. The issue with not being able to write many zeros at the same time could be a current limitation. The embedded MTP memory is probably written with hot carrier injection or another mechanism that requires a lot of current. The total current consumption during writing depends on the numbers of zeros written. I should maybe try to use a transistor to control VDD instrad of a GPIO...
Interesting...
I was able to READ/ERASE with VDD coming from STM32 (3.3V, smallish current) and it worked nice. However writing only sometimes changed some bits.
When I added a transistor to switch VDD (basically wiring resistor to VDD supplied from external PSU and using mosfet to pull it to ground... I know but I had it handy) situation got worse.
I could not write anything anymore. However READ and ERASE still worked.
My experiments with PFS154:
* any VPP 5.7 - 12V and any VDD 2.4 - 7V READ/ERASE works
* WRITE worked only (a little bit) when VDD was connected to MCU (3.3V), it also stopped working with 3.3V when using the transistor.
So maybe my current limiting resistor needs to be changed. Can't wait to try later today :-)
JS
I think it could be very helpful to take an analog log of the PFS154 writes sequence. Most likely it will also be possible to deduce the write direction from the analog voltages.
Frank, do you think you have a chance to do this? If you don't have any PFS154 I could send some to you.
I think it could be very helpful to take an analog log of the PFS154 writes sequence. Most likely it will also be possible to deduce the write direction from the analog voltages.
Frank, do you think you have a chance to do this? If you don't have any PFS154 I could send some to you.
Thanks, I got the ICs. Here (http://www.frank-buss.de/tmp/dump-pfs154.zip) is a dump of the PFS154. I added a lot of 0x00 and 0xff to see if the programmer does something special for long sequences. The test project with source code and PDK file is included. This is programming an already programmed chip with the same data, but in the display I could read an erase step, so I guess it is the same for an empty chip. But I can do another test with an empty chip, if necessary.
Signals:
CH1 = PA3
CH2 = PA5
CH3 = PA6
CH4 = VDD
Still a lot of crosstalk. My scope shows a better signal. But I think I can reduce this a bit with a better decoupling of the reference voltages and better shielding of the test cables.
There was a bit of progress on the software side. The compiler is now mostly working (i.e. except for a few corner cases it should just accept valid ISO C17 code and generate correct asm for it), and the generated asm looks okayish, though there is further potential for optimization.
I've written a "Hello, world!" for the PFS154 (https://github.com/free-pdk/sdcc-pdk-code-examples/tree/master/hello-pfs154). The asm generated by SDCC for it looks correct, but I didn't really check the binary code yet (and the assembler is still quite new).
Philipp
Very nice! I compiled SDCC from your pdk branch and compiled this example. It seems that main code and the initiliaztion code are both relocated to zero? Is that still a bug or is an additional linker-file required?
Kind of both: One could use a linker file (or the --code-loc option), but the default for --code-loc needs to be changed, so it just works for the common case. However, there also are a few other linker / compiler-linker interface issues that need to be fixed.
Philipp
/*
Blinky on PA.0
*/
#include <stdbool.h>
#include <stdio.h>
volatile int counter;
__sfr __at(0x03) clkmd;
__sfr __at(0x04) inten;
__sfr __at(0x05) intrq;
__sfr __at(0x10) pa;
__sfr __at(0x11) pac;
__sfr __at(0x1c) tm2c;
__sfr __at(0x17) tm2s;
__sfr __at(0x09) tm2b;
unsigned char _sdcc_external_startup(void)
{
clkmd = 0x34; // Use IHRC / 2 = 8 Mhz for system clock
clkmd = 0x30; // Disable ILRC, watchdog
return 0; // perform normal initialization
}
void main(void)
{
pac = 0x01; // PA.0=output
for (;;) {
counter=30000;
while (--counter);
pa=0x00;
counter=30000;
while (--counter);
pa=0x01;
}
}
:200002000113002F800B002F002880171830002F800300120830000C01286A006B00820151
:020002000030CC
:020000000C30C2
:20000400342F830B302F830B7A007A00012F910B302F800B752F810B80128110800F810EE3
:1C002400002A1830002F900B80128110800F810E002A2830012F900B10307A003C
:00000001FF
Kind of both: One could use a linker file (or the --code-loc option), but the default for --code-loc needs to be changed, so it just works for the common case. However, there also are a few other linker / compiler-linker interface issues that need to be fixed.
Philipp
Is there any easy workaround?
I'd prefer not to use the padauk tools right now for several reasons:This is just not correct. The tools do compile fine for me.
- The tools to decode pdk files from "freepdk" do not compile.
(who is maintaining this, btw. I added an issue)Read this thread and you know who are maintainers.
- I would like omit the oscillator calibration code for now as this only adds to complexity in the programmer.
- Out of principle, to avoid IP contamination.
While I consider free hardware to be a good thing, there is still a difference. Richard Stallman draws the line between stuff that is supposed to be changed by the user (updateable programs, firmware, FPGA configuration) and and stuff that isn't (e.g. a ROM in a device), which seems to make sense to me.- Out of principle, to avoid IP contamination.
This is the most funny thing you ever posted here. You want to avoid IP contamination?? How do you plan to "avoid" the IP-Core running in the PADAUK IC?
If this really is your concern then for sure you should go with RISC-V.
Compiling with --code-loc 0x0011 or so might help. Worst case one could manually fix the jump targets in the binary. But I don't consider the sdcc-based toolchain ready yet. Work on linker integration has just started. There are probably bugs in the compiler and assembler, many of which will probably not be found before regression testing on the yet-to-be-written-and-ntegrated uCsim-based simulator is in place.
Philipp
;--------------------------------------------------------
; Blinky for Padauk PFS154C
; Based on asm code generated from blinky.c by SDD
;
; File Created by SDCC : free open source ANSI-C Compiler
; Version 3.8.6 #10883 (Linux)
;--------------------------------------------------------
.module blinky
.optsdcc -mpdk14
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _main
.globl _tm2b
.globl _tm2s
.globl _tm2c
.globl _pac
.globl _pa
.globl _intrq
.globl _inten
.globl _clkmd
.globl _counter
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
.area RSEG (ABS)
.org 0x0000
_clkmd = 0x0003
_inten = 0x0004
_intrq = 0x0005
_pa = 0x0010
_pac = 0x0011
_tm2c = 0x001c
_tm2s = 0x0017
_tm2b = 0x0009
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area DATA
_counter::
.ds 2
;--------------------------------------------------------
; overlayable items in ram
;--------------------------------------------------------
;--------------------------------------------------------
; Stack segment in internal ram
;--------------------------------------------------------
.area SSEG
__start__stack:
.ds 1
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area DABS (ABS)
;--------------------------------------------------------
; interrupt vector
;--------------------------------------------------------
.area HOME
__interrupt_vect:
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME
.area GSINIT
.area GSFINAL
.area GSINIT
.area PREG (ABS)
; .area CODE
.org 0x00
__sdcc_program_startup:
goto _main
; return from main will return to caller
;--------------------------------------------------------
; code
;--------------------------------------------------------
.org 0x10
; -----------------------------------------
; function main
; -----------------------------------------
_main:
mov a, #0x78
mov _clkmd, a
mov a, #0x01
mov _pac, a
00108$:
mov a, #0x30
mov _counter+0, a
mov a, #0x75
mov _counter+1, a
; blinky.c: 35: while (--counter);
00101$:
dec _counter+0
subc _counter+1
mov a, _counter+0
or a, _counter+1
ceqsn a, #0x00
goto 00101$
; blinky.c: 36: pa=0x00;
mov a, #0x00
mov _pa, a
; blinky.c: 38: counter=30000;
mov a, #0x30
mov _counter+0, a
mov a, #0x75
mov _counter+1, a
; blinky.c: 39: while (--counter);
00104$:
dec _counter+0
subc _counter+1
mov a, _counter+0
or a, _counter+1
ceqsn a, #0x00
goto 00104$
; blinky.c: 40: pa=0x01;
mov a, #0x01
mov _pa, a
goto 00108$
00110$:
; blinky.c: 42: }
ret
Guys, this is getting too much for me. JS, you may need to think twice before writing angry responses on the internet.
Regarding the issue with compiling the toolchain: I put into the issue on github what I know. I tried two different toolchains on two operating systems and got the same issue. The root cause is not apparent to me now, that's why I opened an issue instead of a pull request. OSS is not about "do everything on your own", that's just very inefficient.
Regarding IP contamination, you may want to read the link about "clean room implementation" that I posted earlier. I agree that it is unlikely to run into issues with Padauk, but in the end it should be my own choice to follow clean processes.
Btw, got a blinky working now on the PFS154 with the OSS toolchain (SDASPDK), and an arduino based programmer. Still extremely hacky.
And there is indeed some risk of "IP contamination": AFAIK, Mini-C adds some of its own code into the resulting program. Many compilers,like GCC or SDCC have a "linker exception" in the license for their library, so the resulting program is not affected by the library license. I din't notice something similar in Mini-C yet (but maybe I just didn't check closely enough). On the other hand, maybe whatever Mini-C adds is unsubstantial enough to not affect the license of the wholeprogram. But that might depend on jurisdiction.
Philipp
JS, you need to chill out.
I will take a break from this forum for now.
I'd prefer not to use the bilnky from tim_ right now for several reasons:
A general issue with SDASPDK: It seems all adress calculation for the instruction memory are based on bytes, not words. Therefore branch targets are off by a factor of two. Or am I missing something?
GOTO _CALIBRATION ;jump to calibration code, will be overwritten with NOP after calibration
GOTO _CALIBRATION ;jump to calibration code, will be overwritten with NOP after calibration
How would one overwrite or otherwise change instructions?
A nop is all-zero. When writing PROM, a 1 can be changed to 0 any time (a few years ago, in a different device, a bug was discovered after PROMs had been programmed - so I had to come up with a patch that only flips 1 bits to 0).
A nop is all-zero. When writing PROM, a 1 can be changed to 0 any time (a few years ago, in a different device, a bug was discovered after PROMs had been programmed - so I had to come up with a patch that only flips 1 bits to 0).
You're changing an OTP device's ROM via software after calibration?
XOR PA,A is only supported by few devices.
Philipp
_CALIBRATION_V1:
SET1 PAC,5 ;PA.5 as output, rest as input => this pin should exist on all devices, same as RESET/ICVPP pin
MOV A,0
_CAL_MAIN_LOOP:
T1SN PA.6 ;read bit from PA.6, increment IHRCR when low. Needs to be low for only one clock cycle!
ADD A,1
SET1 PA,5 ;output one clock cycle
SET0 PA,5
MOV IHRCR, A ;write current A value to IHRCR tuning register
GOTO _CAL_MAIN_LOOP
_CALIBRATION_V2:
SET1 PAC,5 ;PA.5 as output, rest as input => this pin should exist on all devices, same as RESET/ICVPP pin
MOV A,0
_CAL_MAIN_LOOP:
T1SN PA.6 ;read bit from PA.6, increment IHRCR when low. Needs to be low for only one clock cycle!
ADD A,1
SET1 PA,5 ;output one clock cycle
SET0 PA,5
MOV IHRCR, A ;write current A value to IHRCR tuning register
_CAL_WAIT
T0SN PA.6 ;read bit from PA.6, increment IHRCR when low. Needs to be low for only one clock cycle!
GOTO _CAL_MAIN_LOOP
GOTO _CAL_WAIT
Maybe one could use SET1 and SET0 to toggle the clock? Then no memory write is needed. V1 needs the host to be really fast and issue a timed signal on PA6 to increment TMP. V2 will wait until PA6 is released again.
Edit: I see you were faster and already posted a version with SET0 and SET1 :)Code: [Select]_CALIBRATION_V1:
SET1 PAC,5 ;PA.5 as output, rest as input => this pin should exist on all devices, same as RESET/ICVPP pin
MOV A,0
_CAL_MAIN_LOOP:
T1SN PA.6 ;read bit from PA.6, increment IHRCR when low. Needs to be low for only one clock cycle!
ADD A,1
SET1 PA,5 ;output one clock cycle
SET0 PA,5
MOV IHRCR, A ;write current A value to IHRCR tuning register
GOTO _CAL_MAIN_LOOP
_CALIBRATION_V2:
SET1 PAC,5 ;PA.5 as output, rest as input => this pin should exist on all devices, same as RESET/ICVPP pin
MOV A,0
_CAL_MAIN_LOOP:
T1SN PA.6 ;read bit from PA.6, increment IHRCR when low. Needs to be low for only one clock cycle!
ADD A,1
SET1 PA,5 ;output one clock cycle
SET0 PA,5
MOV IHRCR, A ;write current A value to IHRCR tuning register
_CAL_WAIT
T0SN PA.6 ;read bit from PA.6, increment IHRCR when low. Needs to be low for only one clock cycle!
GOTO _CAL_MAIN_LOOP
GOTO _CAL_WAIT
In your version you increment the tuning register with each clock output. This is way to fast to measure. The original version toggles the bit in a loop with same IHRCR value until host signals to change it.
New idea:
Looks great! I love the trick of starting at 0xff to reuse the initialization value. Also much better to control the calibration value from the outside. This would allow to verify the setting. Otherwise there is a risk of bricking the device if there is a glitch during programming.
If you use CF=0 instead of CF=1 to signify a transmission you may be able to remove the MOV A,0?
Hmm, I cant not see what you mean. I only see that the MOV A,0xFF is before the MOV IHRCR,A and can not be used to reset A. The reset is required after a byte was clocked in since A could still have 1/0 bits which could produce more carry flags at next shifts.
Do we really need to fully send the value for IHRCR?This idea was a using less instructions and had the benefit of controlling the value.
Wouldn't it be sufficient if we always start with 0xFF and allow the programmer to decrease the value by 1 when setting PA.6 high for one cycle?
That way the programmer has still control over IHRCR, albeit a tad slower, but a few milliseconds don't matter during calibration. But you wouldn't need to reset A to 0 and you wouldn't need the SL. Or do I miss something?
_STARTUP:
MOV A,0xFF ;immediate value 0xFF with all bits 1, will be changed to MOV A,0x12 (0x12 = determined calibration value) after calibration was done
_STARTUP_IHRCR:
MOV IHRCR, A ;set the calibration value
GOTO _CALIBRATION ;jump to calibration code, will be overwritten with NOP after calibration
;user code here
_CALIBRATION:
SET1 PAC.5 ;PA.5 as output, rest as input => this pin should exist on all devices, it is same as RESET pin
SET1 PA.5 ;set output of PA.5 to 1
T0SN PA.6 ;read bit from PA.6
ADD A,1 ;increment A
SET0 PA.5 ;set output of PA.5 to 0
GOTO _STARTUP_IHRCR
_STARTUP:
MOV A,0xFF ;immediate value 0xFF with all bits 1, will be changed to MOV A,0x12 (0x12 = determined calibration value) after calibration was done
_STARTUP_IHRCR:
MOV IHRCR, A ;set the calibration value
GOTO _CALIBRATION ;jump to calibration code, will be overwritten with NOP after calibration
;user code here
_CALIBRATION:
T0SN PA.6 ;read bit from PA.6
ADD A,1 ;increment A
SET1 PAC.5 ;PA.5 as output, rest as input => this pin should exist on all devices, it is same as RESET pin
SET1 PA.5 ;set output of PA.5 to 1
SET0 PA.5 ;set output of PA.5 to 0
GOTO _STARTUP_IHRCR
_STARTUP:
MOV A,0xFF ;immediate value 0xFF with all bits 1, will be changed to MOV A,0x12 (0x12 = determined calibration value) after calibration was done
_STARTUP_IHRCR:
MOV IHRCR, A ;set the calibration value
GOTO _CALIBRATION ;jump to calibration code, will be overwritten with NOP after calibration
;set SP, init .BSS, init .DATA, ...
;user code here
_CALIBRATION:
MOV A,0
SET1 PAC.5 ;PA.5 as output, rest as input => this pin should exist on all devices, it is same as RESET pin
_CAL_TOGGLE_LOOP:
SET1 PA.5 ;set output of PA.5 to 1
SET0 PA.5 ;set output of PA.5 to 0
SWAPC PA.6
SLC A
T0SN CF ;CF not set?
GOTO _CAL_TOGGLE_LOOP
GOTO _STARTUP_IHRCR
According to the PMS150C datasheet it boots with ILRC not IHRC. May need setting CLKMD before calibration.Sure.
To avoid strict timing requirements the loop can be rewritten to make it slower. In the code below it should be safe to change PA.6 any time PA.5 is low, and it should stay lowSince on host (e.g. STM32) we can utilize a hardware SPI with DMA we can handle >24MHz SPI clock which for sure the IC will never achieve. But of course reordering is possible and should be done.a lotlonger than high. On the programmer set a rising edge-triggered interrupt on PA.5, busy-wait until cleared, then change PA.6.
Also, accidentally shaved one instruction away. :-) At least if rewriting IHRCR and PAC with the same values has no side efects.I like :-)
P.S.: Just figured what you guys meant by using the SPI to generate a pulse. It was supposed to be slave-mode on the programmer, right?Yes.
_STARTUP:
MOV A,0xFF ;immediate value 0xFF with all bits 1, will be changed to MOV A,0x12 (0x12 = determined calibration value) after calibration was done
_STARTUP_IHRCR:
MOV IHRCR, A ;set the calibration value
_CALIBRATION:
SET1 PAC.5 ;PA.5 as output (NOP after calibration)
SET1 PA.5 ;set output of PA.5 to 1 (NOP after calibration)
T0SN PA.6 ;read bit from PA.6 (NOP after calibration)
ADD A,1 ;increment A (NOP after calibration)
SET0 PA.5 ;set output of PA.5 to 0 (NOP after calibration)
GOTO _STARTUP_IHRCR
;user code here
* I also found 1 more instruction to "shave": we could now place the short calibration code in startup directly and overwrite all 6 instructions with NOP after calibration
* I also found 1 more instruction to "shave": we could now place the short calibration code in startup directly and overwrite all 6 instructions with NOP after calibration
Depends. For the 8-core pdk16, there is only 8 bytes in between the fppa7 entry point and the irq handler. You rourinte is 2 + 6 bytes, but once the 6 are overwritten by nop, the next instruction is already in the interrupt handler, so there is no space left for the goto to the startup routine.
Philipp
BTW: Somehow I managed with over voltage? to overwrite the PFS154 fixed chip ID section (with totally different value 0x0808). I still can read the IC reliable. The program inside does start but chip ERASE or WRITE to this section is not working anymore. Maybe I converted the flash part to OTP ?
BTW: Somehow I managed with over voltage? to overwrite the PFS154 fixed chip ID section (with totally different value 0x0808). I still can read the IC reliable. The program inside does start but chip ERASE or WRITE to this section is not working anymore. Maybe I converted the flash part to OTP ?
Did you try repeating the process (over volting) to change the ID?
@socram: I find the PNP transistors should be insufficient to block Vboost in reaching VPP and VDD. If Vboost>5V then the base voltage will be lower than the emitter's, there may be current, and the transistors may accidentally turn on.I found yesterday night that too, the hard way too, when I spent about one hour trying to figure out why the voltage didn't go to zero.
I would suggest using 2 additional NPNs to connect VPP_EN and VDD_EN to ground when required.
An added bonus is that it would also work with 3.3V MCUs on the programmer.
digitalWrite(pin, LOW);
...
digitalWrite(pin, HIGH);
I'm using:digitalWrite(pin, LOW);
pinMode(pin, OUTPUT); // ground PNP base
...
pinMode(pin, INPUT); // high impedance PNP base
I'm open to suggestions and improvements. I had thought about getting an ATtiny261, running V-USB on it and have the smallest and simplest, all-DIP programmer.
uint16_t padauk_command(uint8_t cmd) {
padauk_spi_write( 0xA5A, 12);
padauk_spi_write(0x5A5A, 16);
padauk_spi_write(cmd, 4);
/*
padauk_spi_input();
padauk_spi_clock();
padauk_spi_clock();
padauk_spi_clock();
*/
padauk_spi_write(0, 3);
padauk_spi_input();
padauk_spi_clock();
uint16_t ack = padauk_spi_read(12);
padauk_spi_clock();
padauk_spi_output();
return ack;
}
uint16_t padauk_flash_read(uint16_t addr) {
padauk_spi_write(addr, 13);
padauk_spi_input();
uint16_t data = padauk_spi_read(14);
// padauk_spi_output();
padauk_spi_clock();
padauk_spi_output();
return data;
}
Well I received yesterday some PFS154s, and I already have managed to get have them programmed. I've made the programmer as simple and as hobbyist-friendly as possible, using only DIP parts.
For writing, after sending the command it sets VDD_33_EN to high impedance, and then immediately lowers VDD_SMPS_EN, thus connecting both VPP and VDD to 5.8V, which seems to be the required voltage for programming.
I'm open to suggestions and improvements. I had thought about getting an ATtiny261, running V-USB on it and have the smallest and simplest, all-DIP programmer.
Regarding the voltage generation, I am considering replacing the whole thing with two buck/boost 2-switch converters, so I can switch the VCC before going inside the converter, rather than the 8V coming from the converter. That would also let me remove the HT7133.
Version | LDOs | NMOS | PNPs | NPNs | Diodes | Inductors | Resistors | Capacitors | VDD range | VPP range |
v1 (original) | 1 | 1 | 3 | 0 | 1 | 1 | 8 | 2 | 3.3V + 5V~8V | 5V~8V |
v1 (fixed high-side) | 1 | 3 | 3 | 0 | 1 | 1 | 10 | 2 | 3.3V + 5V~8V | 5V~8V |
v2 | 0 | 0 | 2 | 2 | 2 | 2 | 8 | 2 | 0V~8V | 5V~8V |
I think you still need a way to switch on and off VDD. If you rely only on the boost converter there will be very slow ramps. This could lead to malfunctioning of the reset circuit in the MCU. This could be a rare occurence, though.I'm not sure that would affect any modern microcontrollers, specially if they have low-voltage resets and brown-out resets such as these. I guess there's just one way to be sure about it - trying ;D
*Just to clarify, I am not looking into creating a "competing" github repository to free-pdk. I'd be happy to put relevant information there. But I was honestly not aware who is running it due to a lack of identifiable members on the site. Also someone would need to grant write access to me.
Tim
Added you to free-pdk organization on github*.
The assembler was contributed by Nicolas Lesser. I just merged a patch by him that fixes this issue.
Philipp
The assembler was contributed by Nicolas Lesser. I just merged a patch by him that fixes this issue.
Philipp
What would be the best way to get feedback and patches to him? I found and fixed a bug in enconding SL/SLC/SR/SRC. Fix attached.
Added you to free-pdk organization on github*.
Thanks a lot! I will put the programming protocol information there.
Btw, in general:
It seems like every other padauk device is using a different programming algorithm. So far, only two are known: PFS154 ("5-wire", confirmed twice), PMS150C ("six-wire". The PMC150C algorithm also works on the PMS154C, when changing datalen.
I tried a couple of other device:
- PMC251 uses six-wire physical interface, but was unresponsitve with the PMC150C algorithm
- PMS131 uses an eight-wire physical interface and seven when in an 8-pin package
It could get quite tedious to also decode all devices. Hopefully all MTP devices will use the 5-wire protocol.
To get the patches to him, I'd suggest opening an issue or pull request at his repo:
https://github.com/Rakete1111/sdcc-pdk
How about the PFS173? From the datasheet it looks as if it uses the same pins as the PFS154.
On the other hand, my information on the PFC232 and PFS232 indicates that these two use an interface different from the PFS154, and PA4 has a role in programming them (for a total of 6 pins in the interface).
- both assembled boards are working (tested basic functions: generate +15V, dual DAC+opamp can output specific voltages, USB ok, LEDs ok, button ok, ...)Nice!
- only 1 small mistake on test PCB (forgot to connect something to ground, was easy to fix with a jumper wire)
Nice!
May I suggest one addition for the next revision of the board:
Add another row of 8 holes in 2.54mm raster, spaced 15.24mm (6 rows in 2.54mm raster) from the current one. Connect all the holes to GND.
This would allow to later create small adapter pcbs, which can then be securely plugged on top of the programmer with pin header sockets. In these adapter pcbs you can then plug in programming sockets for the Padauk controllers.
See here for details of the idea: https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2105053/#msg2105053 (https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2105053/#msg2105053)
My initial idea was to go sideways.Yes, that would also work. But in my experience sideways going female headers (the ones that would go on the next pcb to the side) are more expensive and more rare than the straight ones. That is why I'd prefer to go on top.
I already created a small adapter PCB with a ZIF20 DIP small socket which can get connected to the 8 pins directly but also has pin header for every pin of the ZIF20 socket so it can be used as a generic adapter with jumper wires. This allows all PADAUK ICs to be written regardless of the pinout.Jumper wires are ok during programmer development. But I'd like to avoid them for regular use afterwards: they tend to create EMI problems and sometimes make bad contacts. So I'd prefer a solution with adapter pcbs which are made for one kind of Padauk controller. You can fit a lot of different ones on one 10x10 pcb.
Anyway I also like the on top idea. But new problems will arise like can not see LEDs or reach user button anymore, ...You could move the button to where the URL text is now.
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Re: EEVblog #1144 - Padauk Programmer Reverse Engineering
« Reply #479 on: Yesterday at 10:39:40 am »
Say ThanksReplyQuote
I assembled the 2 PCBs of my "easy pdk programmer" today.
- complete design process was done using EasyEDA + JLPCB + LCSC.
- learning how to use EasyEDA was very easy
- ordering on JLPCB was smooth and very good price ($2 for 10 PCBs, if you panelize then you might get 40 programmer PCBs for just $2 + shipping)
- ordering components at LCSC based on EasyEDA BOM was also very easy, they offer to combine shipment with JLPCB so you pay shipping ($5 for normal delivery) only once.
- it only took 8 days from ordering PCB + components till arrival *wow*
- both assembled boards are working (tested basic functions: generate +15V, dual DAC+opamp can output specific voltages, USB ok, LEDs ok, button ok, ...)
- only 1 small mistake on test PCB (forgot to connect something to ground, was easy to fix with a jumper wire)
I will test programing a PFS154 and some other ICs within the next days. Hopefully getting everything ready before chinese new year starts (China closes on 30th of January for 2-3 weeks).
JS
P.S. I will upload schematics, gerber and firmware sources to github as soon as the stable programmer is confirmed working.
PPS:
The PCB on top of the picture is having the optional 4 pin SWD header for easy debugging. The PCB on bottom is having an optional GND pin for easy oscilloscope measurements. Both of this optional components are not required for normal operation of the programmer later.
The missing components are caused by choosing a different DCDC booster and by getting rid of the not required level shifter.
I'd also suggest to add another button connected BOOT0 to boot with the integrated usb bootloader. That way you don't need a SWD programmer for initial programming. This would make it easier for people to make their own padauk programmers when they don't regularly use STM32 or other controllers with SWD interface.
I found femal sideways header on LCSC (you are right, it was tricky).My initial idea was to go sideways.Yes, that would also work. But in my experience sideways going female headers (the ones that would go on the next pcb to the side) are more expensive and more rare than the straight ones. That is why I'd prefer to go on top.
A lot of changes are requested/required (e.g. mounting holes, adapter on top, ...) I will see how much I can put into it.I already created a small adapter PCB with a ZIF20 DIP small socket which can get connected to the 8 pins directly but also has pin header for every pin of the ZIF20 socket so it can be used as a generic adapter with jumper wires. This allows all PADAUK ICs to be written regardless of the pinout.Jumper wires are ok during programmer development. But I'd like to avoid them for regular use afterwards: they tend to create EMI problems and sometimes make bad contacts. So I'd prefer a solution with adapter pcbs which are made for one kind of Padauk controller. You can fit a lot of different ones on one 10x10 pcb.
Was just a thought. Like the original PADAUK programmer. Maybe later you can transfer the image to programmer and then press the button to program (no need of computer).Anyway I also like the on top idea. But new problems will arise like can not see LEDs or reach user button anymore, ...You could move the button to where the URL text is now.
BTW, what do you plan to use the button for?
I'd also suggest to add another button connected BOOT0 to boot with the integrated usb bootloader. That way you don't need a SWD programmer for initial programming. This would make it easier for people to make their own padauk programmers when they don't regularly use STM32 or other controllers with SWD interface.Will do that, I try to connect the user button also to BOOT0.
Having the serial bootloader accessible would be nice, but it missing is not a deal breaker.Since ST-LinkV2 (china clone) costs less than $2 there is really no point anymore to use the serial boot loader.
A lot of changes are requested/required (e.g. mounting holes, adapter on top, ...) I will see how much I can put into it.I offer to make some adapter pcbs for different padauk ics and publish the sources & gerbers for others to use. So no extra work for you creating adapter pcbs. But I'll wait for you to publish a programmer layout with holder pins first.
I assembled the 2 PCBs of my "easy pdk programmer" today.Great work, very clean build!
...
I will test programing a PFS154 and some other ICs within the next days. Hopefully getting everything ready before chinese new year starts (China closes on 30th of January for 2-3 weeks).
I only can strongly recommend to switch to real software development (use JTAG/SWD and a debugger) and avoid the "printf debugging" introduced by Arduino.
Setting up and learning how to use the free open source tool chains for real development and debugging is dead simply nowadays. And it is possible to use all Arduino libraries and sample code.
Just ditch the Arduino IDE!
Any success with programming so far? :)Not much time right now. I just got ADC working properly (was mistake with a resistor in schematic). Next part is trying to reduce ripple (everything is a bit noisy right now so I will play a bit with different cap values / adding some caps).
Well, it looks like we are stuck with "printf debugging" with the Padauk controllers though. One thing I implemented was to use the programming interface as an SPI backchannel. The "programmer" (I am referring to my breadboard contraption) is resetting the MCU and is then listening to SPI transmissions on the programming interface lines as a slave. This allowed some degree of debugging. This may be an interesting addition to the firmware of your programmer as well.
But do you think SPI is a good choice? I used it in a previous test and had the problem that if a single bit was missing (e.g. after startup) the complete output was garbled.I have bad experience with several kinds of CS-less SPI variants. You need a mechanism like CS, otherwise your transfer quickly becomes unreliable.
spth made a small demo with a very simple UART. Maybe we should choose this method as it can handle transmission errors more easy (e.g. require 2 stop bits and we can resync).
Or we use SPI with CS(NSS) but then 1 more wire required.
Having an UART with autobaud would be the best option, but it's a bit more involved to implement this on host side. How would you do bitrate detection? By bitbanging? Or oversampling with DMA?The STM32 have autobaud hardware, see AN4908: https://www.st.com/content/ccc/resource/technical/document/application_note/group0/66/fa/62/a2/5c/75/48/a8/DM00327191/files/DM00327191.pdf/jcr:content/translations/en.DM00327191.pdf (https://www.st.com/content/ccc/resource/technical/document/application_note/group0/66/fa/62/a2/5c/75/48/a8/DM00327191/files/DM00327191.pdf/jcr:content/translations/en.DM00327191.pdf)
I adapted SDAS to PDK13, so it is now also possible to use a OSS toolchain for the true "$0.03 MCU". Not sure whether this will be available upstream anytime soon, as there is still some work to be done to allow PDK13 and PDK14 to coexist in SDCC. (Frankly, that is probably the harder part...)
Where can I find this sdas for pdk13? How is the target selected? An assembler directive similar to how ".cs08" switches the hc08 assembler to s08 mode and .hd64 switches the z80 assembler to z180 mode?
Philipp
0 0 0 0 1 1 c 7-bit MEM addr c 16 bit memory operations
0x03.. 0 0 0 0 1 1 0 M 0 STT16 M M ← Timer16 (last bit of M set to 0, M must be word aligned)
0x03.. 0 0 0 0 1 1 0 M 1 LDT16 M Timer16 ← M (last bit of M set to 1, M must be word aligned)
lsb will always be 0, the bits in the opcode are in the correct bit position, just make bit 0 be 0 always.
- added two 8 pin female header to plugin adapter for programing on top (not going to side anymore)good idea.
=> the 8 pin rows are connected that a standard TSOP16-DIP adapter can be plugged in directly and many PADAUK IC variants (esp. the flash variants like PFS154) can be programmed without an additional adapter PCB.
=> adapter PCB can be designed easily for other types and plugged on top
So your plan is that you usually solder a DIP 16 ZIF socket directly onto the programmer pcb and then plug a SOIC adapter into the zif socket. Optionally you can plug in adapter pcbs into the zif socket. Correct?
Or do you not want to use the zif socket and use female pin headers instead and plug the SOIC adapter into them?
Hi,why... :palm:
since PCB delivery is delayed due to Chinese new year a friend and I played a bit making a 3D printable case for the Easy PDK Programmer.
Hi,why... :palm:
since PCB delivery is delayed due to Chinese new year a friend and I played a bit making a 3D printable case for the Easy PDK Programmer.
Just design the PCB to fit a standard Hammond box.
..and how much time & material does a crappy-looking 3D printed case cost ?Hi,why... :palm:
since PCB delivery is delayed due to Chinese new year a friend and I played a bit making a 3D printable case for the Easy PDK Programmer.
Just design the PCB to fit a standard Hammond box.
Why? Because we can ;D
You also can mount the pcb in a "Hammond box", do some cutting for USB and the pin header and end up with a boring square case where the case alone costs more than the complete programmer.
..and how much time & material does a crappy-looking 3D printed case cost ?Hi,why... :palm:
since PCB delivery is delayed due to Chinese new year a friend and I played a bit making a 3D printable case for the Easy PDK Programmer.
Just design the PCB to fit a standard Hammond box.
Why? Because we can ;D
You also can mount the pcb in a "Hammond box", do some cutting for USB and the pin header and end up with a boring square case where the case alone costs more than the complete programmer.
If you use something like these, you can use PCBs as end panels, so no manual hole cutting etc.
https://www.hammfg.com/electronics/small-case/plastic/1593 (https://www.hammfg.com/electronics/small-case/plastic/1593)
(https://www.hammfg.com/files/images/electronics/electronics/1593-gray-pcb-200w.jpg)
#define EASY_PDK_CALIBRATE_IHRC(frequency) \
__asm__( \
"and a, #'I' \n"\
"and a, #'H' \n"\
"and a, #'R' \n"\
"and a, #'C' \n"\
"and a, #("#frequency") \n"\
"and a, #("#frequency">>8) \n"\
"and a, #("#frequency">>16) \n"\
"and a, #("#frequency">>24) \n"\
)
#define EASY_PDK_CALIBRATE_ILRC(frequency) \
__asm__( \
"and a, #'I' \n"\
"and a, #'L' \n"\
"and a, #'R' \n"\
"and a, #'C' \n"\
"and a, #("#frequency") \n"\
"and a, #("#frequency">>8) \n"\
"and a, #("#frequency">>16) \n"\
"and a, #("#frequency">>24) \n"\
)
unsigned char _sdcc_external_startup(void)
{
clkmd = 0x34; // Use IHRC / 2 = 8 Mhz for system clock, disable ILRC, disable watchdog
EASY_PDK_CALIBRATE_IHRC(8000000); // calibrate IHRC to 8 MHz system clock
return 0;
}
Try adding 100R dummy loads to each output.Thanks. I've tried it and it gets somewhat better, but still gets screwed every now and then. I guess I'll try that the PID controller.
I had thought about getting an ATtiny261, running V-USB on it and have the smallest and simplest, all-DIP programmer.Whay not use a Padauk MCU to program Padauk MCUs.
I had thought about getting an ATtiny261, running V-USB on it and have the smallest and simplest, all-DIP programmer.Whay not use a Padauk MCU to program Padauk MCUs.
...+ some off-the shelf discrete components.
I don't think it makes sense to build a boost converter yourself, except for fun and learning. There are so many ICs out there which does this, probably at lcsc.com for cheap as well, which need just one external inductor. The performance and regulation is probably better than your DIY version, and parts costs might be lower. And for each part, you would need to pay assembly cost too, if a manufacturer does the full board for you. Using a fixed voltage boost converter and a microcontroller with a DAC, and an OpAmp, would then be the easiest and most reliable way to regulate it, and with low noise and ripple.No matter which way I go, I still need one inductor, one diode and one capacitor for a boost converter. It is true that using a dedicated converter would simplify the boost converter design (by removing the MOSFET and the enable PNP and replacing that with a boost IC with input enable pin).
Evaluation boards (design on https://github.com/free-pdk/f-eval-boards), hand-soldered prototypes).
Nice timing. I just got PCB1.2 revision of Easy PDK Programmer and soldered a small batch. No problems found so far. Everything working as expected.That's great, because Also I have ordered some PFS173-S14, I hope they become useful in my projects! Also I found it weird, I can not find these puppies from my other Chinese suppliers! I have at list tried 10 different suppliers, I only got them from lcsc :(
Firmware for the STM32 is almost complete (I think next weekend I can finish last part of calibration).
Initial host software is also working (command line utility which supports Linux/Mac/Windows for reading/writing/executing + serial output debugging).
I will upload all schematics + firmware + software right after I'm sure everything is working as expected.
Firmware for the STM32 is almost complete (I think next weekend I can finish last part of calibration).
Initial host software is also working (command line utility which supports Linux/Mac/Windows for reading/writing/executing + serial output debugging).
Firmware for the STM32 is almost complete (I think next weekend I can finish last part of calibration).
Initial host software is also working (command line utility which supports Linux/Mac/Windows for reading/writing/executing + serial output debugging).
Which Padauk devices are currently supported?
Philipp
1. SDCC compiler development branch which supports PADAUK (MANY MANY thanks to SPTH and Nicolas Lesser) is used to compile a small test program
Where can we download latest SDCC?
...check it out and compile it.Thank You. It's working.
Quote from: js_12345678_55AA...check it out and compile it.Thank You. It's working.
Yes really need the +1 for PCADD. Otherwise my program was jumping into nowhere, crashing (I think it adds 256 in the case of A=0, will need to investigate)
Yes really need the +1 for PCADD. Otherwise my program was jumping into nowhere, crashing (I think it adds 256 in the case of A=0, will need to investigate)
Any news on zero a?
Philipp
I'm working on PFS173 support (read/erase is working, somehow write does not write a single bit yet).Thanks, I have orders some of these ;) :-[
I'm working on PFS173 support (read/erase is working, somehow write does not write a single bit yet).I have similar results with my programmer.
I will cleanup the sources and release all of them on https://free-pdk.github.io during the next few days:Thanks for posting the hardware files of the programmer.
- Easy PDK programmer schematic and PCB design files
Did you use these gerber files to order at JLCPCB or did you use a direct order link from easyeda into JLCPCB?
The exact same Gerber ZIP file was uploaded to JLCPCB using the upload Gerber function. The production went smoothly and the received PCB panels did not have any error (also the USB port fits nicely).Good to know, thanks.
The multiple copy of the outline without having the same PCB inside is an industry standard for PCB factories used to indicate to panelize the PCB.I never heard of that one. All the tutorials regarding panelization I've seen copy the actual content. Do you happen to have a link or document explaining the details of this process?
Only supported by the 14 bit parts.
https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2010509/#msg2010509 (https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2010509/#msg2010509)
I'm working on PFS173 support (read/erase is working, somehow write does not write a single bit yet).Any progress?
QuoteI'm working on PFS173 support (read/erase is working, somehow write does not write a single bit yet).Any progress?
I think i found a new command.
0xA5A5A5AB, with B like BRICKED at the end ;D
When executed µC looks like locked, but FW does not work and cannot be erased.
Tested on pfs154 and pfs173, vpp 10V, vcc 5V/6V.
What's the difference beetween PFS154 and PFS173 in write?
A5A5A5A7
1 bit
15 bit word
15 bit word
15 bit word
15 bit word
13 bit address
...
...
?
:-+ :-+ :-+Firmware please
Even if all empty space was filled, maybe you can side channel attack the programming cycle. I remember that previously you guys had only a few bits programming due to limited power supply...
Try writing 0 to one bit at a time and record the programming current.
I am assuming programming a previously 1 bit takes more energy than a previously 0 bit.
If it works then there is no more code protection viable for these IC.This is a *cheap* IC, not a security IC. It also costs next to nothing sending PADAUK IC to the usual suspects for IC extraction.
volatile unsigned char mem, ta, ra, rf, rsp;
...
ra=0;
rf=0;
rsp=0;
for(ta=0;;ta++)
{
putchar('T'); printhex(ta); putchar('-');
__asm
mov a, #0
mov __flag, a
mov a, _ta
.dw 0x0064 //instruction opcode
mov _ra, a
mov a, __flag
mov _rf, a
mov a, __sp
mov _rsp, a
__endasm;
putchar('a');printhex(ra); putchar('-');
putchar('f');printhex(rf); putchar('-');
putchar('s');printhex(rsp); putchar('-');
putchar('m');printhex(mem);.
putchar('\n');
for(unsigned long int i=10000; i>0; i--); // Wait approx. 20ms
}
...
T00-a00-fF1-s10-m00
T01-aFF-fF6-s10-m00
T02-aFE-fF6-s10-m00
T03-aFD-fF6-s10-m00
T04-aFC-fF6-s10-m00
T05-aFB-fF6-s10-m00
T06-aFA-fF6-s10-m00
T07-aF9-fF6-s10-m00
T08-aF8-fF6-s10-m00
T09-aF7-fF6-s10-m00
T0A-aF6-fF6-s10-m00
T0B-aF5-fF6-s10-m00
T0C-aF4-fF6-s10-m00
T0D-aF3-fF6-s10-m00
T0E-aF2-fF6-s10-m00
T0F-aF1-fF6-s10-m00
T10-aF0-fF2-s10-m00
T11-aEF-fF6-s10-m00
T12-aEE-fF6-s10-m00
T13-aED-fF6-s10-m00
T14-aEC-fF6-s10-m00
T15-aEB-fF6-s10-m00
T16-aEA-fF6-s10-m00
T17-aE9-fF6-s10-m00
T18-aE8-fF6-s10-m00
T19-aE7-fF6-s10-m00
T1A-aE6-fF6-s10-m00
T1B-aE5-fF6-s10-m00
T1C-aE4-fF6-s10-m00
T1D-aE3-fF6-s10-m00
T1E-aE2-fF6-s10-m00
T1F-aE1-fF6-s10-m00
T20-aE0-fF2-s10-m00
T21-aDF-fF6-s10-m00
T22-aDE-fF6-s10-m00
T23-aDD-fF6-s10-m00
T24-aDC-fF6-s10-m00
T25-aDB-fF6-s10-m00
T26-aDA-fF6-s10-m00
T27-aD9-fF6-s10-m00
T28-aD8-fF6-s10-m00
T29-aD7-fF6-s10-m00
T2A-aD6-fF6-s10-m00
T2B-aD5-fF6-s10-m00
T2C-aD4-fF6-s10-m00
T2D-aD3-fF6-s10-m00
T2E-aD2-fF6-s10-m00
T2F-aD1-fF6-s10-m00
T30-aD0-fF2-s10-m00
T31-aCF-fF6-s10-m00
T32-aCE-fF6-s10-m00
T33-aCD-fF6-s10-m00
T34-aCC-fF6-s10-m00
T35-aCB-fF6-s10-m00
T36-aCA-fF6-s10-m00
T37-aC9-fF6-s10-m00
T38-aC8-fF6-s10-m00
T39-aC7-fF6-s10-m00
T3A-aC6-fF6-s10-m00
T3B-aC5-fF6-s10-m00
T3C-aC4-fF6-s10-m00
T3D-aC3-fF6-s10-m00
T3E-aC2-fF6-s10-m00
T3F-aC1-fF6-s10-m00
T40-aC0-fF2-s10-m00
T41-aBF-fF6-s10-m00
T42-aBE-fF6-s10-m00
T43-aBD-fF6-s10-m00
T44-aBC-fF6-s10-m00
T45-aBB-fF6-s10-m00
T46-aBA-fF6-s10-m00
T47-aB9-fF6-s10-m00
T48-aB8-fF6-s10-m00
T49-aB7-fF6-s10-m00
T4A-aB6-fF6-s10-m00
T4B-aB5-fF6-s10-m00
T4C-aB4-fF6-s10-m00
T4D-aB3-fF6-s10-m00
T4E-aB2-fF6-s10-m00
T4F-aB1-fF6-s10-m00
T50-aB0-fF2-s10-m00
T51-aAF-fF6-s10-m00
T52-aAE-fF6-s10-m00
T53-aAD-fF6-s10-m00
T54-aAC-fF6-s10-m00
T55-aAB-fF6-s10-m00
T56-aAA-fF6-s10-m00
T57-aA9-fF6-s10-m00
T58-aA8-fF6-s10-m00
T59-aA7-fF6-s10-m00
T5A-aA6-fF6-s10-m00
T5B-aA5-fF6-s10-m00
T5C-aA4-fF6-s10-m00
T5D-aA3-fF6-s10-m00
T5E-aA2-fF6-s10-m00
T5F-aA1-fF6-s10-m00
T60-aA0-fF2-s10-m00
T61-a9F-fF6-s10-m00
T62-a9E-fF6-s10-m00
T63-a9D-fF6-s10-m00
T64-a9C-fF6-s10-m00
T65-a9B-fF6-s10-m00
T66-a9A-fF6-s10-m00
T67-a99-fF6-s10-m00
T68-a98-fF6-s10-m00
T69-a97-fF6-s10-m00
T6A-a96-fF6-s10-m00
T6B-a95-fF6-s10-m00
T6C-a94-fF6-s10-m00
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T70-a90-fF2-s10-m00
T71-a8F-fF6-s10-m00
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T73-a8D-fF6-s10-m00
T74-a8C-fF6-s10-m00
T75-a8B-fF6-s10-m00
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T7C-a84-fF6-s10-m00
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T8A-a76-fF6-s10-m00
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T91-a6F-fF6-s10-m00
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T93-a6D-fF6-s10-m00
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T9A-a66-fF6-s10-m00
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T9F-a61-fF6-s10-m00
TA0-a60-fF2-s10-m00
TA1-a5F-fF6-s10-m00
TA2-a5E-fF6-s10-m00
TA3-a5D-fF6-s10-m00
TA4-a5C-fF6-s10-m00
TA5-a5B-fF6-s10-m00
TA6-a5A-fF6-s10-m00
TA7-a59-fF6-s10-m00
TA8-a58-fF6-s10-m00
TA9-a57-fF6-s10-m00
TAA-a56-fF6-s10-m00
TAB-a55-fF6-s10-m00
TAC-a54-fF6-s10-m00
TAD-a53-fF6-s10-m00
TAE-a52-fF6-s10-m00
TAF-a51-fF6-s10-m00
TB0-a50-fF2-s10-m00
TB1-a4F-fF6-s10-m00
TB2-a4E-fF6-s10-m00
TB3-a4D-fF6-s10-m00
TB4-a4C-fF6-s10-m00
TB5-a4B-fF6-s10-m00
TB6-a4A-fF6-s10-m00
TB7-a49-fF6-s10-m00
TB8-a48-fF6-s10-m00
TB9-a47-fF6-s10-m00
TBA-a46-fF6-s10-m00
TBB-a45-fF6-s10-m00
TBC-a44-fF6-s10-m00
TBD-a43-fF6-s10-m00
TBE-a42-fF6-s10-m00
TBF-a41-fF6-s10-m00
TC0-a40-fF2-s10-m00
TC1-a3F-fF6-s10-m00
TC2-a3E-fF6-s10-m00
TC3-a3D-fF6-s10-m00
TC4-a3C-fF6-s10-m00
TC5-a3B-fF6-s10-m00
TC6-a3A-fF6-s10-m00
TC7-a39-fF6-s10-m00
TC8-a38-fF6-s10-m00
TC9-a37-fF6-s10-m00
TCA-a36-fF6-s10-m00
TCB-a35-fF6-s10-m00
TCC-a34-fF6-s10-m00
TCD-a33-fF6-s10-m00
TCE-a32-fF6-s10-m00
TCF-a31-fF6-s10-m00
TD0-a30-fF2-s10-m00
TD1-a2F-fF6-s10-m00
TD2-a2E-fF6-s10-m00
TD3-a2D-fF6-s10-m00
TD4-a2C-fF6-s10-m00
TD5-a2B-fF6-s10-m00
TD6-a2A-fF6-s10-m00
TD7-a29-fF6-s10-m00
TD8-a28-fF6-s10-m00
TD9-a27-fF6-s10-m00
TDA-a26-fF6-s10-m00
TDB-a25-fF6-s10-m00
TDC-a24-fF6-s10-m00
TDD-a23-fF6-s10-m00
TDE-a22-fF6-s10-m00
TDF-a21-fF6-s10-m00
TE0-a20-fF2-s10-m00
TE1-a1F-fF6-s10-m00
TE2-a1E-fF6-s10-m00
TE3-a1D-fF6-s10-m00
TE4-a1C-fF6-s10-m00
TE5-a1B-fF6-s10-m00
TE6-a1A-fF6-s10-m00
TE7-a19-fF6-s10-m00
TE8-a18-fF6-s10-m00
TE9-a17-fF6-s10-m00
TEA-a16-fF6-s10-m00
TEB-a15-fF6-s10-m00
TEC-a14-fF6-s10-m00
TED-a13-fF6-s10-m00
TEE-a12-fF6-s10-m00
TEF-a11-fF6-s10-m00
TF0-a10-fF2-s10-m00
TF1-a0F-fF6-s10-m00
TF2-a0E-fF6-s10-m00
TF3-a0D-fF6-s10-m00
TF4-a0C-fF6-s10-m00
TF5-a0B-fF6-s10-m00
TF6-a0A-fF6-s10-m00
TF7-a09-fF6-s10-m00
TF8-a08-fF6-s10-m00
TF9-a07-fF6-s10-m00
TFA-a06-fF6-s10-m00
TFB-a05-fF6-s10-m00
TFC-a04-fF6-s10-m00
TFD-a03-fF6-s10-m00
TFE-a02-fF6-s10-m00
TFF-a01-fF6-s10-m00
I'm waiting for the PDK15 assembler from SDCC to be ready to compile for PFS173 so we can hunt for the missing instructions there.
Which types from the list above do you think are most interesting to support or what other types + adapter you would consider useful?
JS
do a port to the '8266I wonder what the usecase for that is? For example for me it would be much more work to integrate the esp into my network than just to plug in a usb cable.
2) Any idea how sensitive the voltages are, for instance what the optimal values are for VPP and VDD at different stages? Do we ever /need/ to set VPP higher than 8.3V?VPP must go to 10.8. There are some reports of problems when not getting the voltages right in this thread.
3) Why didn't you guys go STM32F042 I didn't see anyone mentioning it? The crystal-less operation makes things really convenient and cheap.The ´72 is very similar, also does crystal-less. But the ´42 is not as common and more expensive.
A side-goal of mine is I want to make an arduino-style development environment, that is 100% web-based. This part is purely for funzies. It's something I've wanted to dink with for a while. Currently most of the web-based ones are for high-level languages, but these are not interesting to me, and this here affords me an opportunity to cut my teeth with web-based compilation. EDIT: Because of the power rail complexity, I am definitely feeling discouraged from an ESP8266 solution.do a port to the '8266I wonder what the usecase for that is? For example for me it would be much more work to integrate the esp into my network than just to plug in a usb cable.
Understood.2) Any idea how sensitive the voltages are, for instance what the optimal values are for VPP and VDD at different stages? Do we ever /need/ to set VPP higher than 8.3V?VPP must go to 10.8. There are some reports of problems when not getting the voltages right in this thread.
3) Why didn't you guys go STM32F042 I didn't see anyone mentioning it? The crystal-less operation makes things really convenient and cheap.The ´72 is very similar, also does crystal-less. But the ´42 is not as common and more expensive.
How about the Puolop PTBO164SX? According to Puolop, it has 1.75 KW of ROM, but I don't see a part with that amount of ROM in the Padauk catalog.
unsigned char _sdcc_external_startup(void)
{
PDK_INIT_SYSCLOCK_4MHZ(); //use 4MHz so we can use 3.0V VDD
EASY_PDK_CALIBRATE_IHRC(4000000,3000); //tune SYSCLK = 4MHz @ 3.000V
return 0; //perform normal initialization
}
void interrupt(void) __interrupt(0)
{
if(_intrq & INTRQ_T16) //interrupt request for timer16?
{
//do something here...
_intrq &= ~INTRQ_T16; //clear this interrupt request
}
}
#define SPI_PORT _pa
#define SPI_PORTC _pac
#define SPI_NCS_PIN 4
#define SPI_CLK_PIN 0
#define SPI_OUT_PIN 6
#define SPI_IN_PIN 7
//...
uint8_t SPI_SendReceive(uint8_t s)
{
__asm__(
" mov a, #8 \n" //loop 8 times
"__SPI_SNDRCV_BIT: \n"
" set0 "_ASMV(SPI_PORT)", #"_ASMD(SPI_OUT_PIN)" \n" //SPI-OUT = 0
" t0sn _SPI_SendReceive_PARM_1, #7 \n" //s.7==0 ?
" set1 "_ASMV(SPI_PORT)", #"_ASMD(SPI_OUT_PIN)" \n" //SPI-OUT = 1
" set1 "_ASMV(SPI_PORT)", #"_ASMD(SPI_CLK_PIN)" \n" //SPI-CLK = 1
" sl _SPI_SendReceive_PARM_1 \n" //s<<=1
" t0sn "_ASMV(SPI_PORT)", #"_ASMD(SPI_IN_PIN)" \n" //SPI-IN==0 ?
" set1 _SPI_SendReceive_PARM_1, #0 \n" //s.0=1
" set0 "_ASMV(SPI_PORT)", #"_ASMD(SPI_CLK_PIN)" \n" //SPI-CLK = 0
" dzsn a \n" //loop--
" goto __SPI_SNDRCV_BIT \n" //loop again if>0
);
return s;
}
Attached is my current WORK IN PROGRESS version (one big include file for all). It includes the calibration definitions and many other useful stuff.thanks for posting. This is indeed much more than just the cal definitions.
I see the firmware uses ST's USB middleware, which is under ST's SLA0044 license.->(1) The USB middleware source code by itself is still under ST license (see file headers of ST USB middleware for details).
Ain't this incompatible with GPL (eg. Do you need a linking exception to allow the ST USB middleware to be used?->(2) It is explicitly allowed to use the compiled firmware containing ST code to be used on ST microprocessors (which is the case here).
The developed FREE-PDK software is GPL. This is the authors choice and 100% valid.I don't think GromBeestje questioned this.
Even the explicit mentioned GPL in (5) refers to another fact. It tries to make clear that the middleware software from ST can never become GPL licensed (which is not the case here, it still falls under the original ST license visible in all ST files).The problem is that this is incompatible with the GPL. The GPL requires that all parts of the program are compatible with the GPL. As the ST files are linked into the final program, you can't distribute a binary that complies with the GPL.
Maybe this will not fulfill the strict 100% GPL requirements of a complete compiled software package required from some Linux distributions like Debian and therefor the software can not be bundled with Debian but this does not mean that there is a problem using GPL for the FREE-PDK software.It means noone, not just linux distributions, is allowed to distribute binary packages of free-pdk as it can't be done in a legally clean manner that complies with the GPL and the SLA0044. i idea. The moment there are contributions from other people in the codebase, even you can't distribute compiled binaries on github anymore unless you have the written permission of all contributors to publish these binaries under a different license than the GPL (as the GPL forbids distributing stuff linked with GPL-incompatible parts). I don't think this is what you intended.
"GPL linking exception for FREE PDK Programmer STM32 firmware binary: You are allowed to compile and link the complete code from this repository, including the included ST USB middleware, in order to build a binary firmware which you can use on the STM32 based Free PDK programmer."The GPL doesn't forbid you to compile and link something non-GPL-compliant, it forbids you to distribute this binary. Unfortunately careful wording is required to avoid the pitfalls of legalese...
Additional permission under GNU GPL version 3 section 7
If you modify this program, or any covered work, by linking or combining it with the STMicroelectronics STM32 USB Device Library (or a modified version of that library),
you are granted additional permission to convey the resulting work. Corresponding Source for a non-source form of such a combination shall include the source code for the
parts of the STM32 USB Device Library used as well as that of the covered work.
"GPL linking exception for FREE PDK Programmer STM32 firmware binary: You are allowed to compile and link the complete code from this repository, including the included ST USB middleware, in order to build a binary firmware which you can use on the STM32 based Free PDK programmer."The GPL doesn't forbid you to compile and link something non-GPL-compliant, it forbids you to distribute this binary. Unfortunately careful wording is required to avoid the pitfalls of legalese...
GPL exceptions are a common thing and I suggest to re-use and adapt what others have done. It looks like for example wget uses something that would fit. See https://en.wikipedia.org/wiki/Wget#License (https://en.wikipedia.org/wiki/Wget#License).
I suggest to adapt it like this:Code: [Select]Additional permission under GNU GPL version 3 section 7
If you modify this program, or any covered work, by linking or combining it with the STMicroelectronics STM32 USB Device Library (or a modified version of that library),
you are granted additional permission to convey the resulting work. Corresponding Source for a non-source form of such a combination shall include the source code for the
parts of the STM32 USB Device Library used as well as that of the covered work.
Hi,I agree with you, also we can copy what ST has done to STM32, and the HAL and libraries for them, they are very good :)
To understand the register mappings on different PDK CPU types better I created a list (based on include files from original IDE).
https://github.com/free-pdk/fppa-pdk-documentation/blob/master/PDK_register_mapping_scroll_right.csv
Attached is a colorful version as PNG from it.
Based on this info (most registers jump around for different types and only a few number remains static) I think the best idea would be to create one include file per supported processor like:
pdk/pmc150c.h
pdk/pfs154.h
pdk/pfs173.h
...
Comments? Suggestions?
JS
Hi,
To understand the register mappings on different PDK CPU types better I created a list (based on include files from original IDE).
https://github.com/free-pdk/fppa-pdk-documentation/blob/master/PDK_register_mapping_scroll_right.csv
Attached is a colorful version as PNG from it.
Based on this info (most registers jump around for different types and only a few number remains static) I think the best idea would be to create one include file per supported processor like:
pdk/pmc150c.h
pdk/pfs154.h
pdk/pfs173.h
...
Comments? Suggestions?
JS
In the table i miss the Timer3 registers for the PFS154.
C compiler: https://github.com/free-pdk/sdcc-pdk-code-examplesThanks for the info, this link is only the examples, though I installed SDCC, how to compile the examples? what's the command?
~/sdcc/bin/sdcc -lpdk15 -mpdk15 count.c
-rw-r--r-- 1 frank frank 4424 Jul 24 11:44 count.sym
-rw-r--r-- 1 frank frank 19123 Jul 24 11:44 count.rst
-rw-r--r-- 1 frank frank 6046 Jul 24 11:44 count.rel
-rw-r--r-- 1 frank frank 8774 Jul 24 11:44 count.map
-rw-r--r-- 1 frank frank 19123 Jul 24 11:44 count.lst
-rw-r--r-- 1 frank frank 192 Jul 24 11:44 count.lk
-rw-r--r-- 1 frank frank 1132 Jul 24 11:44 count.ihx
-rw-r--r-- 1 frank frank 0 Jul 24 11:44 count.cdb
-rw-r--r-- 1 frank frank 1720 Jul 24 11:37 count.c
-rw-r--r-- 1 frank frank 6843 Jul 24 11:44 count.asm
SDCC : mcs51/z80/z180/r2k/r3ka/gbz80/tlcs90/ez80_z80/ds390/pic16/pic14/TININative/ds400/hc08/s08/stm8/pdk14/pdk15 3.9.0 #11195 (MINGW64)
published under GNU General Public License (GPL)
Usage : sdcc [options] filename
Options :-
General options:
--help Display this help
-v --version Display sdcc's version
--verbose Trace calls to the preprocessor, assembler, and linker
-V Execute verbosely. Show sub commands as they are run
-d Output list of mcaro definitions in effect. Use with -E
-D Define macro as in -Dmacro
-I Add to the include (*.h) path, as in -Ipath
-A
-U Undefine macro as in -Umacro
-M Preprocessor option
-W Pass through options to the pre-processor (p), assembler (a) or linker (l)
-S Compile only; do not assemble or link
-c --compile-only Compile and assemble, but do not link
-E --preprocessonly Preprocess only, do not compile
--c1mode Act in c1 mode. The standard input is preprocessed code, the output is assembly code.
-o Place the output into the given path resp. file
--print-search-dirs display the directories in the compiler's search path
--vc messages are compatible with Micro$oft visual studio
--use-stdout send errors to stdout instead of stderr
--nostdlib Do not include the standard library directory in the search path
--nostdinc Do not include the standard include directory in the search path
--less-pedantic Disable some of the more pedantic warnings
--disable-warning <nnnn> Disable specific warning
--Werror Treat the warnings as errors
--debug Enable debugging symbol output
--cyclomatic Display complexity of compiled functions
--std-c89 Use ISO C90 (aka ANSI C89) standard (slightly incomplete)
--std-sdcc89 Use ISO C90 (aka ANSI C89) standard with SDCC extensions
--std-c95 Use ISO C95 (aka ISO C94) standard (slightly incomplete)
--std-c99 Use ISO C99 standard (incomplete)
--std-sdcc99 Use ISO C99 standard with SDCC extensions
--std-c11 Use ISO C11 standard (incomplete)
--std-sdcc11 Use ISO C11 standard with SDCC extensions (default)
--std-c2x Use ISO C2X standard (incomplete)
--std-sdcc2x Use ISO C2X standard with SDCC extensions
--fdollars-in-identifiers Permit '$' as an identifier character
--fsigned-char Make "char" signed by default
--use-non-free Search / include non-free licensed libraries and header files
Code generation options:
-m Set the port to use e.g. -mz80.
-p Select port specific processor e.g. -mpic14 -p16f84
--stack-auto Stack automatic variables
--xstack Use external stack
--int-long-reent Use reentrant calls on the int and long support functions
--float-reent Use reentrant calls on the float support functions
--xram-movc Use movc instead of movx to read xram (xdata)
--callee-saves <func[,func,...]> Cause the called function to save registers instead of the caller
--profile On supported ports, generate extra profiling information
--fomit-frame-pointer Leave out the frame pointer.
--all-callee-saves callee will always save registers used
--stack-probe insert call to function __stack_probe at each function prologue
--no-xinit-opt don't memcpy initialized xram from code
--no-c-code-in-asm don't include c-code as comments in the asm file
--no-peep-comments don't include peephole optimizer comments
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--dataseg <name> use this name for the data segment
Optimization options:
--nooverlay Disable overlaying leaf function auto variables
--nogcse Disable the GCSE optimisation
--nolabelopt Disable label optimisation
--noinvariant Disable optimisation of invariants
--noinduction Disable loop variable induction
--noloopreverse Disable the loop reverse optimisation
--no-peep Disable the peephole assembly file optimisation
--no-reg-params On some ports, disable passing some parameters in registers
--peep-asm Enable peephole optimization on inline assembly
--peep-return Enable peephole optimization for return instructions
--no-peep-return Disable peephole optimization for return instructions
--peep-file <file> use this extra peephole file
--opt-code-speed Optimize for code speed rather than size
--opt-code-size Optimize for code size rather than speed
--max-allocs-per-node Maximum number of register assignments considered at each node of the tree decomposition
--nolospre Disable lospre
--allow-unsafe-read Allow optimizations to read any memory location anytime
--nostdlibcall Disable optimization of calls to standard library
Internal debugging options:
--dump-ast Dump front-end AST before generating i-code
--dump-i-code Dump the i-code structure at all stages
--dump-graphs Dump graphs (control-flow, conflict, etc)
--i-code-in-asm Include i-code as comments in the asm file
--fverbose-asm Include code generator comments in the asm output
Linker options:
-l Include the given library in the link
-L Add the next field to the library search path
--lib-path <path> use this path to search for libraries
--out-fmt-ihx Output in Intel hex format
--out-fmt-s19 Output in S19 hex format
--xram-loc <nnnn> External Ram start location
--xram-size <nnnn> External Ram size
--iram-size <nnnn> Internal Ram size
--xstack-loc <nnnn> External Stack start location
--code-loc <nnnn> Code Segment Location
--code-size <nnnn> Code Segment size
--stack-loc <nnnn> Stack pointer initial value
--data-loc <nnnn> Direct data start location
--idata-loc
--no-optsdcc-in-asm Do not emit .optsdcc in asm
Special options for the mcs51 port:
--model-small internal data space is used (default)
--model-medium external paged data space is used
--model-large external data space is used
--model-huge functions are banked, data in external space
--stack-size Tells the linker to allocate this space for stack
--parms-in-bank1 use Bank1 for parameter passing
--pack-iram Tells the linker to pack variables in internal ram (default)
--no-pack-iram Deprecated: Tells the linker not to pack variables in internal ram
--acall-ajmp Use acall/ajmp instead of lcall/ljmp
--no-ret-without-call Do not use ret independent of acall/lcall
Special options for the z80 port:
--callee-saves-bc Force a called function to always save BC
--portmode= Determine PORT I/O mode (z80/z180)
--asm= Define assembler name (rgbds/asxxxx/isas/z80asm)
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--dataseg <name> use this name for the data segment
--no-std-crt0 For the z80/gbz80 do not link default crt0.rel
--reserve-regs-iy Do not use IY (incompatible with --fomit-frame-pointer)
--oldralloc Use old register allocator
--fno-omit-frame-pointer Do not omit frame pointer
--emit-externs Emit externs list in generated asm
Special options for the z180 port:
--callee-saves-bc Force a called function to always save BC
--portmode= Determine PORT I/O mode (z80/z180)
--asm= Define assembler name (rgbds/asxxxx/isas/z80asm)
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--dataseg <name> use this name for the data segment
--no-std-crt0 For the z80/gbz80 do not link default crt0.rel
--reserve-regs-iy Do not use IY (incompatible with --fomit-frame-pointer)
--oldralloc Use old register allocator
--fno-omit-frame-pointer Do not omit frame pointer
--emit-externs Emit externs list in generated asm
Special options for the r2k port:
--callee-saves-bc Force a called function to always save BC
--portmode= Determine PORT I/O mode (z80/z180)
--asm= Define assembler name (rgbds/asxxxx/isas/z80asm)
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--dataseg <name> use this name for the data segment
--no-std-crt0 For the z80/gbz80 do not link default crt0.rel
--reserve-regs-iy Do not use IY (incompatible with --fomit-frame-pointer)
--oldralloc Use old register allocator
--fno-omit-frame-pointer Do not omit frame pointer
--emit-externs Emit externs list in generated asm
Special options for the r3ka port:
--callee-saves-bc Force a called function to always save BC
--portmode= Determine PORT I/O mode (z80/z180)
--asm= Define assembler name (rgbds/asxxxx/isas/z80asm)
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--dataseg <name> use this name for the data segment
--no-std-crt0 For the z80/gbz80 do not link default crt0.rel
--reserve-regs-iy Do not use IY (incompatible with --fomit-frame-pointer)
--oldralloc Use old register allocator
--fno-omit-frame-pointer Do not omit frame pointer
--emit-externs Emit externs list in generated asm
Special options for the gbz80 port:
-bo <num> use code bank <num>
-ba <num> use data bank <num>
--callee-saves-bc Force a called function to always save BC
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--dataseg <name> use this name for the data segment
--no-std-crt0 For the z80/gbz80 do not link default crt0.rel
Special options for the tlcs90 port:
--callee-saves-bc Force a called function to always save BC
--portmode= Determine PORT I/O mode (z80/z180)
--asm= Define assembler name (rgbds/asxxxx/isas/z80asm)
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--dataseg <name> use this name for the data segment
--no-std-crt0 For the z80/gbz80 do not link default crt0.rel
--reserve-regs-iy Do not use IY (incompatible with --fomit-frame-pointer)
--oldralloc Use old register allocator
--fno-omit-frame-pointer Do not omit frame pointer
--emit-externs Emit externs list in generated asm
Special options for the ez80_z80 port:
--callee-saves-bc Force a called function to always save BC
--portmode= Determine PORT I/O mode (z80/z180)
--asm= Define assembler name (rgbds/asxxxx/isas/z80asm)
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--dataseg <name> use this name for the data segment
--no-std-crt0 For the z80/gbz80 do not link default crt0.rel
--reserve-regs-iy Do not use IY (incompatible with --fomit-frame-pointer)
--oldralloc Use old register allocator
--fno-omit-frame-pointer Do not omit frame pointer
--emit-externs Emit externs list in generated asm
Special options for the ds390 port:
--model-flat24 use the flat24 model for the ds390 (default)
--stack-8bit use the 8bit stack for the ds390 (not supported yet)
--stack-size Tells the linker to allocate this space for stack
--pack-iram Tells the linker to pack variables in internal ram (default)
--no-pack-iram Deprecated: Tells the linker not to pack variables in internal ram
--stack-10bit use the 10bit stack for ds390 (default)
--use-accelerator generate code for ds390 arithmetic accelerator
--protect-sp-update will disable interrupts during ESP:SP updates
--parms-in-bank1 use Bank1 for parameter passing
Special options for the pic16 port:
--pstack-model= use stack model 'small' (default) or 'large'
-y --extended enable Extended Instruction Set/Literal Offset Addressing mode
--pno-banksel do not generate BANKSEL assembler directives
--obanksel= set banksel optimization level (default=0 no)
--denable-peeps explicit enable of peepholes
--no-optimize-goto do NOT use (conditional) BRA instead of GOTO
--optimize-cmp try to optimize some compares
--optimize-df thoroughly analyze data flow (memory and time intensive!)
--asm= Use alternative assembler
--mplab-comp enable compatibility mode for MPLAB utilities (MPASM/MPLINK)
--link= Use alternative linker
--preplace-udata-with= Place udata variables at another section: udata_acs, udata_ovr, udata_shr
--ivt-loc= Set address of interrupt vector table.
--nodefaultlibs do not link default libraries when linking
--use-crt= use <crt-o> run-time initialization module
--no-crt do not link any default run-time initialization module
--debug-xtra show more debug info in assembly output
--debug-ralloc dump register allocator debug file *.d
--pcode-verbose dump pcode related info
--calltree dump call tree in .calltree file
--gstack trace stack pointer push/pop to overflow
--no-warn-non-free suppress warning on absent --use-non-free option
Special options for the pic14 port:
--debug-xtra show more debug info in assembly output
--no-pcode-opt disable (slightly faulty) optimization on pCode
--stack-size sets the size if the argument passing stack (default: 16, minimum: 4)
--no-extended-instructions forbid use of the extended instruction set (e.g., ADDFSR)
--no-warn-non-free suppress warning on absent --use-non-free option
Special options for the TININative port:
--model-flat24 use the flat24 model for the ds390 (default)
--stack-8bit use the 8bit stack for the ds390 (not supported yet)
--stack-size Tells the linker to allocate this space for stack
--pack-iram Tells the linker to pack variables in internal ram (default)
--no-pack-iram Deprecated: Tells the linker not to pack variables in internal ram
--stack-10bit use the 10bit stack for ds390 (default)
--use-accelerator generate code for ds390 arithmetic accelerator
--protect-sp-update will disable interrupts during ESP:SP updates
--parms-in-bank1 use Bank1 for parameter passing
--tini-libid <nnnn> LibraryID used in -mTININative
Special options for the ds400 port:
--model-flat24 use the flat24 model for the ds400 (default)
--stack-8bit use the 8bit stack for the ds400 (not supported yet)
--stack-size Tells the linker to allocate this space for stack
--pack-iram Tells the linker to pack variables in internal ram (default)
--no-pack-iram Deprecated: Tells the linker not to pack variables in internal ram
--stack-10bit use the 10bit stack for ds400 (default)
--use-accelerator generate code for ds400 arithmetic accelerator
--protect-sp-update will disable interrupts during ESP:SP updates
--parms-in-bank1 use Bank1 for parameter passing
Special options for the hc08 port:
--model-small 8-bit address space for data
--model-large 16-bit address space for data (default)
--out-fmt-elf Output executable in ELF format
--oldralloc Use old register allocator
Special options for the s08 port:
--model-small 8-bit address space for data
--model-large 16-bit address space for data (default)
--out-fmt-elf Output executable in ELF format
--oldralloc Use old register allocator
Special options for the stm8 port:
--model-medium 16-bit address space for both data and code (default)
--model-large 16-bit address space for data, 24-bit for code
--codeseg <name> use this name for the code segment
--constseg <name> use this name for the const segment
--out-fmt-elf Output executable in ELF format
open source hardware programmer: https://github.com/free-pdk/easy-pdk-programmer-hardware
There is a message at the bottom of the page: "Software sources can be found here" and then a link.Quoteopen source hardware programmer: https://github.com/free-pdk/easy-pdk-programmer-hardware
I have checked it, it has only the hardware files, where is the software files for the STM32 MCU and also the PC side software
The only question I have is some odd behaviour I found.
If I use aborted write cycle to read chip ID I get 0xA16 but if I use second read cycle I always get 0x50B which is obviously shifted by a bit to the right.
So my question is which is actually right ID? Who said it should be 0xA16 and not 0x50B?
There is a message at the bottom of the page: "Software sources can be found here" and then a link.Thanks FrankBuss :-+
Hi
Probably this is very lame question here but still I need some help from experts. I have written blinky program in FPPA IDE and now want to burn code. But problem is I dont see .PDK file. I see only .c, .pre, .prj files.
Can you please let me know what i am missing.
I have chips and writer. No ICE.
make all
make all
cd lib/argp-standalone-1.3 && sh configure
checking for a BSD-compatible install... /usr/bin/install -c
checking whether build environment is sane... yes
checking for gawk... gawk
checking whether make sets $(MAKE)... yes
checking for gcc... gcc
checking for C compiler default output file name... a.exe
checking whether the C compiler works... yes
checking whether we are cross compiling... no
checking for suffix of executables... .exe
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ANSI C... none needed
checking for style of include used by make... GNU
checking dependency style of gcc... gcc3
checking whether make sets $(MAKE)... (cached) yes
checking for ranlib... ranlib
checking for gcc... (cached) gcc
checking whether we are using the GNU C compiler... (cached) yes
checking whether gcc accepts -g... (cached) yes
checking for gcc option to accept ANSI C... (cached) none needed
checking dependency style of gcc... (cached) gcc3
checking how to run the C preprocessor... gcc -E
checking for egrep... grep -E
checking for ANSI C header files... yes
checking for sys/types.h... yes
checking for sys/stat.h... yes
checking for stdlib.h... yes
checking for string.h... yes
checking for memory.h... yes
checking for strings.h... yes
checking for inttypes.h... yes
checking for stdint.h... yes
checking for unistd.h... yes
checking limits.h usability... yes
checking limits.h presence... yes
checking for limits.h... yes
checking malloc.h usability... yes
checking malloc.h presence... yes
checking for malloc.h... yes
checking for unistd.h... (cached) yes
checking for an ANSI C-conforming const... yes
checking for inline... inline
checking for size_t... yes
checking for __attribute__... no
checking for working alloca.h... yes
checking for alloca... yes
checking for vprintf... yes
checking for _doprnt... no
checking for strerror... yes
checking for mempcpy... no
checking for strndup... no
checking for strchrnul... no
checking for putc_unlocked('x', stdout)... no
checking for flockfile... no
checking for fputs_unlocked... no
checking for fwrite_unlocked... no
checking for strdup... yes
checking for asprintf... no
checking whether program_invocation_name is declared... no
checking whether program_invocation_short_name is declared... no
configure: creating ./config.status
config.status: creating Makefile
config.status: creating testsuite/Makefile
config.status: creating config.h
config.status: config.h is unchanged
config.status: executing depfiles commands
C:/Program Files/Git/mingw64/bin/make -C lib/argp-standalone-1.3
make[1]: Entering directory 'C:/Users/ASiDesigner/Desktop/easy-pdk-programmer-software-master/easy-pdk-programmer-software-master/lib/argp-standalone-1.3'
C:/Program Files/Git/mingw64/bin/make all-recursive
make[2]: Entering directory 'C:/Users/ASiDesigner/Desktop/easy-pdk-programmer-software-master/easy-pdk-programmer-software-master/lib/argp-standalone-1.3'
Making all in .
/usr/bin/sh: line 11: C:/Program: No such file or directory
make[2]: *** [Makefile:325: all-recursive] Error 1
make[2]: Leaving directory 'C:/Users/ASiDesigner/Desktop/easy-pdk-programmer-software-master/easy-pdk-programmer-software-master/lib/argp-standalone-1.3'
make[1]: *** [Makefile:215: all] Error 2
make[1]: Leaving directory 'C:/Users/ASiDesigner/Desktop/easy-pdk-programmer-software-master/easy-pdk-programmer-software-master/lib/argp-standalone-1.3'
make: *** [Makefile:33: lib/argp-standalone-1.3/libargp.a] Error 2
I have installed mingw on my windows machine and added the PATH to environment variables. also I have added make to my Git Bash!
How should I compile the PC software? I use this and I got errors
Code: [Select]make all
...
make[2]: Entering directory 'C:/Users/ASiDesigner/Desktop/easy-pdk-programmer-software-master/easy-pdk-programmer-software-master/lib/argp-standalone-1.3'
Making all in .
/usr/bin/sh: line 11: C:/Program: No such file or directory
make[2]: *** [Makefile:325: all-recursive] Error 1
...
FYI, I ventured out and reviewed all sub $0.10 microcontrollers on LCSC. I hope it's somewhat useful:
https://cpldcpu.wordpress.com/2019/08/12/the-terrible-3-cent-mcu/ (https://cpldcpu.wordpress.com/2019/08/12/the-terrible-3-cent-mcu/)
from usb1 import *
from libusb1 import *
import struct
CMD_START = 1
PDK_READ = 6
ctx = USBContext()
dev = ctx.getByVendorIDAndProductID(0x16C0, 0x05DC)
handle = dev.open()
with handle.claimInterface(0):
print(handle.getProduct())
devId, = struct.unpack("h", handle.controlRead(LIBUSB_REQUEST_TYPE_VENDOR, CMD_START, PDK_READ, 0, 2))
print('Device ID: %03X' % devId)
handle.close()
It looks like this is NOT an EASYPDK programmer. It shows "xProg V1.0" and "www.ASiDesigner.com" on the PCB but no sign of "freepdk" or "easpdkprog".Thanks JS, it's just a redesign and I did it myself, it's for personal use! :)
Is there someone willing to sell an assembled programmer for the PMS150C? Official one seems very unavailable.It's open source, you can build it! ^-^
QuoteIs there someone willing to sell an assembled programmer for the PMS150C? Official one seems very unavailable.It's open source, you can build it! ^-^
mine has some issues, if I could solve them I can send you one.
I have installed Ubuntu on Virtual-box, I'm new to Linux, so how should I compile EASYPDK for windows?
Quoteopen source hardware programmer: https://github.com/free-pdk/easy-pdk-programmer-hardware
I have checked it, it has only the hardware files, where is the software files for the STM32 MCU and also the PC side software
Because some people have trouble compiling on/for Windows, I added automatic builds (using travis-ci) to the freepdk github repository.
Every commit will now build the software for all 3 platforms (Linux/Mac/Windows) and check for errors.
Tags will automatically create ZIP files with the compiled binaries for all 3 platforms, available under "releases".
I created a temporary tag "1.1-development" from development branch. Here you can find the 1.1-development (work in progress) binaries for all 3 platforms:
https://github.com/free-pdk/easy-pdk-programmer-software/releases
Have fun,
JS
Quoteopen source hardware programmer: https://github.com/free-pdk/easy-pdk-programmer-hardware
I have checked it, it has only the hardware files, where is the software files for the STM32 MCU and also the PC side software
I just tried to get this board made and it's in a 4x1 panel format, but only one of the boards is populated. Kinda annoying, can this be updated to just be a single non-panelised PCB?
Looks like no original PCB file available?
I don't want to edit the gerber files so I'll just get the panel made as is for testing.
I just tried to get this board made and it's in a 4x1 panel format, but only one of the boards is populated. Kinda annoying, can this be updated to just be a single non-panelised PCB?
Looks like no original PCB file available?In case you want to modify the design you can find the complete source schematics/pcb design files in the github repository (look in easyeda folder)
Yep, JLC rejected my PCB, Can I get a single PCB gerber files or the original PCB file please? (KiCAD/Eagle/Altium?) Thanks.
Yep, JLC rejected my PCB, Can I get a single PCB gerber files or the original PCB file please? (KiCAD/Eagle/Altium?) Thanks.
This is very odd. Several users used the exact same gerber.zip file to order from JLCPCB before and it was accepted.
What was the exact reason for the rejection?
Sorry to tell you that the size of your panel is too small to be made with v-cut, it needs to 7 *7 cm at least to get through the v-cut machine, could you please kindly check? And you can add edge rail to the the boards as the attachment ,then it can be produced by V-cut ,thank you !
In the mean time I will create a non panelaized Gerber and put it to the github project page.
Edit: https://github.com/free-pdk/easy-pdk-programmer-hardware/tree/master/pcb also contains a single board gerber now: "Gerber_EASYPDKPROG_PCB12_NoSilk.zip"
It's because the gerber looks like a panel with V score, and they said:QuoteSorry to tell you that the size of your panel is too small to be made with v-cut, it needs to 7 *7 cm at least to get through the v-cut machine, could you please kindly check? And you can add edge rail to the the boards as the attachment ,then it can be produced by V-cut ,thank you !
Dave you can check out my Altium project!
JS, I have compiled the ARM program and flashed the easyPaduk, but unfortunately it says the firmware is a mismatch! (I have flashed the programmer with the new Bin file)
also can you please update the make file for the PC side software to generate the .exe file for windows too( I mean inside ubuntu)
Thanks JS, I managed to flash the Dev branch to the ARM and now it's working, But still only probing is working |O |O |O any Idea what might goes wrong?
Hi,
To understand the register mappings on different PDK CPU types better I created a list (based on include files from original IDE).
https://github.com/free-pdk/fppa-pdk-documentation/blob/master/PDK_register_mapping_scroll_right.csv
Attached is a colorful version as PNG from it.
Based on this info (most registers jump around for different types and only a few number remains static) I think the best idea would be to create one include file per supported processor like:
pdk/pmc150c.h
pdk/pfs154.h
pdk/pfs173.h
...
Hi,
To understand the register mappings on different PDK CPU types better I created a list (based on include files from original IDE).
https://github.com/free-pdk/fppa-pdk-documentation/blob/master/PDK_register_mapping_scroll_right.csv
Attached is a colorful version as PNG from it.
Based on this info (most registers jump around for different types and only a few number remains static) I think the best idea would be to create one include file per supported processor like:
pdk/pmc150c.h
pdk/pfs154.h
pdk/pfs173.h
...
I fully agree with this approach. I wonder, has anybody already been looking into this? Right now, I am cleaning up some of my old examples. So far I have defined everything in line.
#ifndef __PMS150C_H__
#define __PMS150C_H__
#include "pdkcommon.h"
//set calibration macros
#define EASY_PDK_CALIBRATE_IHRC EASY_PDK_CALIBRATE_IHRC_H8
#define EASY_PDK_CALIBRATE_ILRC EASY_PDK_CALIBRATE_IHRC_L8
//IO register definitions
//__sfr __at(0x00) _flag;
//0x01
//__sfr __at(0x02) _sp;
__sfr __at(0x03) _clkmd;
__sfr __at(0x04) _inten;
__sfr __at(0x05) _intrq;
__sfr __at(0x06) _t16m;
//0x07
//0x08
__sfr __at(0x09) _tm2b;
__sfr __at(0x0a) _eoscr;
__sfr __at(0x0b) _ihrcr;
__sfr __at(0x0c) _integs;
__sfr __at(0x0d) _padier;
//0x0e
//0x0f
__sfr __at(0x10) _pa;
__sfr __at(0x11) _pac;
__sfr __at(0x12) _paph;
//0x13
//0x14
//0x15
//0x16
__sfr __at(0x17) _tm2s;
//0x18
__sfr __at(0x19) _bgtr;
__sfr __at(0x1a) _gpcc;
__sfr __at(0x1b) _misc;
__sfr __at(0x1c) _tm2c;
__sfr __at(0x1d) _tm2ct;
__sfr __at(0x1e) _gpcs;
__sfr __at(0x1f) _ilrcr;
//T16C register
__sfr16 _t16c;
//clkmd definitions
#define CLKMD_ENABLE_PA5RST 0x01
#define CLKMD_ENABLE_WATCHDOG 0x02
#define CLKMD_ENABLE_ILRC 0x04
#define CLKMD_ENABLE_IHRC 0x10
#define CLKMD_IHRC_DIV2 0x20
#define CLKMD_IHRC_DIV4 0x00
#define CLKMD_IHRC_DIV8 0x28
#define CLKMD_IHRC_DIV16 0x08
#define CLKMD_IHRC_DIV32 0x68
#define CLKMD_IHRC_DIV64 0x88
#define CLKMD_ILRC 0xe0
#define CLKMD_ILRC_DIV4 0xc0
//interrupt enable definitions
#define INTEN_PA0 0x01
#define INTEN_T16 0x04
#define INTEN_COMP 0x10
#define INTEN_TM2 0x40
//interrupt request definitions
#define INTRQ_PA0 0x01
#define INTRQ_T16 0x04
#define INTRQ_COMP 0x10
#define INTRQ_TM2 0x40
//tm16 definitions
#define T16_INTSRC_8BIT 0x00
#define T16_INTSRC_9BIT 0x01
#define T16_INTSRC_10BIT 0x02
#define T16_INTSRC_11BIT 0x03
#define T16_INTSRC_12BIT 0x04
#define T16_INTSRC_13BIT 0x05
#define T16_INTSRC_14BIT 0x06
#define T16_INTSRC_15BIT 0x07
#define T16_CLK_DIV1 0x00
#define T16_CLK_DIV4 0x08
#define T16_CLK_DIV16 0x10
#define T16_CLK_DIV64 0x18
#define T16_CLK_DISABLE 0x00
#define T16_CLK_SYSCLK 0x20
#define T16_CLK_PA4_FALL 0x60
#define T16_CLK_IHRC 0x80
#define T16_CLK_ILRC 0xC0
#define T16_CLK_PA0_FALL 0xE0
//eosc definitions
#define EOSC_LVD_BANDGAP_SHUTDOWN 0x01
//integs definitions
#define INTEGS_PA0_BOTH 0x00
#define INTEGS_PA0_RISING 0x01
#define INTEGS_PA0_FALLING 0x02
#define INTEGS_T16_RISING 0x00
#define INTEGS_T16_FALLING 0x04
#define INTEGS_COMP_BOTH 0x00
#define INTEGS_COMP_RISING 0x40
#define INTEGS_COMP_FALLING 0x80
//padie definitions
#define PADIE_PA0_WAKEUP_ENABLE 0x01
#define PADIE_PA3_WAKEUP_ENABLE 0x08
#define PADIE_PA4_WAKEUP_ENABLE 0x10
#define PADIE_PA5_WAKEUP_ENABLE 0x20
#define PADIE_PA6_WAKEUP_ENABLE 0x40
#define PADIE_PA7_WAKEUP_ENABLE 0x80
//misc definitions
#define MISC_WATCHDOG_8K_ILRC 0x00
#define MISC_WATCHDOG_16K_ILRC 0x01
#define MISC_WATCHDOG_64K_ILRC 0x02
#define MISC_WATCHDOG_256K_ILRC 0x03
#define MISC_LVR_DISABLE 0x04
#define MISC_FAST_WAKEUP_ENABLE 0x20
//tm2c definitions
#define TM2C_CLK_DISABLE 0x00
#define TM2C_CLK_SYSCLK 0x10
#define TM2C_CLK_IHRC 0x20
#define TM2C_CLK_EOSC 0x30
#define TM2C_CLK_ILRC 0x40
#define TM2C_CLK_COMPOUT 0x50
#define TM2C_CLK_PA0_RISE 0x80
#define TM2C_CLK_PA0_FALL 0x90
#define TM2C_CLK_PB0_RISE 0xA0
#define TM2C_CLK_PB0_FALL 0xB0
#define TM2C_CLK_PA4_RISE 0xC0
#define TM2C_CLK_PA4_FALL 0xD0
#define TM2C_OUT_DISABLE 0x00
#define TM2C_OUT_PB2 0x04
#define TM2C_OUT_PA3 0x08
#define TM2C_OUT_PB4 0x0C
#define TM2C_MODE_PERIOD 0x00
#define TM2C_MODE_PWM 0x02
#define TM2C_INVERT_OUT 0x01
//tm2s definitions
#define TM2S_PWM_RES_8BIT 0x00
#define TM2S_PWM_RES_6BIT 0x80
#define TM2S_PRESCALE_NONE 0x00
#define TM2S_PRESCALE_DIV4 0x20
#define TM2S_PRESCALE_DIV16 0x40
#define TM2S_PRESCALE_DIV64 0x60
//gpcc definitions
#define GPCC_COMP_PLUS_VINT 0x00
#define GPCC_COMP_PLUS_PA4 0x01
#define GPCC_COMP_MINUS_PA3 0x00
#define GPCC_COMP_MINUS_PA4 0x02
#define GPCC_COMP_MINUS_BANDGAP_1V2 0x04
#define GPCC_COMP_MINUS_VINT_R 0x06
#define GPCC_COMP_MINUS_PA6 0x08
#define GPCC_COMP_MINUS_PA7 0x0A
//gpcs definitions
#define GPCS_COMP_CASE1 0x00
#define GPCS_COMP_CASE2 0x10
#define GPCS_COMP_CASE3 0x20
#define GPCS_COMP_CASE4 0x30
#define GPCS_COMP_WAKEUP_ENABLE 0x40
#define GPCS_COMP_OUTPUT_PA0 0x80
//__PMS150C_H__
#ifndef __PDKCOMMON_H__
#define __PDKCOMMON_H__
//macros so we can use defines in assembler strings
#define _STRINGIFY(x)
#define _ASMV(x) "_"_STRINGIFY(x)
#define _ASMD(x) _STRINGIFY(x)
//definitions for built in opcodess
#define __engint() __asm__("engint\n")
#define __disgint() __asm__("disgint\n")
#define __stopsys() __asm__("stopsys\n")
#define __stopexe() __asm__("stopexe\nnop\n")
#define __set0(x,y) __asm__("set0 "_ASMV(x)", #"_ASMD(y)"\n")
#define __set1(x,y) __asm__("set1 "_ASMV(x)", #"_ASMD(y)"\n")
//macros for clock setup
#define EASY_PDK_INIT_SYSCLOCK_8MHZ() {_clkmd=CLKMD_ENABLE_ILRC|CLKMD_ENABLE_IHRC|CLKMD_IHRC_DIV2;}
#define EASY_PDK_INIT_SYSCLOCK_4MHZ() {_clkmd=CLKMD_ENABLE_ILRC|CLKMD_ENABLE_IHRC|CLKMD_IHRC_DIV4;}
#define EASY_PDK_INIT_SYSCLOCK_2MHZ() {_clkmd=CLKMD_ENABLE_ILRC|CLKMD_ENABLE_IHRC|CLKMD_IHRC_DIV8;}
#define EASY_PDK_INIT_SYSCLOCK_1MHZ() {_clkmd=CLKMD_ENABLE_ILRC|CLKMD_ENABLE_IHRC|CLKMD_IHRC_DIV16;}
#define EASY_PDK_INIT_SYSCLOCK_512kHz() {_clkmd=CLKMD_ENABLE_ILRC|CLKMD_ENABLE_IHRC|CLKMD_IHRC_DIV32;}
//place holder for EASYPDK serial inserted from easypdkprog
#define EASY_PDK_SERIAL(sname) static const uint8_t sname[8] = {'F','P','S','E','R','I','A','L'}
//place holder for EASYPDK calibrations executed / replaced by easypdkprog
#define EASY_PDK_CALIBRATE_IHRC_H8(frequency,millivolt) \
__asm__( \
"and a, #'H' \n"\
"and a, #'8' \n"\
"and a, #("#frequency") \n"\
"and a, #("#frequency">>8) \n"\
"and a, #("#frequency">>16) \n"\
"and a, #("#frequency">>24) \n"\
"and a, #("#millivolt") \n"\
"and a, #("#millivolt">>8) \n"\
)
#define EASY_PDK_CALIBRATE_ILRC_L8(frequency,millivolt) \
__asm__( \
"and a, #'L' \n"\
"and a, #'8' \n"\
"and a, #("#frequency") \n"\
"and a, #("#frequency">>8) \n"\
"and a, #("#frequency">>16) \n"\
"and a, #("#frequency">>24) \n"\
"and a, #("#millivolt") \n"\
"and a, #("#millivolt">>8) \n"\
)
#define EASY_PDK_CALIBRATE_IHRC_H9(frequency,millivolt) \
__asm__( \
"and a, #'H' \n"\
"and a, #'9' \n"\
"and a, #("#frequency") \n"\
"and a, #("#frequency">>8) \n"\
"and a, #("#frequency">>16) \n"\
"and a, #("#frequency">>24) \n"\
"and a, #("#millivolt") \n"\
"and a, #("#millivolt">>8) \n"\
"and a, #0 \n"\
)
#define EASY_PDK_CALIBRATE_ILRC_L9(frequency,millivolt) \
__asm__( \
"and a, #'L' \n"\
"and a, #'9' \n"\
"and a, #("#frequency") \n"\
"and a, #("#frequency">>8) \n"\
"and a, #("#frequency">>16) \n"\
"and a, #("#frequency">>24) \n"\
"and a, #("#millivolt") \n"\
"and a, #("#millivolt">>8) \n"\
"and a, #0 \n"\
)
//__PDKCOMMON_H__
#include <stdint.h>
#include "pms150c.h"
unsigned char _sdcc_external_startup(void)
{
EASY_PDK_INIT_SYSCLOCK_8MHZ(); //use 8MHz to save power
EASY_PDK_CALIBRATE_IHRC(8000000,3300); //tune SYSCLK to 8.0MHz @ 3.300V
return 0; //perform normal initialization
}
void main(void)
{
for(;;)
{
//YOUR CODE HERE
}
}
But I managed to install MSYS2 on my machine and finally it could compile the code, But there is something very weird! the code just does not run |O |O |O also I could compile the easypdkprogtest program too, but It can not run either!
Thanks JS, Now the program would run from the MSYS2 shell, The voltages are a bit high
They are 5.17v and 5.18v with my voltmeter, are they in expected range?how should I calculate the offset and change.
:20000000022F8201782F8301012F9101101E101C0630FF2F820B830B82110C3083110C30C7
:020020007A0064
:00000001FF
I spent some time tinkering with a toolchain setup for SDCC and easypdkprog. You can find my work in progress here:
https://github.com/cpldcpu/SimPad/tree/master/Toolchain
Notable findings:
Includes
- I wrote a small python script that automatically generates include files from the CSV that JS posted a while ago. This should greatly reduce the work of creating include files for all MCUS. you can find it at
https://github.com/cpldcpu/SimPad/tree/master/Toolchain/util
- The goal is currently to have one master "io.h" file that automatically includes the architecture specific files.
- The architecture specific includes contain information about i/o register locations. The descriptions of the individual bits seem to be universial for all devices and have therefore been moved into a common file.
- I also introduced F_CPU to allow for a proper delay function.
Makefile
- Unversial makefile added, based on STM8-bare-min. Everything is automated now.
SDCC
- I was pleasantly surprised to learn that SDCC can infer SET0/SET1 now. Therefore it is not necessary to introduce specific macros for set0/set1
- Since SDCC implements a very unusual way of defining SFRs, intellisense/vscode is not able to identify the register definitions. This is somewhat unfortunate. There is an open ticked about this at the vscode github since last year, but apparently it is not a priority. Is there any workaround? Doing it like AVR-GCC ("__sfr(register)") would allow using defines, which is more compatible to intellisense.
- It does not seem to be possible to use local labels in inline assembler? This is inconvenient because it does not allow inlining of functions with assembler code when they use labels...
- It appears the -p options is not yet supported for the PDK architecture? This would be very useful, because it would allow distinguishing different processors from the makefile. May use a define as a workaround for now...
Easypdkprog
does not write the last byte of the ihx for some reason. This is only noticable when linking several files. Already submitted an issue.
I will add more examples soon. Also planning to integrates JS autocalibration code.
Let me know what you think. There are still many things to be clarified regarding naming etc.
@tim_: I have used your blinkyasm example for testing my programmer. However, while the LED turns ON, it never turns back off. I've tried commenting out the wait busy loop and I can see now with the scope the GPIO toggling. Could you tell me if the IHX file you are getting for that matches mine?Code: [Select]:20000000022F8201782F8301012F9101101E101C0630FF2F820B830B82110C3083110C30C7
:020020007A0064
:00000001FF
I have just compiled it using the SDCC snapshot for today (1st September 2019), so I am not sure if the compilation is broken.
My other guessing is that the SRAM is bad in this chip (hence the DCSN never reaches zero to leave). Has anybody else experienced something like this in its Padauk IC, where the CPU is indeed working but the SRAM is dead?
0000: 2F02 mov A,#$02
0001: 0182 movio $02,A
0002: 2F78 mov A,#$78
0003: 0183 movio $03,A
0004: 2F01 mov A,#$01
0005: 0191 movio $11,A
0006: 1E10 set1io $10,#0
0007: 1C10 set0io $10,#0
0008: 3006 goto $0006
0009: 2FFF mov A,#$FF
000A: 0B82 mov $02,A
000B: 0B83 mov $03,A
000C: 1182 dzsn $02
000D: 300C goto $000C
000E: 1183 dzsn $03
000F: 300C goto $000C
0010: 007A ret
I think auto generating the IO header files is not the way to go.
The most work was to add all the bit definitions for the specific IO registers (see "pms150.h" from above).
This is needed to do simple things like: _clkmd=CLKMD_ENABLE_ILRC | CLKMD_ENABLE_IHRC | CLKMD_IHRC_DIV2;
Also since SDCC defines "_sp" and "_flags" internally I think we should keep the "_" prefix for all other registers as well
The last byte missing problem from easypdkprog seems odd and it does not happen to me. Maybe programming the last byte was not working on your hardware and some tweaking of the code is required to make this more reliable.
So I have mostly given up on getting the programmer running on the ATtiny - it's just not capable of doing so much realtime stuff at once - either you break USB, or you break the SMPS regulation, you can't have both at once.
Therefore, I have switched to plan B - using an Arduino as development platform instead. And it turns out this is probably the way I should have chosen from the start.
While certainly not the most professional-looking alternative, it sure is the easiest to build. It uses as little components as possible.
The schematic is attached, and the firmware along with upload scripts can be found in https://github.com/socram8888/ArduinoPDKProgrammer. This already supports uploading and verifying IHX files, as those generated by SDCC.
I think auto generating the IO header files is not the way to go.It should be possible to just ship the header files with SDCC (this already happens for some MCS-51 derivatives and some HC08 devices). They would live in device/include/pdk13, device/include/pdk14, device/include/pdk15.
The most work was to add all the bit definitions for the specific IO registers (see "pms150.h" from above).
This is needed to do simple things like: _clkmd=CLKMD_ENABLE_ILRC | CLKMD_ENABLE_IHRC | CLKMD_IHRC_DIV2;
Also since SDCC defines "_sp" and "_flags" internally I think we should keep the "_" prefix for all other registers as well
yeah, I was unsure about this. There does not seem to be any general convention for SFR naming. SDCC also uses the _xxx naming for internal variable names in SRAM, so it seems to be a bit confusing to use the same conventions for memory and SFR. I guess the _ prefix is added to avoid namespace collisions.
Well, the thinking here is very simple: Padauk seems to reuse specific peripheral modules, but moves them around in the I/O space. The description of the individual registers can be done once on a common file, this does not need to be auto generated. To cope with padauk moving around peripheral modules in the address space, it is very convenient to auto generate the register addresses. This also makes global renaming much easier.
BTW did you put C1 yet?!What C1? do you mean a cap on VCC and GND and the PFS173? something like this?
See disassembly of your hex file below. For some reason it is missing calls to the delay routine?!?Sorry, I had removed call to see if a loop without any call worked fine (which it did, it worked and I could see the pin toggling on a scope) and forgot to recompile to paste it here.
:20000000022F8201782F8301012F9101101E0B38101C0B380630FF2F820B830B82110E300F
:0600200083110E307A008E
:00000001FF
0000: 2F02 mov A,#$02
0001: 0182 movio $02,A
0002: 2F78 mov A,#$78
0003: 0183 movio $03,A
0004: 2F01 mov A,#$01
0005: 0191 movio $11,A
0006: 1E10 set1io $10,#0
0007: 380B call $000B
0008: 1C10 set0io $10,#0
0009: 380B call $000B
000A: 3006 goto $0006
000B: 2FFF mov A,#$FF
000C: 0B82 mov $02,A
000D: 0B83 mov $03,A
000E: 1182 dzsn $02
000F: 300E goto $000E
0010: 1183 dzsn $03
0011: 300E goto $000E
0012: 007A ret
I would suggest you use the blinky example from the toolchain folder, as posted above. Also, always check *.asm files or use the dissembler to double check. The old examples heavily rely on workarounds to be able to cope with bugs in the very early versions of SDCC. I will remove them soon.Okay, I will try this evening with the ones from toolchain, and using another IC to rule out that the chip is damaged. Many thanks.
QuoteBTW did you put C1 yet?!What C1? do you mean a cap on VCC and GND and the PFS173? something like this?
See disassembly of your hex file below. For some reason it is missing calls to the delay routine?!?Sorry, I had removed call to see if a loop without any call worked fine (which it did, it worked and I could see the pin toggling on a scope) and forgot to recompile to paste it here.
This is it with the call:Code: [Select]:20000000022F8201782F8301012F9101101E0B38101C0B380630FF2F820B830B82110E300F
:0600200083110E307A008E
:00000001FF
I am getting the following disassembly:
I am getting the following disassembly:Code: [Select]0000: 2F02 mov A,#$02
0001: 0182 movio $02,A
0002: 2F78 mov A,#$78
0003: 0183 movio $03,A
0004: 2F01 mov A,#$01
0005: 0191 movio $11,A
0006: 1E10 set1io $10,#0
0007: 380B call $000B
0008: 1C10 set0io $10,#0
0009: 380B call $000B
000A: 3006 goto $0006
000B: 2FFF mov A,#$FF
000C: 0B82 mov $02,A
000D: 0B83 mov $03,A
000E: 1182 dzsn $02
000F: 300E goto $000E
0010: 1183 dzsn $03
0011: 300E goto $000E
0012: 007A ret
For me it looks like you trash your stack...
It should be possible to just ship the header files with SDCC (this already happens for some MCS-51 derivatives and some HC08 devices).
struct __pdk_bits
{
unsigned int bit0:1;
unsigned int bit1:1;
unsigned int bit2:1;
unsigned int bit3:1;
unsigned int bit4:1;
unsigned int bit5:1;
unsigned int bit6:1;
unsigned int bit7:1;
};
#define PORTA4 ((struct __pdk_bits *)(&pa))->bit4
#define LEDPIN PA4
unsigned char _sdcc_external_startup(void)
{
clkmd = CLKMD_IHRC_DIV2|CLKMD_ENABLE_IHRC; // 8 Mhz main clock
return 0; // perform normal initialization
}
void main(void)
{
pac |= _BV(LEDPIN); // Use this exact syntax to infer set0/set1
for (;;) {
// pa ^= _BV(LEDPIN); // Toggle LED
PORTA4 ^=1; // works, but creates 11 instructions
delay_ms(500);
PORTA4 = 1; // creates broken assembler code
}
}
; blinky.c: 38: PORTA4 ^=1; // works, but creates 11 instructions
mov a, _pa+0
swap a
and a, #0x01
xor a, #0x01
clear p
sr a
mov a, _pa+0
and a, #0xef
t0sn f, c
or a, #0x10
mov _pa+0, a
; blinky.c: 39: delay_ms(500);
mov a, #0xf4
mov _delay_ms_PARM_1+0, a
mov a, #0x01
mov _delay_ms_PARM_1+1, a
call _delay_ms
; blinky.c: 40: PORTA4 = 1; // creates broken assembler code
mov a, #0x10
or _pa+0, a
goto 00102$
...Many thanks! After setting the stack address to something else I got the assembly blink working.
:16000000102F8201782F8301012F9101101E2038101C20380630FB
:10004000FF2F820B830B82112330831123307A0020
:00000001FF
:020020007B0063
:1000000000000113042F0128FE2C82011D3812303C
:16002400022F800B1930002F80030012022F022800171530113005
:0200220020308C
:20003A00782F83010002012F9101302F820B752F830B820F0129800B830F6100830B80133F
:20005A00820B8013800E002A2630002F9001302F820B752F830B820F0129800B830F610041
:16007A00830B8013820B8013800E002A3830012F900122307A0082
:00000001FF
:020020007B0063
:1000000000000113042F0328FE2C82011D3812303A
:16002400022F800B1930002F80030012022F022800171530113005
:0200220020308C
:1C003A00302F83010002111FD001102E9001F42F820B012F830B2B3821307A0059
:20005600820F840B830F850B850F800B840F84128510800E002B42300013800F2829401AF3
:140076002F30322F0129001A3D30001238307A0000007A0097
:00000001FF
It should be possible to just ship the header files with SDCC (this already happens for some MCS-51 derivatives and some HC08 devices).
The HC08 headers are actually quite interesting. They use bitfield structs to declare individual bits in the I/O ports. I tried to do the same for the PDK14, but got mixed results, see code below.
"PORTA4" is defined as bit4 on PA.
PORTA4^=1 creates functional, but very inefficient code. (11 instructions instead of 3)
PORTA4=1/PORTA4|=1/PORTA4&=~1 creates broken code and SDCC exits with an assembler error.
I mean C1 on your programmer board (I think it is for the high voltage output). Also Y1 (the oscillator) was missing in the picture from you. Did you change the firmware to use the HSI48 clock source instead of the external OSC?I have soldered a 47uF 1206 ceramic cap for the 15V output already. Also I have not soldered a 8MHz crystal yet, because I do not have stock yet, Since the programmer can talk to PC, it means it can generate the USB 48MHz clock internally, does this may be a problem?
The cap you added on the PADAUK MCU is contra productive since it might require different timing for VPP / VDD phase of programming (remove it for testing).
JS
So far, I only used and tested access via the __sfr keyword (as in my examples on https://github.com/free-pdk/sdcc-pdk-code-examples). I don't know if the struct / bit-field approach canbe combined with __sfr.
Besides, at least for me, this is just a matter of trying exotic, chinese stuff rather than getting anything serious working on the platform. It's like that evening you spend coding in Brainfuck just for fun, except on the hardware side.
/* simple brainfuck interpreter */
/* 20 April 2006 */
/* Daniel B. Cristofani */
/* http://www.brainfuck.org/ */
#include <stdio.h>
#include <stdlib.h>
#define ARRAYSIZE 65536
#define MAXCODESIZE 65536
//For simplicity, we'll use statically allocated arrays with matching indices.
int stack[MAXCODESIZE], stackp; //to store locations of still-unmatched '['s.
char code[MAXCODESIZE]; int codep, codelength; //copy of the program we'll read into memory.
short int array[ARRAYSIZE], memp; //the memory used by the brainfuck program.
int targets[MAXCODESIZE]; //to save matching '[' for each ']' and vice versa.
int c;
FILE *prog;
int main(int argc, char **argv){
if (argc > 2) fprintf(stderr, "Too many arguments.\n"), exit(1);
if (argc < 2) fprintf(stderr, "I need a program filename.\n"), exit(1);
if(!(prog = fopen(argv[1], "r"))) fprintf(stderr,"Can't open the file %s.\n", argv[1]),exit(1);
codelength = fread(code, 1, MAXCODESIZE, prog);
fclose(prog);
for(codep=0; codep<codelength; codep++){
if (code[codep]=='[') stack[stackp++]=codep;//put each '[' on the stack
if (code[codep]==']'){ //If we meet a ']',
if(stackp==0){ //and there is no '[' left on the stack, it's an error.
fprintf(stderr,"Unmatched ']' at byte %d.", codep), exit(1);
} else {
--stackp; //if there is one, we take the matching '[' from the stack top,
targets[codep]=stack[stackp]; //save it as the match for the current ']',
targets[stack[stackp]]=codep; //and save the current ']' as the match for it.
}
}
}
if(stackp>0){ //Any unmatched '['s still left on the stack are an error too.
fprintf(stderr,"Unmatched '[' at byte %d.", stack[--stackp]), exit(1);
}
for(codep=0;codep<codelength;codep++){//Everything is okay; we start executing the program.
switch(code[codep]){
case '+': array[memp]++; break;
case '-': array[memp]--; break;
case '<': memp--; break;
case '>': memp++; break;
case ',': if((c=getchar())!=EOF) array[memp]=c=='\n'?10:c; break;
case '.': putchar(array[memp]==10?'\n':array[memp]); break;
case '[': if(!array[memp]) codep=targets[codep]; break;
case ']': if(array[memp]) codep=targets[codep]; break;
}
}
exit(0);
}
I'm trying to buy the parts from the BOM file in the github and it seems it's for LCSC, but when I load the CSV into LCSC using their BOM tool it's just a mess.
Anyone know why?
It is because it's semicolon delimited instead of coma delimited?
Thanks.
I downloaded the LCSC BOm template and manually copied everything over and it's still a mess when I import it into LCSC |O
Turns out there is a bug in the LCSC BOM. It re-loads the previous (incorrect) file even when you try and upload a new one. You have to restart the web page.
XLS BOM attached in LCSC format
JS I made progress! I have soldered a 8MHz crystal to the board and now it can Erase the part ok, But when I read it, it says "Could not read data from programmer"
how to get started with SDCC for PFS173, I see your examples and they are for PFS154, is there something that I should change?
// "Hello, world!" for the Padauk PFS154, to be compiled with SDCC.
// Repeatedly outputs the string "Hello, World!" at 9600 baud on pin 0 of Port A.
// Written by Philipp Klaus Krause in 2019.
// Source code under CC0 1.0.
// Output on PA0 at 1200 baud.
#include <stdbool.h>
#include <stdio.h>
volatile unsigned char sendcounter;
volatile unsigned int senddata;
volatile bool sending;
//PFS173 SFR's
__sfr __at(0x00) flag;
__sfr __at(0x02) sp;
__sfr __at(0x03) clkmd;
__sfr __at(0x04) inten;
__sfr __at(0x05) intrq;
__sfr __at(0x06) t16m;
__sfr __at(0x0a) eoscr;
__sfr __at(0x0b) ihrcr;
__sfr __at(0x0c) integs;
__sfr __at(0x0d) padier;
__sfr __at(0x0e) pbdier;
__sfr __at(0x0f) pcdier;
__sfr __at(0x10) pa;
__sfr __at(0x11) pac;
__sfr __at(0x12) paph;
__sfr __at(0x13) pb;
__sfr __at(0x14) pbc;
__sfr __at(0x15) pbph;
__sfr __at(0x16) pc;
__sfr __at(0x17) pcc;
__sfr __at(0x18) pcph;
__sfr __at(0x19) pbpl;
__sfr __at(0x1a) pcpl;
__sfr __at(0x20) adcc;
__sfr __at(0x21) adcm;
__sfr __at(0x22) adcr;
__sfr __at(0x24) adcrgc;
__sfr __at(0x26) misc;
__sfr __at(0x2b) gpcc;
__sfr __at(0x2c) gpcs;
__sfr __at(0x30) tm2c;
__sfr __at(0x31) tm2ct;
__sfr __at(0x32) tm2s;
__sfr __at(0x33) tm2b;
__sfr __at(0x34) tm3c;
__sfr __at(0x35) tm3ct;
__sfr __at(0x36) tm3s;
__sfr __at(0x37) tm3b;
__sfr __at(0x40) pwmg0c;
__sfr __at(0x41) pwmgclk;
__sfr __at(0x42) pwmg0dth;
__sfr __at(0x43) pwmg0dtl;
__sfr __at(0x44) pwmgcubh;
__sfr __at(0x45) pwmgcubl;
__sfr __at(0x46) pwmg1c;
__sfr __at(0x48) pwmg1dth;
__sfr __at(0x49) pwmg1dtl;
__sfr __at(0x4c) pwmg2c;
__sfr __at(0x4e) pwmg2dth;
__sfr __at(0x4f) pwmg2dtl;
void send_bit(void) __interrupt(0)
{
// Reset interrupt request, proceed only if we had a timer interrupt.
if(!(intrq & 0x40))
{
intrq = 0x00;
return;
}
intrq = 0x00;
if(!sending)
return;
if(senddata & 1)
pa = 0x80;
else
pa = 0x00;
senddata >>= 1;
if(!--sendcounter)
{
sending = false;
inten &= ~0x40;
}
}
int putchar(int c)
{
while(sending);
senddata = (c << 1) | 0x200;
sendcounter = 10;
tm2ct = 0;
sending = true;
inten |= 0x40;
return (c);
}
unsigned char _sdcc_external_startup(void)
{
#ifdef __SDCC_pdk15
ihrcr = *((const unsigned char*)(0x8bed)); // Use PFS173 factory calibration value for IHRC at 16 Mhz.
#else
ihrcr = *((const unsigned char*)(0x87ed)); // Use PFS154 factory calibration value for IHRC at 16 Mhz.
#endif
clkmd = 0x34; // Use IHRC / 2 = 8 Mhz for system clock, disable watchdog.
clkmd = 0x30; // Disable ILRC
return 0; // perform normal initialization
}
void main(void)
{
// Set timer 2 for interrupt for 1200 baud.
tm2c = 0x10; // Use CLK (8 Mhz)
tm2s = 0x06; // Divide by 6 + 1 ~> 1142857 Hz
tm2b = 118; // Divide by 118 + 1 ~> 9604 Hz
inten = 0x40;
__asm
engint
__endasm;
pac = 0x81;
for(;;)
{
printf("ASiDesigner!\r\n");
for(unsigned long int i = 0; i < 150000; i++); // Wait approx. 3s.
}
}
printf("ASiDesigner! %d\r\n",k);
k++;
I have modified the Hello example to output the UART on the PA.7 port, so after starting easypdkprog, it should capture the UART data, it can not get the UART data for now, But I have connected an external UART Bridge(FT230x) to it and it's putting data on the line,There is no "BUG" with easypdkprog. EasyPDK programmer features AUTO-BAUD-DETECTION which requires to send 0x55 as first character followed by at lest 4 extra stop bits (or a small delay) to internally apply the baud rate.
Also I have another question, is it possible to run the device @ 16MHz, I have changed the clkmd =0x54; and it's certainly running @ 8MHz.How did you measure the internal clock speed? Serial port implementation in the sdcc-example program which you used is based on IHRC directly, not on SYSCLK, This means baud rate will not change when you change SYSCLK.
Does the printf accept additional arguments? :-\Yes it does. Most likely the SDCC library is not compiled as "small" so the full printf (including support for width adjustments, leading spaces / zeros / floats / ...) implementation simply does not fit in our ultra ultra small RAM.
Also I have another question, is it possible to run the device @ 16MHz, I have changed the clkmd =0x54; and it's certainly running @ 8MHz.
Is there a way to tell how much flash and ram is used with SDCC? ^-^
Thanks,Is there a way to add it to the command prompt? using make to tell the flash usage?
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
CONST 0000106E 00000B16 = 2838. bytes (REL,CON)
with grep to get the start and size, then add them (e.g. using bc with ibase=16), then divide by 2 to get the size in words.Program Size: Code=15080 RO-data=464 RW-data=284 ZI-data=4704>:D
can we have an OS on PAUDUK, something like this
http://www.femtoos.org/ (http://www.femtoos.org/)
or Am I dreaming ::) ::) ::)
Then we can make a generic make file with the programming command too, also If there is some way of adding the code generated examples for PADAUK IDE for USART send,receive, I2C, SPI, PS2 and ADC it would be very nice too. I think the AVR and winavr was a smart choice at that time and place,(you could easily change the CPU name and FPCU in make file) and also PADAUK are very similar to lower end AVR's, still cheaper tough >:D
Also I have another question, is it possible to run the device @ 16MHz, I have changed the clkmd =0x54; and it's certainly running @ 8MHz.
I don't know. I've asked Padauk, but didn't get a reply yet.
For the PFS173, PMS133 and PMS134, the datasheets are contradictionary on that question. Section 6.3 vs. sections 5.4.2 and 5.4.5.
Regarding a multitaskting OS: I believe that is quite in contradiction to the "FPPA" paradigm. The idea of the Padauk MCUs is to do multithreading with deterministic timing in hardware. That is much more valuable than preemptive multitasking in software and requires little software overhead. Software based preemtive multitasking will not allow you to implement virtual periphery, as it is possible with the FPPA approach.
edit: Of course you could use one FPPA with a multitaksing OS and use other FPPAs for virtual periphery. Things are getting a tad bit complex then.
For those that are a bit more into computer architecture, you can find an introduction to XMOS below. This is based on similar ideas as the padauk FPPA.
https://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.18.4-DSP/HC23.18.410-XMOS-XS1-May_Xmos.pdf (https://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.18.4-DSP/HC23.18.410-XMOS-XS1-May_Xmos.pdf)
Their current FPPA paradigm is not very compatible with C. It looks like they designed a non-parallel instruction set, and then just made some parallel devices.
SDCC currently does not support multiple FPPA.
For efficient parallelism for the Padauk µC, we'd need:
* Stack-pointer-relative addressing and better stack handling (I'm currently running some experiments - when you compile code with --stack-auto for the current architecure, code size triples)
* Synchronization. We would need at least a compare-and-swap instruction, and an xch withindirect addressing mode. Preferably also an idxadd variant of add M, a.
I believe I can add support for multiple FPPA to SDCC. But the generated code will be big and slow. For practical purposes, running a multitasking OS on a single FPPA would be more efficient.
...
That's quite interesting. Is that your video?
I don't think true c-compatible paralellism was their ultimate goal. (They don't even provide a C-compiler...). Obviously that would have added a lot of additional complexity, as you point out.Still, on such a "multicore" µC, you want efficient communication between multiple cores and interrupt handlers, which means efficient lockless atomics, which means a compare-and-swap instruction, preferably with indirect addressing mode.
The idea is probably to have specific tasks assigned to specific threads. For example one thread runs the SPI peripheral, a second one runs a control loop, while the main thread mostly sleeps and does housekeeping/reconfiguration. Each of these would reside in their own memory space with dedicated ressources and would use minimal inter-thread communication via pipes. This would keep synchronization overhead down a lot.
For SDCC, the main challenge would be to allow multiple main function to initialize each FPPA. Maybe that could be dont similar to interrupts? It would be up to the user to ensure that variables are not reused between different threads.
Of course, something needs to be done with the p-register. A very rigid approach would be to clearly assign each function to only one FPPA.
A more pragmatic approach, for now, would be to have C-code always stay on FPPA0 and use assembler for the others...
Regarding preemtive multitasking: Of course this would free up some of the synchronization headache, but then the usefulness would be quite limited compared to using multiple hardware threads.
[[sdcc::fppa(3)]] void f(int)
{
…
}
An FPPA3-specific p3 would be used instead of p when generating code for f.Still, on such a "multicore" µC, you want efficient communication between multiple cores and interrupt handlers, which means efficient lockless atomics, which means a compare-and-swap instruction, preferably with indirect addressing mode.Well, this simply is not a universial multicore architecture. It is to be used within very narrow constraints. For example, if threads are used to emulate virtual periphery, it should be sufficient to work with very simple messaging schemes instead of comprehensive synchronisation. In most cases there will be a clear producer/consumer relationship and it will not be necessary to synchronize two or more threads with the same priority. There is also no real benefit from avoiding active waiting.
mov a,#1
loop:
xch a,lock
ceqsn a,#0
goto loop:
[...critical block...]
clear lock
SDCC is a C compiler, and will aim to comply with the C standard. Where that can't be done efficiently, we still need to be able to comply, but offers alternatives. E.g. when compiling for Padauk, functions are currently not reentrant by default (but reentrancy can be enabled for individual functions using __reentrant, or for the whole program using --stack-auto; it about triples code size though).
For multiple FPPA, my idea would be:
By default make the code work on any FPPA. That means a lock around any use of p. And no longer using p to pass return values (thus 16-bit return values would have to be passed on the stack, like we currently do for return values > 16 bit). Inefficient, but avoids nasty surprises.
Then provide a way for the user to specify that a function is to be used on a specific FPPA only, e.g. something likeCode: [Select][[sdcc::fppa(3)]] void f(int)
An FPPA3-specific p3 would be used instead of p when generating code for f.
{
…
}
Btw, it should also be possible to use the atomic xch instruction? This is effectively like a CAS that can only compare to a single value.
…
Thumbs up :-+ adding RX to it would be nice too ;)
Thumbs up :-+ adding RX to it would be nice too ;)
Apart from that, the includes now support upper case SFR names as defines. This allows intellisense in VSCODE to work to at least some extend.
07E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 0282 025A 1FFE
07F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
IHRCAL: 82
IHRCRNOW: 82
ILRCRNOW: 82
BGTCAL: 5A
BGTRNOW: 5A
from include file: IHRCR IO_WO 0x0B
ILRCR IO_WO 0x39 (-) // [7:4]
BGTR IO_RW 0x1A (0x2C) // [7:3]
I have been experimenting with the IHRC and BGTR-calibration. As JS notedin an older post, there are calibration values stores on the flash in the PFS154/163 in two read-only memory addresses.
It appears to me, that these are automatically loaded into the respective registers. The dump below shows the initial value of IHRCR and BGTR and it is exactly the same as the value stored on the flash. The value is also the same that EASYPDKPROG ends up with during calibration. It appears that no calibration is needed on the flash types, unless you want to adjust to a different voltage?
Is this confirmed anywhere?
I also noted that IHRCR is readable, although it is marked as write only in the official .INC file.
Also strange: The low frequency oscillator calibration register (ILRCR) has the same initial value as the IHRCR. There is no corresponding value in the flash.Code: [Select]07E0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 0282 025A 1FFE
from include file:
07F0: 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF 3FFF
IHRCAL: 82
IHRCRNOW: 82
ILRCRNOW: 82
BGTCAL: 5A
BGTRNOW: 5ACode: [Select]IHRCR IO_WO 0x0B
ILRCR IO_WO 0x39 (-) // [7:4]
BGTR IO_RW 0x1A (0x2C) // [7:3]
The bandgap is probably also used by the oscillator, unless it uses a separate voltage reference. It's a good idea to trim it, too. The resolution is rather fine though, around 500mV across the entire 8 bit range of BGTR, ~2mV per count. I tested this by using the comparator and Vint_ref as reference. It may be a challenge to measure the voltage accurately enough.
I do not understand how you use SPI to calibrate IC and measure the final frequency.
Another thing I'm curious about is that there are direct ways to operate on OTP ram, such as burning programs directly into OTP ram and executing programs in ram.
Apparently only bits [7:3] of BGTR are used. I determined Vbg to be at ~1.08V for BGTR=0 and 1.47V for BGTR=240 on one PFS154. This means that the voltage resolution of the trimming register is 8*(1.47V-1.08V)/240= ~ 13mV.
To reach a trimming accuracy that is better than 13mV it would be necessary to apply 4.8V+-26mV externally (13*4.8/1.2/2=26). This assumes perfect resistor matching, which is unlikely. Certainly not impossible but also not without a challenge. If this is not possible it may be better to use the factory trimming.
A more accurate solution is obviously to apply 1.2V+-6.5mV to an external input of the comparator and use that as a trimming reference.
Hi,
I think you look to precise on this. In order to understand the magnitude of error our cheap ICs are having I suggest the following experiments:
1) output an alternating clock signal on an IO pin and measure frequency with oscilloscope
2) now touch the IC with your finger (which slightly increases temperature) and watch the HUGE difference of the clock
3) tune and perform your band gap comparator test (e.g. switch at 1.200V)
4) now touch the IC with your finger (which slightly increases temperature) and watch the HUGE difference of the band gap switch
BTW: I found factory trimming of bandgap on all FLASH and some OTP variants, however factory trimming of IHRC is available on FLASH based ICs only. ILRC does not have a factory trimming values in any of the devices I checked.
One quick question: has been the read protection of the PFS154 already documented?Found this with a quick search of the thread: https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2305515/#msg2305515 (https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2305515/#msg2305515)
I can only corroberate JS findings about very bad noise immunity of the PFS154.
I wasted a lof time getting a LED to work as a light sensor on the PFS154. My only conclusion is that the PFS154 has severe internal coupling issues. I summarized my findings here:
https://cpldcpu.wordpress.com/2019/09/28/a-led-candle-based-on-the-3-cent-mcu/
It seems to be advised to stick to purely digital designs, at least for the lower end Padauk MCUs.
Bad noise immunity on the PFS series is not a surprise, it is even stated by Padauk in their catalog. The otherwise closest devices, but with claimed much better noise immunity would be the PFC series. Though teh PFC154 is marked as a "new" device, so it might take a few weeks until it arrives at distributors.
> write-pfs154.py honk.ihx com3
Writing 0000-0007... done
Writing 0010-00AB... done
Writing 07FF-07FF... done
Verifying 0000-0007... OK
Verifying 0010-00AB... OK
Verifying 07FF-07FF... FAILED
@ 07FF - expected 0000, read 3FFF
I've tried setting the last word but it seems there's some kind of either protection or sorcery going on - I cannot change it to anything:Code: [Select]> write-pfs154.py honk.ihx com3
Writing 0000-0007... done
Writing 0010-00AB... done
Writing 07FF-07FF... done
Verifying 0000-0007... OK
Verifying 0010-00AB... OK
Verifying 07FF-07FF... FAILED
@ 07FF - expected 0000, read 3FFF
I have VPP set to 5.8V and the rest of the flash seems to be programmable just fine. Should I do anything special to program this last word?
Bad noise immunity on the PFS series is not a surprise, it is even stated by Padauk in their catalog. The otherwise closest devices, but with claimed much better noise immunity would be the PFC series. Though teh PFC154 is marked as a "new" device, so it might take a few weeks until it arrives at distributors.
Yeah, it's kinda telling if the manufacturer mentions it even on their line card. Although, bad PSRR/EMI immunity does not neccesarily imply that there is also strong internal coupling. In this case it seems to be like that.
I wonder, has anybody tried the ADC in the PFS173 yet? How many bits are actually noise free?
There is no magic for last word. It looks like your programmer / programming script tries to write to odd address. PFS devices only can start writing at even addresses (this means you have to write 7FE and 7FF, you can write "FFFF" to 7FE so it will not change the exisiting value, just the verifier in your script needs to know about this fact afterwards).Thank you! I will try to have my programmer align to chunks of 4 words.
JS
0x0007: 0x2fe0 MOV A, 0x00
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
0x0007: 0x2fe0 MOV A, 0x20
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
0x0007: 0x2fe0 MOV A, 0x40
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
0x0007: 0x2fe0 MOV A, 0x60
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
0x0007: 0x2fe0 MOV A, 0x80
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
0x0007: 0x2fe0 MOV A, 0xA0
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
0x0007: 0x2fe0 MOV A, 0xC0
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
0x0007: 0x2fe0 MOV A, 0xE0
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
I think PFS173 is the better way to go for your specific project.
I got PFS173 in small 6 pin housing for 4.6 cent / pcs. So no real need for me to use PFS154 or PMS150C: https://item.taobao.com/item.htm?id=598420620199
JS
As oposed to what https://github.com/free-pdk/fppa-pdk-documentation/blob/master/Reserved_Area_Last_8_Words_Of_Codemem.txt says, the LVR seems not to be configured via the last word but the MISC_LVR register:
For 4.0V:Code: [Select]0x0007: 0x2fe0 MOV A, 0x00
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
For 3.5V:Code: [Select]0x0007: 0x2fe0 MOV A, 0x20
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
For 3.0V:Code: [Select]0x0007: 0x2fe0 MOV A, 0x40
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
For 2.75V:Code: [Select]0x0007: 0x2fe0 MOV A, 0x60
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
For 2.5V:Code: [Select]0x0007: 0x2fe0 MOV A, 0x80
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
For 1.8V:Code: [Select]0x0007: 0x2fe0 MOV A, 0xA0
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
For 2.2V:Code: [Select]0x0007: 0x2fe0 MOV A, 0xC0
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
For 2.0V:Code: [Select]0x0007: 0x2fe0 MOV A, 0xE0
0x0008: 0x019b MOV IO(0x1B), A ;MISC_LVR
I think PFS173 is the better way to go for your specific project.
I got PFS173 in small 6 pin housing for 4.6 cent / pcs. So no real need for me to use PFS154 or PMS150C: https://item.taobao.com/item.htm?id=598420620199
JS
Thats a very good offer. How did you manage to order there?
Regarding the MISC_LVR register again - was that name found somewhere in official PADAUK docs or in the IDE code or somewhere else? I am wondering because otherwise, maybe it would be sensible to rename it to MISCLVR (without the underscore), or lvrc (LVR control, as other control registers are the name of the peripheral + "c" such as tm2c or gpcc).
The problem with MISC_LVR is that I wanted to make a PR to cpldcpu's io_pfs154.h (https://github.com/cpldcpu/SimPad/blob/master/Toolchain/library/pdk/io_pfs154.h) to include the bits that the IDE generates for several voltages for the PFS154 (https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2723562/#msg2723562), but there's already a MISC_LVR_DISABLE, and IMHO it would be confusing that this one refers to the misc register, and MISC_LVR_1_8V (for setting LVR to 1.8V, for example) refers to the MISC_LVR register.
MISC_LVR IO_WO:OP 0x1B (-)
$ 7 ~ 4 : 1V8, 1V9, 2V, 2V1, 2V2, 2V3, 2V4, 2V5, 2V75, 3V, 3V15, 3V3, 3V5, 3V75, 4V, 4V5
$ 1 ~ 0 : BG_On, BG/4, BG/32, BG_Auto
Maybe i missed this somewhere, but im not seeing it in the documentation.It is documented vaguely in the datasheets and manual for the official programmer from Padauk. You'd have to read several of the controller datasheets, the protocol description in this thread and on github and then slowly the pieces begin to fall together.
I built the programmer, flashed firmware. All seems well. I would like to program the 6 pin PMS150c, but i do not know how to wire to the output headers.
hi,
i build my own easy-pdk-programmer , but can't write ,Other operations are OK。
(Attachment Link)
this my board pic
any idea what might goes wrong?
Maybe i missed this somewhere, but im not seeing it in the documentation.It is documented vaguely in the datasheets and manual for the official programmer from Padauk. You'd have to read several of the controller datasheets, the protocol description in this thread and on github and then slowly the pieces begin to fall together.
I built the programmer, flashed firmware. All seems well. I would like to program the 6 pin PMS150c, but i do not know how to wire to the output headers.
But I also made an adapter pcb which should make it easy: https://github.com/free-pdk/easy-pdk-programmer-hardware/tree/master/adapter-pcbs (https://github.com/free-pdk/easy-pdk-programmer-hardware/tree/master/adapter-pcbs). You could replicate that on your breadboard. See the schematics. The inner columns are the programmer, the outer ones the Padauk.
thanks JS,hi,
i build my own easy-pdk-programmer , but can't write ,Other operations are OK。
(Attachment Link)
this my board pic
any idea what might goes wrong?
Hi,
it looks very good already.
The problem you see can be caused by long wires / dirty contacts of adapter / ... so VDD or VPP is not supplied properly to IC.
Usually reseating the IC in socket / using shorter wires solves this problem.
How do you connect the PFS173 to the programmer?
Also please check values and soldering of:
C2 / C10 (must be 100nF, they stabilize VDD and VPP)
and
C13 / C21 (must be 4.7uF, they stabilize the opamp inputs)
JS
thanks JS,hi,
i build my own easy-pdk-programmer , but can't write ,Other operations are OK。
(Attachment Link)
this my board pic
any idea what might goes wrong?
Hi,
it looks very good already.
The problem you see can be caused by long wires / dirty contacts of adapter / ... so VDD or VPP is not supplied properly to IC.
Usually reseating the IC in socket / using shorter wires solves this problem.
How do you connect the PFS173 to the programmer?
Also please check values and soldering of:
C2 / C10 (must be 100nF, they stabilize VDD and VPP)
and
C13 / C21 (must be 4.7uF, they stabilize the opamp inputs)
JS
I made a test board, only PFS173 and Female Socket were soldered. I also checked C2 / C10,C13 / C21 , and they were correct.
(Attachment Link)
ok ive made a little progress. Programer is detected, chip is detected and id. when i try to program the hello world 150c i get a successful write, but a failed verify. if i try to write again it says chip is not blank (of course)
Running easypdk start i do not get a hello world, but i dont know if i am supposed to.
Not sure how to debug this. Running verbose doesn't seem to give anything further. Tried 2 chips with same result just to make sure.
Also, what are these IHX files all about? How does one convert a PDK project made in the official IDE to this format?
ok ive made a little progress. Programer is detected, chip is detected and id. when i try to program the hello world 150c i get a successful write, but a failed verify. if i try to write again it says chip is not blank (of course)
Running easypdk start i do not get a hello world, but i dont know if i am supposed to.
Not sure how to debug this. Running verbose doesn't seem to give anything further. Tried 2 chips with same result just to make sure.
Also, what are these IHX files all about? How does one convert a PDK project made in the official IDE to this format?
Regarding the MISC_LVR register again - was that name found somewhere in official PADAUK docs or in the IDE code or somewhere else? I am wondering because otherwise, maybe it would be sensible to rename it to MISCLVR (without the underscore), or lvrc (LVR control, as other control registers are the name of the peripheral + "c" such as tm2c or gpcc).
The problem with MISC_LVR is that I wanted to make a PR to cpldcpu's io_pfs154.h (https://github.com/cpldcpu/SimPad/blob/master/Toolchain/library/pdk/io_pfs154.h) to include the bits that the IDE generates for several voltages for the PFS154 (https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2723562/#msg2723562), but there's already a MISC_LVR_DISABLE, and IMHO it would be confusing that this one refers to the misc register, and MISC_LVR_1_8V (for setting LVR to 1.8V, for example) refers to the MISC_LVR register.
I can read successfully and it has been written. not sure how to compare it to input, since input is a IHX file, readout seems to do a HEX file or a BIN file.
I can read successfully and it has been written. not sure how to compare it to input, since input is a IHX file, readout seems to do a HEX file or a BIN file.
.ihx and .hex are both file endings for Intel Hex. objcopy can be used to convert between Intel Hex and raw binary.
(In development branch of programmer software, examples folder: https://github.com/free-pdk/easy-pdk-programmer-software/tree/development/Examples/src (https://github.com/free-pdk/easy-pdk-programmer-software/tree/development/Examples/src))I might be wrong, but isn't 2.5 LVR register value 0x80 instead of 0x70? I think I got 0x80, and that would make sense given the rest of the values are using only the three MSB of the MISCLVR register.
JS
VDD (BG=1.2V) | GPCS.5 | GPCS.4 | GPCS.N |
1.60 | 0 | 0 | 15 |
1.67 | 0 | 0 | 14 |
1.75 | 0 | 0 | 13 |
1.80 | 0 | 1 | 15 |
1.83 | 0 | 0 | 12 |
1.92 | 0 | 1 | 14 |
1.92 | 0 | 0 | 11 |
2.00 | 1 | 0 | 15 |
2.02 | 0 | 0 | 10 |
2.06 | 0 | 1 | 13 |
2.09 | 1 | 0 | 14 |
2.13 | 0 | 0 | 9 |
2.18 | 1 | 0 | 13 |
2.22 | 0 | 1 | 12 |
2.26 | 0 | 0 | 8 |
2.29 | 1 | 0 | 12 |
2.40 | 0 | 0 | 7 |
2.40 | 0 | 1 | 11 |
2.40 | 1 | 0 | 11 |
2.40 | 1 | 1 | 15 |
2.53 | 1 | 0 | 10 |
2.56 | 0 | 0 | 6 |
2.56 | 1 | 1 | 14 |
2.62 | 0 | 1 | 10 |
2.67 | 1 | 0 | 9 |
2.74 | 0 | 0 | 5 |
2.74 | 1 | 1 | 13 |
2.82 | 1 | 0 | 8 |
2.88 | 0 | 1 | 9 |
2.95 | 0 | 0 | 4 |
2.95 | 1 | 1 | 12 |
3.00 | 1 | 0 | 7 |
3.20 | 0 | 0 | 3 |
3.20 | 0 | 1 | 8 |
3.20 | 1 | 1 | 11 |
3.20 | 1 | 0 | 6 |
3.43 | 1 | 0 | 5 |
3.49 | 0 | 0 | 2 |
3.49 | 1 | 1 | 10 |
3.60 | 0 | 1 | 7 |
3.69 | 1 | 0 | 4 |
3.84 | 0 | 0 | 1 |
3.84 | 1 | 1 | 9 |
4.00 | 1 | 0 | 3 |
4.11 | 0 | 1 | 6 |
4.27 | 0 | 0 | 0 |
4.27 | 1 | 1 | 8 |
4.36 | 1 | 0 | 2 |
4.80 | 0 | 1 | 5 |
4.80 | 1 | 0 | 1 |
4.80 | 1 | 1 | 7 |
5.33 | 1 | 0 | 0 |
5.49 | 1 | 1 | 6 |
5.76 | 0 | 1 | 4 |
6.40 | 1 | 1 | 5 |
7.20 | 0 | 1 | 3 |
7.68 | 1 | 1 | 4 |
9.60 | 0 | 1 | 2 |
9.60 | 1 | 1 | 3 |
12.80 | 1 | 1 | 2 |
14.40 | 0 | 1 | 1 |
19.20 | 1 | 1 | 1 |
28.80 | 0 | 1 | 0 |
38.40 | 1 | 1 | 0 |
I can read successfully and it has been written. not sure how to compare it to input, since input is a IHX file, readout seems to do a HEX file or a BIN file.
.ihx and .hex are both file endings for Intel Hex. objcopy can be used to convert between Intel Hex and raw binary.
I have attached my readout as well as the orginal example PM150 hello world (had to add txt per forum upload rules)
In hex editor they appear very different.
(In development branch of programmer software, examples folder: https://github.com/free-pdk/easy-pdk-programmer-software/tree/development/Examples/src (https://github.com/free-pdk/easy-pdk-programmer-software/tree/development/Examples/src))I might be wrong, but isn't 2.5 LVR register value 0x80 instead of 0x70? I think I got 0x80, and that would make sense given the rest of the values are using only the three MSB of the MISCLVR register.
JS
Sorry, I forgot to mention I was talking about the PFS154.
For a very low-power, which does not need perfect frequency accuracy, I'm trying to use ILRC and keep IHRC disabled. However I seem to be getting a frequency four times lower than expected on ILRC:Code: [Select]#include <pfs154.h>
I get a square wave with a duty cycle of 25%, but at 11.1KHz rather than the expected 54KHz than the datasheet suggests. Any idea why?
// From cpldcpu's SimPad repository
#define PDK_USE_FACTORY_TRIMMING() {__asm__ (".word (0x3fed)\nmov __ihrcr,a\n.word (0x3fee)\nmov __bgtr,a\n");}
unsigned char _sdcc_external_startup(void) {
PDK_USE_FACTORY_TRIMMING();
// Set clock to ILRC and disable IHRC
CLKMD = CLKMD_ENABLE_ILRC | CLKMD_ENABLE_IHRC | CLKMD_ILRC;
CLKMD &= ~CLKMD_ENABLE_IHRC;
return 0;
}
int main(void) {
// Set PA0 pin to output
PAC = 0b00000001;
while (1) {
__set1(PA, 0);
__set0(PA, 0);
}
}
I have tried with two different PFS154 to rule out a defect in a single device, and they both behave the same.
Hello :),Try
I hope that you can help me. I got to know the padauk uC from youtube quite a while ago. Recently I build the Free pdk Programmer from Github, but I have some starting issues. I got the firmware sucessfully flashed and have also probed successfully a PMS150C. My question is now what mikrocontrollers are supported by the time, bcause I think I read somewhere that I can only flash the PFS154 and PFS174.
easypdkprog list
to list the supported devices.And my last question is, if there is a tutorial or a list of the operations you can use when programming in c or mini-C?
I mean where do I find the specific comandos for setting up the uC. Thing like timer , interupts on coperator edge detections. Do I use the same aus discribed in the data sheet or do they vary a bit.The manufacturer data sheets are the best source. They explain in detail how to setup interrupts, timers, comparator, edge detections,...
And the question for the programming of the PMS150C is more if I can generate the file for flashing or not?You can use SDCC and it will produce the complete (hex) file for flashing. (see above)
I think I read somewhere in this post, that by now only the PFS154 and PFS174 are supported in the SDCC...This is wrong. Right now SDCC can be used to generate code for all 13, 14 and 15 bit PADAUK ICs which includes apx. 95% of all PADAUK ICs available.
Therefor I want to know if I an use the .pdk Files from the padauk IDE. I think I read ... that ... I can only flash .hex files because the .pdk contain futher informations than only the code (something like calibration of the clock).This is correct. PDK files can NOT be flashed to the IC directly. The original IDE inserts a lot of stub code which the WRITER (flasher) needs to know about and manipulate the contents flashed to the IC.
js_12345678_55AA you said tat the 13 bit padauks are supported, but on Github (https://github.com/free-pdk/sdcc-pdk-code-examples/blob/master/README (https://github.com/free-pdk/sdcc-pdk-code-examples/blob/master/README)) stands that it is still experimental.
Futhermore I installed sdcc yesterday and only the pdk14 and pdk15 where showes for lib installation.
Is there a way that I get the pdk13 lib, altthough it is still experimental.
The work you've done reverse-engineering and designing the programmer is very impressive :). Is there a document describing the steps the programmer goes through to program the devices (e.g. set MCLR/Vpp=13V, VDD=6.5V, delay 100ms, etc.)?
Also, I was wondering if you've thought about using the PICKIT2 for programming the devices, as has a programmable Vpp/Vdd/etc. for programming PIC microcontrollers, and I get the feeling that the padauk chips are somewhat related. I've used the PICKIT2 for programming ATMEGA88 (set Vpp=Vdd=5V, use SPI data transfer) before the USBASP was readily available, and it may be easier to get hold of a PICKIT2 from online shops than the free-pdf/easy-pdk-programmer, for some people.
Best Regards,
db
Have a look here: https://github.com/free-pdk/fppa-pdk-documentation . You will find many notes and documents regarding programing of the IC.Thanks! The "Architectural considerations" document is quite thorough.
I also had a look at PICKIT2 and considered using it. Unfortunately it was not fulfilling all requirements like capturing high speed signal from IC (this is required to calibrate the internal oscillator).The PICKIT2 can capture at up to 1MHz (or 500kHz, 250kHz, etc.), for 1000 samples, so the calibration should be possible. It can only output Vdd<5V though, which will be an issue if 6.5V is required for programming. This would require a hardware workaround, if 5V Vdd is insufficient.
Also the price of PICKIT2 is a bit high compared to the $2 solution of easypdk programmer ::).So, where/how would someone in a developing nation, in particular Australia, get one of these $2 programmers?
Also the price of PICKIT2 is a bit high compared to the $2 solution of easypdk programmer ::).So, where/how would someone in a developing nation, in particular Australia, get one of these $2 programmers?
There is a "limited voltage programming mode", at least for the PFS154, which does limit VDD to 5V. This mode is not yet documented however.
I would be interested too in using a PICkit too, since that would be an easier entry point for more people to get interested in the Padauk platform.
Hi
js_12345678_55AA you said tat the 13 bit padauks are supported, but on Github (https://github.com/free-pdk/sdcc-pdk-code-examples/blob/master/README (https://github.com/free-pdk/sdcc-pdk-code-examples/blob/master/README)) stands that it is still experimental. Futhermore I installed sdcc yesterday and only the pdk14 and pdk15 where showes for lib installation. Is there a way that I get the pdk13 lib, altthough it is still experimental. I want to use the PMS150C for a few small and very simple task, because of its little footprint (sot23-6).
I would be interested too in using a PICkit too, since that would be an easier entry point for more people to get interested in the Padauk platform.Same. I might have a go, although the way I'm thinking will require an external power supply, and an opamp to multiply the VDD x1.5.
I outlined the process to order from JLCPCB.com and LCSC.com. If you use the signup discounts you might pay less than USD20 (including shipping) for several pcbs and parts to make at least 10 pcs... and it is a fun project to solder them :-)Yes, I did see that; it's a bit more than just a $2 device then. Maybe if the taobao guy doesn't get up and running, I'll consider making a batch. Soldering new clean PCBs is always fun :)
But anything lower than this (e.g. 4.9V) will not work for sure... But this obviously would work for the PFS (flash based ICs) only.That's good to know about the LVPM; the PICKIT2 has a schottky diode in line with VDD, so it will be ~4.9V max (unless VUSB is boosted to 6V).
BTW: Have you seen this: https://github.com/free-pdk/easy-pdk-programmer-hardware/issues/10 (https://github.com/free-pdk/easy-pdk-programmer-hardware/issues/10)Sounds good :)
Looks like somebody might create a ready made version and sell it soon...
If you follow the link / instructions from the example directory I mentioned earlier... https://github.com/free-pdk/easy-pdk-programmer-software/tree/master/Examples/src (https://github.com/free-pdk/easy-pdk-programmer-software/tree/master/Examples/src)
you will find a download link for current SDCC snapshots (nightly builds) for several platforms: http://sdcc.sourceforge.net/snap.php (http://sdcc.sourceforge.net/snap.php)
I just checked again and 13 bit support is included.
If you follow the link / instructions from the example directory I mentioned earlier... https://github.com/free-pdk/easy-pdk-programmer-software/tree/master/Examples/src (https://github.com/free-pdk/easy-pdk-programmer-software/tree/master/Examples/src)
you will find a download link for current SDCC snapshots (nightly builds) for several platforms: http://sdcc.sourceforge.net/snap.php (http://sdcc.sourceforge.net/snap.php)
I just checked again and 13 bit support is included.
Okay, I did what you said, but I still did not get it completly (sorry for that). I downloaded and installed the sdcc exe. During the installation prozess the applied libs are viewed. So I downloaded additionally the .zip file and unzipped it. In this unziped directory I found in the lib folder the pdk13 folder and copied it into the lib folder of the installed exe.
Now I tried compieling the code examples. At first helloword example from the software branch and later the examples from the sdcc example branch. Non of them worked. In the helloworld from the software branch I later defined additionally the the used uC. At first I tried compiling withe the "make" command in diffent variations like explained in the software/examples/src branch but I did not get a response at all. Next I tried compiling with "sdcc helloworld.c" . With this it started compiling but I got warning 182 for the "pfs154.h" "absolute address for sfr '...' probably out of range". Futhermore I got errors for helloworld.asm. Ten times I got ".org in REL area or directive / mnemonic error" and at last "missing or improper operator, terminators, or delimiters". After that helloworld.rel was removed. (I added a screenshot of the cmd window)
It would be great if you can tell me what I am doing wrong all the time and thank you very much for your comments in the past.
Hi. I just had a look at the schematic.It's for protection. The enable signal of the boost converter does not enable / disable the output. It is enabling / disabling the boost. So at startup, even without the enable signal present, you get +5V out of it.
Why is the supply switched to the boost converter, rather than using the 'Enable' pin of the converter? The extra 4u7 on the +5V rail is within USB spec's <10uF total rail capacitance.
Why is the negative charge pump required for the opamp? The AS358 input and output ranges include 0V. Was it added because the AS358 sink current drops off below 1V? I get the feeling that it shouldn't be an issue.
It's for protection. The enable signal of the boost converter does not enable / disable the output. It is enabling / disabling the boost. So at startup, even without the enable signal present, you get +5V out of it.The DAC pins are pulled low through 240k resistors, so on startup, the voltage is 0V. If the charge pump was removed, the negative voltage would always be stable.
The output of the boost converter directly feeds the opamp.
But at startup DAC output of the STM32 and the negative voltage reference of the opamp is undefined which would let the output of the boost converter slip through to the pins of a potential connected target IC.
To save cost. I wanted to use a cheap opamp (rail to rail opamps are much more expensive) and we really need 0V. With a non rail to rail opamp like the AS358 it is impossible to get 0V output with a 0V negative reference.The AS358 has an output range of 0V to 13.5V, with a 15V supply voltage. The input voltage range also includes 0V. The only thing to note with the output voltage under 1V is that the current that the output can sink reduces rapidly.
Thanks for the reply. :)Unfortunately not.... When you enable the DAC on STM32 the output is 100%. After initialization you can setup 0 value. So for a short moment DAC output is 100% during initialization.It's for protection. The enable signal of the boost converter does not enable / disable the output. It is enabling / disabling the boost. So at startup, even without the enable signal present, you get +5V out of it.The DAC pins are pulled low through 240k resistors, so on startup, the voltage is 0V. If the charge pump was removed, the negative voltage would always be stable.
The output of the boost converter directly feeds the opamp.
But at startup DAC output of the STM32 and the negative voltage reference of the opamp is undefined which would let the output of the boost converter slip through to the pins of a potential connected target IC.
I tried without the negative reference and could not program the ICs. I think the 2 extra diodes are ok... If I rememebr correctly I was never able to get 0V from opamp output with VIN- tied to GND. Have you tested / measured the result with AS358 and VIN- 0V?To save cost. I wanted to use a cheap opamp (rail to rail opamps are much more expensive) and we really need 0V. With a non rail to rail opamp like the AS358 it is impossible to get 0V output with a 0V negative reference.The AS358 has an output range of 0V to 13.5V, with a 15V supply voltage. The input voltage range also includes 0V. The only thing to note with the output voltage under 1V is that the current that the output can sink reduces rapidly.
I think you could remove 10 components and have it still function happily.
Cheers,
It would be great if you can tell me what I am doing wrong all the time and thank you very much for your comments in the past.
If I rememebr correctly I was never able to get 0V from opamp output with VIN- tied to GND. Have you tested / measured the result with AS358 and VIN- 0V?I just connected an LM358 as a unity-gain buffer, on a 12V supply, which gave ~6mV output for 0V input, and 10.76V for 12V input.
If I rememebr correctly I was never able to get 0V from opamp output with VIN- tied to GND. Have you tested / measured the result with AS358 and VIN- 0V?I just connected an LM358 as a unity-gain buffer, on a 12V supply, which gave ~6mV output for 0V input, and 10.76V for 12V input.
The TI LM358 and the DI AS358 datasheets have the same simplified schematics (transistors and current sources), and I suspect that they're effectively the same device.
Cheers,
The firmware to stm32 flashed correctly. I have a few PMS150c 8 pins I can use and have it connected. When i use easypdkprog I get the message "No programmer found".How did you flash the firmware? With DFU tool over USB from your Ubuntu installation?
What I'd like to know is, is there any component I may have botched? When do the LEDs light up? Are there testpoints I can check for certain voltages to know if i damaged something? I did handsolder and the stm32 suffered the most with my "skills" but it seems to be ok.
shucks i actually see that dfu error only now :palm:
Is there any reverse engineering regarding the ICE (In-Circuit-Emulator) going on (didn't read the whole 32 pages)?
I got my ICE today as well. Here is a high resolution image: https://i.imgur.com/8yef37g.jpg (https://i.imgur.com/8yef37g.jpg)
The FPGA has no markings. It might be possible to capture the JTAG init sequence, if it doesn't store the configuration data inside the FPGA, because looks like there is no external configuration flash memory.
The USB device is a CY7C68013A, with high speed USB (480 Mbps) and an integrated 8051 CPU, that can be booted through USB (there is an interesting project, which implements a communication through such a Cypress chip to a FPGA over USB, FPGALink (http://www.swaton.ukfsn.org/docs/fpgalink/vhdl_paper.pdf)). So this could be a very flexible construction, booting first the firmware of the 8051, then booting the FPGA bitstream, all over USB. But I think it might be easier to develop a new emulator than trying to reverse engineer this. Would be nearly impossible to decode the FPGA bitstream back to the HDL code.
"usb-devices" shows the same as js_12345678_55AA wrote:Code: [Select]T: Bus=01 Lev=01 Prnt=01 Port=01 Cnt=03 Dev#= 9 Spd=480 MxCh= 0
D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1
P: Vendor=0797 ProdID=7002 Rev=80.01
S: Manufacturer=PADAUK
S: Product=LGS_DEV FX2-HID 0.01
C: #Ifs= 1 Cfg#= 1 Atr=a0 MxPwr=500mA
I: If#= 0 Alt= 0 #EPs= 2 Cls=03(HID ) Sub=00 Prot=00 Driver=usbhid
# SDCC=../../sdcc/bin/sdcc
# Add enviroment path for SDCC to windows path
SDCC = sdcc.exe
OUTDIR=build
all: PFS173
PFS173:
mkdir -p $(OUTDIR)
$(SDCC) -DPFS173 -mpdk15 -o $(OUTDIR)/main.ihx main.c
clean:
rm -rf $(OUTDIR)
# Place easypdkprog.exe file inside the source folder of your .c file
prog:
easypdkprog write build\main.ihx -nPFS173
start:
@echo "Starting the Device"
easypdkprog start --runvdd=4.0
run: PFS173 prog start
.PHONY: all clean
JS I'm playing with your serialecho example, and modified it! I think the getchar is not working
Also Do you have some ADC examples?
char c='';
for(;;)
{
puts("Echoing serial receive (type something):\r\n");
for(int i=0;i<10000;i++);
c = getchar();
for(int i=0;i<10000;i++);
putchar(c);
}
Also Do you have some ADC examples?
FYI, I ventured out and reviewed all sub $0.10 microcontrollers on LCSC. I hope it's somewhat useful:Cheap MCUs that are widely used in China are OTP produced by Taiwan nyquest. My purchase of NY8A050D is only RMB 0.1 yuan, about 0.014 US dollars.
https://cpldcpu.wordpress.com/2019/08/12/the-terrible-3-cent-mcu/ (https://cpldcpu.wordpress.com/2019/08/12/the-terrible-3-cent-mcu/)
I can now confirm that the Padauk MCUs are the best in this segment. We knew this before, did we?
Well, now back to actual projects on the PFS154...
Thanks JS, I managed to flash the Dev branch to the ARM and now it's working, But still only probing is working |O |O |O any Idea what might goes wrong?
Now you have to check your hardware variant. On the picture I saw that C1 is not populated and also Y1 is missing. A cap on the 15V rail is essential since VCC/VDD draw some power during programing. The crystal is used to get better tuning results after the CPU is flashed, without it the drift might be much higher or you create a very special clock path using the HSI48 with sync to USB frames (then programmer can not be used stand alone - a feature planned for future use, just like WRITER).
Also, since you changed the opamp, it might be possible that the output voltages differ. You can use the "easypdkprogtest" program to check that the output voltage is correct:
DO THIS WITHOUT A MCU CONNECTED TO THE PROGRAMMER
make easypdkprogtest
./easypdkprogtest
vdd: 5.01 vpp: 4.98 (vref= 3.30)
Please check that VDD and VPP are 5V and VREF is 3.3V. Also measure them on your PCB.
In case VDD and VPP voltages are incorrect you need to tune the DAC reference values for your specific hardware (in fpdk.c you need to change FPDK_VDD_DAC_MAX_MV / FPDK_VPP_DAC_MAX_MV).
JS
The depdk converted bin file cannot be written to the target chip using easypdkprog Is there a way to convert the bin file to an ihx file ?
Where to get it "easypdkprogtest" program ? File Directory path . Thanks!
JS please add PMC131 and PMC271 parts support, they are industrial grade and have ADC
(https://image.easyeda.com/pullimage/0saC7lN9uPN13wP1Y6bCfeq7nIJxO12LutiRiZsv.png)
What does RO mean in brackets on the right of the list?
I used to be on this topic downloaded a command line utility that can parse the PDK file , and it can show which IC types the PDK file was compiled . But now I can't find that command line utility through this topic. Do you help me find it ?
JS please add PMC131 and PMC271 parts support, they are industrial grade and have ADC
Thanks JS, I find the PFS173 to be very useful, I need it to capture some Signals with ADC and send them over uart! The only problem with PFS173 is the working temperature! it's not -40 to 85C, so It can not be used inside industrial gears, Also the SOT23-6 package is very nice to have. then unfortunately we do not have something in the -40 to 85c in the PMC parts :palm:
why PFS173 would not boot properly when connected to an external 5V supply to work as stand alone? :palm:
should be reset pulled up to VCC? I have done it and got no luck!
There will be a short talk on the free toolchain for the Padauk µC on 12:00 Sunday the 2nd of February at FOSDEM 2020:
https://fosdem.org/2020/schedule/event/paduak_toolchain/
There will be a short talk on the free toolchain for the Padauk µC on 12:00 Sunday the 2nd of February at FOSDEM 2020:
https://fosdem.org/2020/schedule/event/paduak_toolchain/
Nice! Will the talk be recorded? Or will at least the slides be available?
Btw, where do you get the €0.01 from?
I saw it today. Looks like massive work! Is it synthesizable? This could be the foundation for an open-source in-circuit emulator based on any cheap FPGA board. It would ease development for the OTP variants a lot.As of now, it is not synthesizable. Mainly because there are a few open questions regading the microcontroller implementation (see the toplevel README, I have a few questions there that need to be answered).
I wonder, what is so peculiar about the PFS154 interrupts? Since every instruction is executed in one or two cycles, the interrupts should be fairly quick and with low jitter?They are quick... but it's hard to understand if you can keep up the pace when the interrupt sources come at only a few microsseconds apart. Simulating this at a lower level allows you to test several scenarios and evaluate whether your design will work or not. What I can tell you is, my first version which was implemented in "C" and built with SDCC was *not* able to keep pace. I found this during simulation, and simulation helped me optimize the (now in assembly) code.
I saw it today. Looks like massive work! Is it synthesizable? This could be the foundation for an open-source in-circuit emulator based on any cheap FPGA board. It would ease development for the OTP variants a lot.As of now, it is not synthesizable. Mainly because there are a few open questions regading the microcontroller implementation (see the toplevel README, I have a few questions there that need to be answered).QuoteI wonder, what is so peculiar about the PFS154 interrupts? Since every instruction is executed in one or two cycles, the interrupts should be fairly quick and with low jitter?They are quick... but it's hard to understand if you can keep up the pace when the interrupt sources come at only a few microsseconds apart. Simulating this at a lower level allows you to test several scenarios and evaluate whether your design will work or not. What I can tell you is, my first version which was implemented in "C" and built with SDCC was *not* able to keep pace. I found this during simulation, and simulation helped me optimize the (now in assembly) code.
There is something peculiar about how SDCC generates the interrupt handler, though. I ended up with the following sequence which was non-optimal (in addition to the goto statement due to memory location, I presume)
pushaf
mov a, p
pushaf
// Interrupt code
popaf
mov p, a
popaf
reti
I did not require modification of A for the most important part of the interrupt routine. And definitely not using "p". 6 less instructions to execute, 750ns saved. Quite important when you have 3 us between interrupts, and you need to serve them quickly because you need to sample pins from within the interrupt routine.
Alvaro
__sfr __at(0x03) clkmd;
__sfr __at(0x0d) padier;
__sfr __at(0x0e) pbdier;
__sfr __at(0x10) pa;
__sfr __at(0x11) pac;
__sfr __at(0x12) paph;
unsigned char _sdcc_external_startup(void){
return 0;
}
void main(void){
paph = (1<<5); // Enable pull-high
pa = 0; // HI
pac = (1<<0); // Enable output
padier = 0;//(1<<5); // Enable PA5 wake up event
while(1){
if((pa&(1<<5))) pa |= (1<<0);
else pa &= ~(1<<0);
}
}
Hi again.
I have 2 questions.
1. I can't read input when PADIER = 0. Tested with PFS154.
Is there some kind of bug, or I'm missing something in the documentation?
2. I got strange 2x speed difference between PFS154 and PMS150C.Also nothing strange here. This is just how the ICs are manufactured (big variance from batch to batch from IC to IC).
Both set to 0x80 in IHRCR. PMS150C is 2 times slower (pwm speed and instruction execution time).
I need to set IHRCR really high (0xDA) to get the same results. Is it normal?
Is there a IHRCR factory calibration value for PMS150C in memory?
No bug. Just like it is. If you want to use a pin as digital input you have to enable the digital input pin in PxDIER = "Port x Digital Input Enable Register".Thank you for answer.
Also nothing strange here. This is just how the ICs are manufactured (big variance from batch to batch from IC to IC).
No bug. Just like it is. If you want to use a pin as digital input you have to enable the digital input pin in PxDIER = "Port x Digital Input Enable Register".Thank you for answer.
I thought PxC register is input/output switch and PxDIER is for wake up enable. There is nothing about input in bit definitions.
"Enable PA7~PA3 wake up event. 1 / 0 : enable / disable.
These bits can be set to low to disable wake up from PA7~PA3 toggling."
There is also nothing about it in "IO Pins" chapter.
"...all the pins can be independently set into two states output or input by configuring the data
registers (pa), control registers (pac) and pull-high registers (paph)......
If user wants to read the pin state, please notice that it should be set to input mode before
reading the data port....
When PMS15A/PMS150C is put in power-down or power-save mode, every pin can be
used to wake-up system by toggling its state. Therefore, those pins needed to wake-up system must be set to
input mode and set the corresponding bits of registers padier to high."
Only after analyzing "Hardware diagram of IO buffer", the reader may state that the description is incorrect.
The behavior of the chip also does not match the mentioned diagram. Read is always HI when PxDIER is LOW. If there is an AND gate, the read should be LOW.
Padauk put this AND gate in wrong place. It's a bug.
Thanks for the code. I seem to have an endianess problem somewhere.
I am using linux, but the IDE doesnt work with wine.
So I used windows to make and convert the file. Somehow bytes got swapped :palm:
Taiwan-based MCU maker Padauk Technology expects its shipments of MCU products to grow by over 20% on year to reach 1.3 billion units in 2020, according to company Tang Tsan-bih.
Despite growing concerns about the stability of related supply chain caused by the coronavirus outbreak, Tang said that he believes demand for MCUs will remain strong, particularly from sectors including 5G base stations, servers and other cooling fan systems.
Boasting a group of strong supply chain partners, including Magnachip Semiconductor and Powerchip Semiconductor Manufacturing (PSMC) for wafer foundry and Greatek Electronics for IC backend services as well as inventories of needed components for up to three months, Padauk is readied to support product roll-outs of its clients, Tang stated.
For individual product category, shipments of 8-bit MCUs for BLDC (brushless DC) motors will account for about 30% of its totals sales in 2020, up from 23% a year earlier, Tang revealed.
Meanwhile, the company is also expected to see its shipments of MCUs for TWS (true wireless stereo) devices expand significantly in 2020, having shipped about 20 million units to the sector in 2019, according to an estimate of industry sources.
The sources also estimated that Padauk will see its 2020 revenues grow over 10% from the NT$522 million (US$17.17 million) it recorded a year ago.
Shares of the MCU maker is scheduled to debut on Taiwan's OTC securities market in the second half of March.
#define ROP_TMX_6BIT 0x00
#define ROP_TMX_7BIT 0x10
#define ROP_TMX_16MHZ 0x00
#define ROP_TMX_32MHZ 0x20
#define ROP_PURE_PWM 0x00
#define ROP_GPC_PWM 0x40
#define ROP_PWM_16MHZ 0x00
#define ROP_PWM_32MHZ 0x80
JS, I want to know how we enable options in the SDSC, for example in the PFS173 Datasheet there are these options regarding clocking tim2 and Comparator usage,
GPC_PWM which can Enable Comparator controls all PWM outputs, and TMx_Source When tm2c[7:4]= 0010, TM2 clock source = IHRC*2 = 32MHZ and PWM_Source When Pwmgclk.0= 1, PWMG clock source = IHRC*2 = 32MHZ
There are these defines in the pfs173.hQuote#define ROP_TMX_6BIT 0x00
#define ROP_TMX_7BIT 0x10
#define ROP_TMX_16MHZ 0x00
#define ROP_TMX_32MHZ 0x20
#define ROP_PURE_PWM 0x00
#define ROP_GPC_PWM 0x40
#define ROP_PWM_16MHZ 0x00
#define ROP_PWM_32MHZ 0x80
how we should use them? I want to change the TIM2 clock to 32MHz and use the Comparator to control the PWM.
Take a look at this picture from the PFS173 Datasheet
Thanks
Thanks JS, I want to do a simple buck controller with these options, have you done any DC/DC converter with these padauk MCUs?Sorry, I never made a DC-DC myself, I always used dedicated ICs for this purpose.
Also there is nothing mentioning ROP register in the Datasheet, how did you find it?The .h files from the original PADAUK IDE contain all this information :)
You also can get rid of the 2 extra cycles from the GOTO statement in case you manually instruct SDCC to place your interrupt code directly to the right position.
Thank you for your detailed explanation! The major issue that I am having is that it is extremely difficult to obtain an EasyPDK programmer. STM32F072C8T6(and some other parts) becomes out of stock on LCSC for a long time(it means no jlcpcb SMT assembly). Also I found that assemble this programmer is really hard for people that lacks SMT soldering experience.
Hi,
did anybody investigate how the LVR (low voltage reset) fuses for the PFS154 work?
I tried to manually set the fuse for example to 0x36E1, which should set the LVR to 4V. At least according to https://github.com/free-pdk/fppa-pdk-documentation/blob/master/Reserved_Area_Last_8_Words_Of_Codemem.txt (https://github.com/free-pdk/fppa-pdk-documentation/blob/master/Reserved_Area_Last_8_Words_Of_Codemem.txt).
But the PFS154 powers on right at about 2V and powers off again if I go below 2V. I do not disable the LVR in the MISC register, so I think it should not switch on fully before Vdd reaches about 4V.
I read back the fuse value with the read command and it was indeed set to 0x36E1 as expected.
Or do I misunderstand how the LVR function works?
Thanks.
the LVR value is not a fixed place in code memory on PFS154, you have to program a SFR instead. Original PDK initialization code uses a fixed position to get a value and sets the SFR based on this.aha, so on the PFS154 they aren't using the fuse as on PMS150C, read out by hardware, to set LVR, but a regular, undocumented register you have to set in your initialization code.
I defined the SFR register names and settings for PFS154 in pfs154.h (see dev branch: https://github.com/free-pdk/easy-pdk-programmer-software/blob/development/Examples/src/easypdk/pfs154.h )
Special Function Register (SFR) name is:
MISCLVR
1) Maybe the programmer could be designed in a way to piggybag on a bluepill? This would remove the need to source the controller and solder the USB port.The Bluepill has two big downsides:
Alternatively one could switch to a more available, but slightly more expensive MCU, like the STM32F103. Does it have DFU mode? Another option: Switch to a low-cost 8051 based USB micro (WCH...). But porting the firmware will be painful...The STM32F103 does not come with a USB-Bootloader. So you would have to flash one in first. You'd need a ST-Link or similar for that, which makes first bringup much more complicated than now where you just have to hold a button.
2) There is a charge pump that generates -2.4V for the OPAMPs that control the programming voltages. This is needed to allow full voltage swing down to GND to be actually able to turn the supply voltages off. I have checked the AR358 (LM358 clone) datasheet and the output voltage swing goes down to 30mV. While this is not super-clean, pulling VPP and VDD to 30mV should be sufficient to disable the device to be programmed. SO maybe this part could be skipped and the OPAMP be connected to ground? JS, did you try this and it failed?This could maybe be optimized, but I'm not sure if it is worth it. The charge pump circuit is really small and straight forward. What could be done though is replacing the two small diodes with one BAT54S in SOT23. That would make populating it easier.
3) The step up converter comes with dual mosfet to disable power supply. The Step-up-converter itself has an enable pin that is tied tied to always active. Turning off the step-up converter using the enabled input would result in 5V on the 15V supply. However, the 15V supply is only used to feed the opamps. If using the opamps to pull VPP and VDD to ground, it would be acceptable for them to be supplied from 5V when the boost converter is inactive. I have to admit that this is not super robust, but it shold likely be fine as long as the MCU is controlling everything while the device to be programmed is connected. Thus, Q1, Q1, R7,C11,C19 could be removed? One may want to put in a filter to protect the rest of the circuit from noise, though.I think the current solution is much cleaner, because it prevents any small power glitches and similar during turnon when the STM32 is still starting up. The way it is now, the Padauk only gets powered when the STM32 is fully controlling things.
I think the current solution is much cleaner, because it prevents any small power glitches and similar during turnon when the STM32 is still starting up. The way it is now, the Padauk only gets powered when the STM32 is fully controlling things.
I like the design of the programmer as it is now, as it does what it should without unnecessary bells and whistles. The footprints and lack of silkscreen sometimes make it harder to build than necessary though. There is some work being done porting the layout to Kicad right now, see github pull requests. I think this is a good starting point for optimizations in these areas.
Actually the reference voltage inputs of the OPAMP are pulled to GND by R4 and R9, so that the voltage at VDD and VPP of the device will always be GND, unless the STM32 is fully in control. I don't think power gating the boost-converter is necessary.Ok, you are right. So one could get rid of Q1, Q2, R7 and enable the stepup from the STM32, keeping R26 as pulldown for the EN. The datasheet of the MT3608 defines EN input high as minimum 1.5V, so we are good with the 3.3V from the STM32.
Btw, I noticed that JS has optimized the BOM of the EASYPDKprog for lowerst cost at LCSC.I like the idea of opitmizing the programmer so that it can be easily populated by the JLCPCB SMT service. Unfortunately the STM32F072C and the MT3608 are both "extended" parts, so I don't see any way around that additional setup fee without creating a substantially different programmer.
JLPCB has a slightly different catalogue for part they allow to use for their assembly service. All parts in the "Basic" category do not require any addional set up cost. So, if it was possible to build the easypdkprog only from parts in the basic category, it could be ordered fully assembled at reasonable cost.
- remove negative opamp feed (diodes) - this might cause trouble during programing, but with all observations of already supported ICs an offset voltage on VDD to GND might be compensated with a higher programing voltage
(-2 diodes, -2 capacitors)
It would be more helpful to support adoption of new ICs and to create better introductions / walk throughs for beginners.
You saw Dave struggling when he tried his own "Hello World" (even that there are fully working and pre compiled examples including make files coming with the EasyPDK programmer software... He just overlooked this).
You can find the schematics below. I had to change quite a few parts. I simplified the supply a bit, as discussed above. The functionality should be exactly identical, including the not-yet-used ADC sense lines.You can get rid of another 4 resistors if you connect PB0 & PB1 to the opamp pin 2 & 6
You can find the schematics below. I had to change quite a few parts. I simplified the supply a bit, as discussed above. The functionality should be exactly identical, including the not-yet-used ADC sense lines.You can get rid of another 4 resistors if you connect PB0 & PB1 to the opamp pin 2 & 6
But on the other hand I wonder what you would measure then?You measure exactly what you're measuring with the resistor dividers R14/15/16/17, just scaled differently.
This is basically dependent on opamp gain. So it would vary depending on temperature and part-to-part variation. It would only be a very indirect indicator of supply current.Resistor dividers don't really suffer from temperature dependence. I'm not sure what this has to do with supply current.
But on the other hand I wonder what you would measure then?You measure exactly what you're measuring with the resistor dividers R14/15/16/17, just scaled differently.This is basically dependent on opamp gain. So it would vary depending on temperature and part-to-part variation. It would only be a very indirect indicator of supply current.Resistor dividers don't really suffer from temperature dependence. I'm not sure what this has to do with supply current.
In a real circuit you will measure a small delta, because the gain of the OPAMP is finite. The OPAMP gain however, depends on part-to-part variation, ambient temperature, and supply voltage in a non-predictable way. In addition we will also observe an influence of the opamp output impedance.The opamp gain is so large w.r.t. the closed-loop gain that its variance doesn't matter. The input offset voltage would have more of an effect.
The thought experiment of simplifying the schematics just shows that the information to be gained from the sense input is to be treated with caution. You can surely detect a short condition, but any attempt of measuring more nuanced information needs to be scrutinized in respect to the deviation introduced by the opamp.If you want to measure the VDD/VPP current consumption, keep R14/15/16/17 on the output of the opamp, but add a series resistor (10R should be OK) between there and the header pins; this resistor should be inside the feedback loop. I agree that the sense configuration as currently drawn is not very informative.
The opamp gain is so large w.r.t. the closed-loop gain that its variance doesn't matter. The input offset voltage would have more of an effect.Good point. Looks like the input offset for the LM358 is 5 mV and the gain is 100dB, so there is at least 2 oom difference wrt to FS output.
If you want to measure the VDD/VPP current consumption, keep R14/15/16/17 on the output of the opamp, but add a series resistor (10R should be OK) between there and the header pins; this resistor should be inside the feedback loop. I agree that the sense configuration as currently drawn is not very informative.
Ok, I had the audacity to create a preliminary "lite"-Version of the easypdkprogrammer, based on "Basic" components from the JLCPCB catalogues.
(Attachment Link)
You can find the schematics below. I had to change quite a few parts. I simplified the supply a bit, as discussed above. The functionality should be exactly identical, including the not-yet-used ADC sense lines.
The inductor, USB-port and headers have to be soldered manually. The XTAL is optional, but can still be populated. The switch is also optional. Two pins can be used instead to invoke the bootloader.
The MCU can be either populated by JLCPCB or manually.
Cost for populated PCBs without MCU is $16.95 for five, so $3.39 each. That includes the PCB, but no shipping. Cost with CPU is $26.8 for five, $5.36 a piece.
Let me know if you have additional input. I will most likely test this the next time I order at JLCPC, which could still be a while. If anybody else wants to try, i can share the design files.
p.s.: It seems that EasyEDA has updated all their libraries with slightly increased solder pad sizes. If you update the footprints, a lot of designrules in the easypdkprogrammer pcb are violated.
You saw Dave struggling when he tried his own "Hello World" (even that there are fully working and pre compiled examples including make files coming with the EasyPDK programmer software... He just overlooked this).
EDIT: Direct link to EasyPDK code examples: https://github.com/free-pdk/easy-pdk-programmer-software/tree/master/Examples <=============== CODE EXAMPLES
Awesome work Tim!
If people can buy a turn-key assembled board from JLC then that wold be awesome, but one-off's aren't practical so someone in each country couldn't make up a bunch on sell locally perhaps?
Don't JLC have a public open source projects thing?
Will this be going back into the git?
Fully agree. To be really honest, we may need to solve the issue of having example code for four different environments first. (Small C examples, Philips examples with no make file, my examples using different includes etc.).
Hi I whipped up a Code::Blocks wizard for Padauk projects at:
https://github.com/kenyapcomau/codeblocks-wizard-pdk
I don't actually have any hardware at the moment, I just tested with a dummy main.c file with SDCC 3.9 so please raise an issue at the repository if I have got anything wrong. I have a dropdown for pdk14 and pdk15. Should I add pdk13 and pdk16? Which is the best default choice in the dropdown?
You saw Dave struggling when he tried his own "Hello World" (even that there are fully working and pre compiled examples including make files coming with the EasyPDK programmer software... He just overlooked this).
EDIT: Direct link to EasyPDK code examples: https://github.com/free-pdk/easy-pdk-programmer-software/tree/master/Examples <=============== CODE EXAMPLES
Yep, missed that!
But why didn't the code I had work on the PMS150C?
Ok, done. Dropdown contains pdk{13,14,15}.
I don't know how to register and interface programs like easypdkprog to C::B. Maybe a plugin is required, I have to find out.
p.s.: It seems that EasyEDA has updated all their libraries with slightly increased solder pad sizes. If you update the footprints, a lot of designrules in the easypdkprogrammer pcb are violated.So essentially they change something in their library or program, and your project, which was previously completely fine, now requires lot's of changes just to get it into a working shape again. That is why I really dislike cloud services like this.
p.s.: It seems that EasyEDA has updated all their libraries with slightly increased solder pad sizes. If you update the footprints, a lot of designrules in the easypdkprogrammer pcb are violated.So essentially they change something in their library or program, and your project, which was previously completely fine, now requires lot's of changes just to get it into a working shape again. That is why I really dislike cloud services like this.
So I'd prefer if we move to a different EDA suite which is known for being more stable than this. I think the work being done by thomasesr in https://github.com/free-pdk/easy-pdk-programmer-hardware/pull/14 (https://github.com/free-pdk/easy-pdk-programmer-hardware/pull/14) is the better direction for going forward. A JLCPCB optimized or lite version could then be based on top of that.
No, actually they ask you if you want to update. But if you confirm, your next DRC will look aweful. Probably this can be fixed by adjusting design rules.But can you decline the update, keep the pcb untouched by their updates and still make changes to it?
No, actually they ask you if you want to update. But if you confirm, your next DRC will look aweful. Probably this can be fixed by adjusting design rules.But can you decline the update, keep the pcb untouched by their updates and still make changes to it?
I suppose that would fall under the categorisation of a Code::Blocks 'Tool'. That's how I have, for instance, stm8flash and stm8gal set up in C::B. You can use variables in the command-line parameters of each tool for things like the output file, etc.
p.s.: It seems that EasyEDA has updated all their libraries with slightly increased solder pad sizes. If you update the footprints, a lot of designrules in the easypdkprogrammer pcb are violated.So essentially they change something in their library or program, and your project, which was previously completely fine, now requires lot's of changes just to get it into a working shape again. That is why I really dislike cloud services like this.
So I'd prefer if we move to a different EDA suite which is known for being more stable than this. I think the work being done by thomasesr in https://github.com/free-pdk/easy-pdk-programmer-hardware/pull/14 (https://github.com/free-pdk/easy-pdk-programmer-hardware/pull/14) is the better direction for going forward. A JLCPCB optimized or lite version could then be based on top of that.
No, actually they ask you if you want to update. But if you confirm, your next DRC will look aweful. Probably this can be fixed by adjusting design rules.
btw: it also seems to me not useful to have a DIL tht footprint on the programmer. All the Padauk controllers come in SMD and so the board where they reside needs a socket for a kind of programming cable. So the programmer itself only needs to have also a connector for this cable.
regards
This looks like a quirks in EasyEDA... I found that it has something to do with IMPERIAL / METRIC settings and rounding.
I could prevent this by switching Units to "mil" in canvas settings, then do the PCB update, then switch back to "mm".
When I look onto the shown schematics, I think, a usual PIC programmer would do the same job. Just apply a programmable Vcc, a also programmable Vpp and a clock + data.
And do not say, that a STM32F103 cannot do the job. I append a small PIC programmer of my own. Use it as you want (if you want).
...
btw: it also seems to me not useful to have a DIL tht footprint on the programmer. All the Padauk controllers come in SMD and so the board where they reside needs a socket for a kind of programming cable. So the programmer itself only needs to have also a connector for this cable.
regards
btw: it also seems to me not useful to have a DIL tht footprint on the programmer. All the Padauk controllers come in SMD and so the board where they reside needs a socket for a kind of programming cable. So the programmer itself only needs to have also a connector for this cable.I think the DIL connector was chosen so you can easily plug in a common programming socket. I use this one: https://www.aliexpress.com/item/32716376199.html (https://www.aliexpress.com/item/32716376199.html) and it works quite well.
Your programmer uses many different component, so it also does not have a very optimized BOM for production.
HI.
Great job!.
any chance to make a simulator?... i know the IC's are cheap but....
anyway again thank's Dave for sharing this amazing work!. i have a lot to learn now. don't worry I'll RTFM before asking.
Yeah, one could actually run the bost converter from an PWM output, i know that's also done in some PIC programmers. Or one could use a lowpass filter to get a DC reference voltage. Using a DAC saves some headache for calibration though and one can use an open-loop control. if it is available in the MCU it's a better approach in my books.Your programmer uses many different component, so it also does not have a very optimized BOM for production.
Yes, this programmer has a quite different approach. It is intended to feed VCC to a board, which may consume more current than the PIC itself would need. Also it is intended to set the voltage on VCC to values from approx. 2 volts to nearly 7 volts from the supply via USB and maintains the logic levels according to this span. That's probably a bigger gun than required for programming a Padauk controller.
But there are some details in the hardware, I would like to point on: the setup of the voltages is separated from the switches, it needs only a usual PWM and it is limited by the choosen values of the resistors, so no fault can occure if the software fails to limit it to the bounds given by the manufacturer.
My problems with the easypdkprog are software problems, in particular the lacking definitions of the protocol between PC and programmer on the USB. I use to start any development by writing down the interface and protocol between different parts (like PC software and µC firmware), so the whole development can be divided into smaller parts and can be written separately.
And I love to split down the necessary functions of the programmers firmware to atomic ones, so the algorithms can be left on the PC side without making the whole procedere clumsy. If there is an interest in this, I can post it here.
Ok, I had the audacity to create a preliminary "lite"-Version of the easypdkprogrammer, based on "Basic" components from the JLCPCB catalogues.
Is this lite programmer mechanically compatible (i.e. will it fit into the same case as the normal programmer)?
The main problem I see for assembly is the USB connector. Replacing it with a through-hole part, while breaking mechanical compability, would make it easier to hand-solder (as JLCPCB does not solder connectors).
P.S.: Why not just put the design into free-pdk git, as an alternative programmer, to make it easier for people to have a closer look (and github issues might be better for discussion of individual features than this forum thread). We already have 10 repos there, so an 11th one won't hurt.
Is this lite programmer mechanically compatible (i.e. will it fit into the same case as the normal programmer)?
The main problem I see for assembly is the USB connector. Replacing it with a through-hole part, while breaking mechanical compability, would make it easier to hand-solder (as JLCPCB does not solder connectors).
P.S.: Why not just put the design into free-pdk git, as an alternative programmer, to make it easier for people to have a closer look (and github issues might be better for discussion of individual features than this forum thread). We already have 10 repos there, so an 11th one won't hurt.
Yes, it should be 100% mechanically compatible. I considered your proposal of adding a through-hole USB connector. But unfortunately those are only available as A-type plug or socket. Adding them would have required significant changes to the board layout. Also type-A connectors seem to be somewhat outdated. So I stuck with the Micro-B, but moved some components around for easier soldering.
I can add the design files and ordering instructions to the easkypdk repository after testing.
Is this lite programmer mechanically compatible (i.e. will it fit into the same case as the normal programmer)?
The main problem I see for assembly is the USB connector. Replacing it with a through-hole part, while breaking mechanical compability, would make it easier to hand-solder (as JLCPCB does not solder connectors).
P.S.: Why not just put the design into free-pdk git, as an alternative programmer, to make it easier for people to have a closer look (and github issues might be better for discussion of individual features than this forum thread). We already have 10 repos there, so an 11th one won't hurt.
Yes, it should be 100% mechanically compatible. I considered your proposal of adding a through-hole USB connector. But unfortunately those are only available as A-type plug or socket. Adding them would have required significant changes to the board layout. Also type-A connectors seem to be somewhat outdated. So I stuck with the Micro-B, but moved some components around for easier soldering.
I can add the design files and ordering instructions to the easkypdk repository after testing.
Hi,
in case this needs to be identified as a board variant (which I think might not be required) it would be a good idea to connect one of the unused STM32 pins (e.g. choose one from PB8-PB15) to GND.
This would make it possible to identify this hardware variant in the firmware and to handle things different in case it's needed.
JS
I connected PB8 to ground, so the board is identifiable. See circuit and design notes.
In hindsight it would make sense to have one pin to indicate whether a crystal is present and a few others to identify boards. Maybe we can use PB8 to GND to identify boards without crystal? I can add some other ID pins in the final version.
I connected PB8 to ground, so the board is identifiable. See circuit and design notes.
In hindsight it would make sense to have one pin to indicate whether a crystal is present and a few others to identify boards. Maybe we can use PB8 to GND to identify boards without crystal? I can add some other ID pins in the final version.
Hi,
Crystal presence can be detected in software :-)
JS
I connected PB8 to ground, so the board is identifiable. See circuit and design notes.
In hindsight it would make sense to have one pin to indicate whether a crystal is present and a few others to identify boards. Maybe we can use PB8 to GND to identify boards without crystal? I can add some other ID pins in the final version.
Hi,
Crystal presence can be detected in software :-)
JS
Even better. Is this already implemented?
Well, then I'll keep it as it is and claim "PB8=GND" as identifier for the lite version.
Regards,
Tim
Just a heads up... before you make new version.
Right now I'm working on supporting new flash types from PADAUK (PFS172 / PFC...). It looks like programing sequence changed. Now not sending high voltage on VPP (PA5) but on VDD instead. Looks like after CMD phase (2V voltage difference between VDD and VPP, e.g. 2.5 VDD / 4.5 VPP) new protocol sets VPP to 0 for read/erase/write and VDD needs to be 8.3V for write.
==> Right now programmer can not create 8.3V on VDD (we might need to change R6, maybe same value as R8 so both opamp outputs can produce same levels).
Still investigating.
JS
Regarding the PFS172: It seems it supports two programming modes, right? This is described in unusual detail in the datasheet. The current revision of easypdkprog should be able to support the limited voltage programming mode. They just don't mention why one needs the "normal mode" at all...
Regarding the PFS172: It seems it supports two programming modes, right? This is described in unusual detail in the datasheet. The current revision of easypdkprog should be able to support the limited voltage programming mode. They just don't mention why one needs the "normal mode" at all...
Maybe the reduced volatge programming mode has reduced retention? Or programming is slower?
Regarding the PFS172: It seems it supports two programming modes, right? This is described in unusual detail in the datasheet. The current revision of easypdkprog should be able to support the limited voltage programming mode. They just don't mention why one needs the "normal mode" at all...
Maybe the reduced volatge programming mode has reduced retention? Or programming is slower?
This should not be a problem at all. It also can be used to auto detect the programmer variant.
- PB0/PB1 was moved to PA0/PA1. This kept the final board size smaller and means the blue-pill's boot mode jumpers aren't blocked. I don't think this will be a problem, although it will require a software modification, and
This connection is intended to also have the button state on a GPIO so the programmer can be used in stand alone mode (later) - firmware is stored in MCU flash, no computer attachached, press button to program IC.
- PA15 isn't connected to BOOT0 (although it could be with a bodge wire). Not sure why it is on the original?
Hi,
I think I figured out "limited voltage" programing.
The logic analyzer capture showed the trick:
Programing needs 4 words on PFS172 to be programmed at same time.
In limited voltage programming mode VDD is set to 5.3V and only 1 of the 4 words is programmed (the other 3 words are all '1's, so nothing will change during programming).
After the first word is programmed, the second word of this group is programmed, ...
so instead of programing
A W W W W
it will take 4 passes:
A W X X X
A X W X X
A X X W X
A X X X W
then address is incremented and next 4 word group is programmed.
Address(A), Word(W), AllOnes(X)
This also might be a nice trick to make a real cheap programmer for the flash variants (e.g. using the 5V of Arduino and a 2 resistor voltage divider to have a second voltage to enter programing mode)
JS
This should not be a problem at all. It also can be used to auto detect the programmer variant.JS, thanks for the confirmation. :-+ I was looking at the source code, and if I am reading it correctly, it looks like I would only need to modify the code to use ADC 0/1 instead of ADC 8/9. Does that sound right?
This connection is intended to also have the button state on a GPIO so the programmer can be used in stand alone mode (later) - firmware is stored in MCU flash, no computer attachached, press button to program IC.Ahh... that makes sense. I included it on the STM32 Mini-Pill that I just posted.
Due to the high number of different pinouts on the 8-pin Padauk devices, I had to create five different variants of the minimal evaluation boards:
https://github.com/free-pdk/f-eval-boards
This also might be a nice trick to make a real cheap programmer for the flash variants (e.g. using the 5V of Arduino and a 2 resistor voltage divider to have a second voltage to enter programing mode)
spth: I was looking at this repo yesterday and found myself desiring to see a preview of these boards. Maybe there is one somewhere and I just didn't see it? I'm not even sure what to do with the .sch and .lht files to generate my own. (What tool are those files for?) Would it be possible for you to upload some .pngs of the boards and schematics to the repo?
Tools used:
* gschem for the schematic (symbols used to be found in pdk-gschem-symbols repository)
* pcb-rnd for the pcb design
Padauk is not making any money selling the programmer, so why don't ask them for the programming protocol?Companies are reluctant to publish information that might want to change at any time. If they want to alter the silicon, maybe to change fabs or for a die shrink, and change the protocol, its a nightmare trying to deal with an open ended set of tools.
Adding support for universal programmers like TL866 can help sell tons of 3cent microcontrollers.Nobody buys a ton of parts and programs them with a tool like the TL866. People only program handfuls with a TL866, and nobody gets rich selling 3 cent parts by the handful.
Would adding some photographs of the assembled boards help (even though it would show how bad I am at hand-soldering)?Yes, photos of the boards would help a lot! If possible, a screenshot of the schematics would also help. Having both of these would allow people to review/troubleshoot without downloading files and opening them in an external program.
I realize you are responding to a several year old post, and I agree that Padauk is not likely to release the programming protocol, unfortunately. But, I would imagine if they did change the silicon in a way that changed the programming protocol they would also have to release an update to their own programmer and they would probably release the IC with a different part number anyway.Padauk is not making any money selling the programmer, so why don't ask them for the programming protocol?Companies are reluctant to publish information that might want to change at any time. If they want to alter the silicon, maybe to change fabs or for a die shrink, and change the protocol, its a nightmare trying to deal with an open ended set of tools.
Would adding some photographs of the assembled boards help (even though it would show how bad I am at hand-soldering)?Yes, photos of the boards would help a lot! If possible, a screenshot of the schematics would also help. Having both of these would allow people to review/troubleshoot without downloading files and opening them in an external program.
For now, because of availability and cost, I find the PFS154 and PFS173 to be more interesting than the PFS172 which isn't currently stocked at lcsc.
Also, do you know the current status of the PMS152 when used with the easy-pdk-programmer? Is it still read-only, or has the write mode been written/tested? The PCS152-S16 is currently the cheapest 16-pin variant on lcsc and I was thinking of picking some up in addition to the flash variants if they are likely to work.
Well, it is good to have device support early, getting ahead of LCSC a bit.Oh yes, I agree completely. Actually, I forget my original point now... I think it was more around wondering if the low voltage programming would also work on the earlier (already widely available) flash parts PFS154 and PFS173, or if those are only high voltage programmable. If the low voltage mode would work on those, it would be interesting to work on a much cheaper / more available programmer to potentially accelerate adoption.
One device I am looking forward to (said to be released in Q3) is the PGC434.That does indeed look interesting (depending on cost). Where did you find that it would be released in Q3? I do see it referenced in this doc (https://www.netvisiontek.com/pdfs/selection_guide_2019H1__20190227_EN.pdf (https://www.netvisiontek.com/pdfs/selection_guide_2019H1__20190227_EN.pdf)), but am not finding much information otherwise. I suppose since it is a multi FPPA IC, using SDCC would be out of the question for now, right? Maybe I understand incorrectly, but I thought the easy pdk programmer only works with SDCC .hex files, and not output from the official compiler?
I'v added both now (though I left out the photo of the f-eval-pdk-s08b with PFC161, since my hand-soldering looks worst there):Thank you! Those photos and drawings are very helpful. And your soldering looks fine. :-+
Oh yes, I agree completely. Actually, I forget my original point now... I think it was more around wondering if the low voltage programming would also work on the earlier (already widely available) flash parts PFS154 and PFS173, or if those are only high voltage programmable. If the low voltage mode would work on those, it would be interesting to work on a much cheaper / more available programmer to potentially accelerate adoption.According to the datasheets, both support a limited-voltage programming mode.
One device I am looking forward to (said to be released in Q3) is the PGC434.That does indeed look interesting (depending on cost). Where did you find that it would be released in Q3? I do see it referenced in this doc (https://www.netvisiontek.com/pdfs/selection_guide_2019H1__20190227_EN.pdf (https://www.netvisiontek.com/pdfs/selection_guide_2019H1__20190227_EN.pdf)), but am not finding much information otherwise. I suppose since it is a multi FPPA IC, using SDCC would be out of the question for now, right? Maybe I understand incorrectly, but I thought the easy pdk programmer only works with SDCC .hex files, and not output from the official compiler?
I see two capacitors, one on the USB input of 0.1uF and one on the MCU side of the diode that is 0.01uF. I assume the one on the MCU side of the diode is a bypass capacitor? If so, why not the more normal 0.1uF/100nF for that one?Yes, it is a bypass capacitor. According to the datasheets, 0.01 µF is both the recommended value and the maximum allowed for in-circuit programming. Apparently during programming, VDD needs to change quickly, and higher capacitance would interfere with that.
And, what is the point of the capacitor on the USB side of the diode?But 0.01 µF also seems a bit low, especially when the board is powered via a potentially long USB cable, so I added another capacitor on the USB side.
Speaking of the diode, I assume it is just there to make sure voltage isn't back-fed into the USB connector if you happen to power this through the programmer or breadboard pins, right?The main purpose is indeed to protect a USB hub, port, or whatever the other end of the USB connector is plugged in, from back-fed voltage. And it allows me to place that extra capacitor.
I finally got around documenting my last project with the Padauk MCU. It's a chainable 7 segment disaply, where each segment is controlled by PFS154.
It's not too exciting, but I thought it was a suitable application for a 3 cent MCU and is a nice testbed to play around with networking protocols.
You can find a writeup here: https://cpldcpu.wordpress.com/2020/04/05/addressable-7-segment-display/ (https://cpldcpu.wordpress.com/2020/04/05/addressable-7-segment-display/)
Btw, one nice trick I found during the design was to use a SOIC8-clamp for programming (see attachment). All Padauk MCU have their supply and programming pins arranged in a way that easily allows doing this. No need to add any ISP connectors. You can get these very cheap on aliexpress and ebay.
Thanks for the clarification. I am looking at the datasheet for the PFS154, and on page 85 it mentions a capacitor on VDD/GND of less than or equal to 0.1uF. I don't see any mention of 0.01uF. Did that come from a different datasheet? Also, the easy-pdk programmer itself already has a 0.1uF capacitor on the VDD line. Are these in conflict with each other then?I see two capacitors, one on the USB input of 0.1uF and one on the MCU side of the diode that is 0.01uF. I assume the one on the MCU side of the diode is a bypass capacitor? If so, why not the more normal 0.1uF/100nF for that one?Yes, it is a bypass capacitor. According to the datasheets, 0.01 µF is both the recommended value and the maximum allowed for in-circuit programming. Apparently during programming, VDD needs to change quickly, and higher capacitance would interfere with that.
Ok, that makes sense. Surely something 1uF or higher would be better here, right? I guess it is a 0805, so higher uF caps can be installed as needed.And, what is the point of the capacitor on the USB side of the diode?But 0.01 µF also seems a bit low, especially when the board is powered via a potentially long USB cable, so I added another capacitor on the USB side.
Yep, makes sense.Speaking of the diode, I assume it is just there to make sure voltage isn't back-fed into the USB connector if you happen to power this through the programmer or breadboard pins, right?The main purpose is indeed to protect a USB hub, port, or whatever the other end of the USB connector is plugged in, from back-fed voltage. And it allows me to place that extra capacitor.
Thanks for the clarification. I am looking at the datasheet for the PFS154, and on page 85 it mentions a capacitor on VDD/GND of less than or equal to 0.1uF. I don't see any mention of 0.01uF. Did that come from a different datasheet? Also, the easy-pdk programmer itself already has a 0.1uF capacitor on the VDD line. Are these in conflict with each other then?I see two capacitors, one on the USB input of 0.1uF and one on the MCU side of the diode that is 0.01uF. I assume the one on the MCU side of the diode is a bypass capacitor? If so, why not the more normal 0.1uF/100nF for that one?Yes, it is a bypass capacitor. According to the datasheets, 0.01 µF is both the recommended value and the maximum allowed for in-circuit programming. Apparently during programming, VDD needs to change quickly, and higher capacitance would interfere with that.
Ok, that makes sense. Surely something 1uF or higher would be better here, right? I guess it is a 0805, so higher uF caps can be installed as needed.And, what is the point of the capacitor on the USB side of the diode?But 0.01 µF also seems a bit low, especially when the board is powered via a potentially long USB cable, so I added another capacitor on the USB side.
Thanks for the clarification. I am looking at the datasheet for the PFS154, and on page 85 it mentions a capacitor on VDD/GND of less than or equal to 0.1uF. I don't see any mention of 0.01uF. Did that come from a different datasheet? Also, the easy-pdk programmer itself already has a 0.1uF capacitor on the VDD line. Are these in conflict with each other then?I see two capacitors, one on the USB input of 0.1uF and one on the MCU side of the diode that is 0.01uF. I assume the one on the MCU side of the diode is a bypass capacitor? If so, why not the more normal 0.1uF/100nF for that one?Yes, it is a bypass capacitor. According to the datasheets, 0.01 µF is both the recommended value and the maximum allowed for in-circuit programming. Apparently during programming, VDD needs to change quickly, and higher capacitance would interfere with that.
Which PFS154 datasheet? In version 1.03 of the datasheet, page 87 I see the less than or equal to 0.1 µF. In version 1.05, page 89 it is less than or equal to 0.01 µF.
easy-pdk programmer has in it it needs to be able to deal with. I guess Padauk datasheets assume their programmer (another programmer might be able to sink or source current more quickly to charge or discharge the capacitor).
I noticed that you opened an issue on github about moving from gEDA schem to leptop. Is there a reason you aren't considering KiCad, which as far as I know, has a much broader user base and is more cross platform compatible? I would be more than happy to convert the files over for you, if interested.I don't design electronics often (so I definitely don't want to put much time into learning new tools), but when I did in the past I used gEDA. Now the original gEDA looks more and more like a dead end. But with pcb-rnd fork of pcb and lepton fork of the rest of gEDA are well-maintained successors available, so I can continue that way.
The LEDs are configured backwards compared to what I am used to seeing. Usually the MCU sinks them down to ground instead of sourcing voltage to them. I think this is because most MCUs are able to sink current better than sourcing it. I'm not as familiar with the Padauk MCUs yet, but wondering if you took that into consideration?
Since this is a dev board (i.e. in-circuit programming) maybe it should be targeting the On-Board/In-Circuit/Limited-Voltage mode that JS is working on?
Fair enough, although you may want to think about adding the isolation (>10k resistors or <220p capacitors) to pins PA3, PA5, PA6 that they talk about in the On-Board wiring section on page 90. Actually, if you moved the 15k resistors and LEDs to these pins, you could kill two birds with one stone potentially. And it would make things more consistent between boards, as some of the smaller ICs don't even have PBx pins. Might want to make them sink instead of source if you did that based on the comment on page 90: "In general, the writing signal pins PA3, PA5 and PA6 SHOULD NOT be considered as strong output pins."Since this is a dev board (i.e. in-circuit programming) maybe it should be targeting the On-Board/In-Circuit/Limited-Voltage mode that JS is working on?
Thess boards are quite minimal, so for now I'm just trying to keep them compatible with both modes.
That might be less of a priority for a future board with a bit more features that I intend design once the PGC434 datasheet becomes available.
Thank you for taking the time to explain your design choices. I will probably create my own version anyway, as my priorities are a bit different. For one, I would rather have a narrower board that is a bit more optimized for use in a breadboard.
Thanks!I finally got around documenting my last project with the Padauk MCU. It's a chainable 7 segment disaply, where each segment is controlled by PFS154.
It's not too exciting, but I thought it was a suitable application for a 3 cent MCU and is a nice testbed to play around with networking protocols.
You can find a writeup here: https://cpldcpu.wordpress.com/2020/04/05/addressable-7-segment-display/ (https://cpldcpu.wordpress.com/2020/04/05/addressable-7-segment-display/)
tim_, Awesome project! It really helps show the usefulness of such inexpensive devices.
I was reading through your article and source code last night and had a couple of thoughts that I wonder if you had considered:Yes, there are many protocol enhancements and variants that could be tested. Autobauding is a nice idea. One could also do direct clock recovery by introducing pseudo-manchester? The challenge is to combine this with a standard UART interface, although one could also move away from that.
- Because you are only using 5 of 8 bits, I think it would be fairly easy to add autobaud capabilities to support a much wider (and variable) range of baud rates. Basically make sure that bit 0 is always a '1' and then the length of the start bit can be measured to use for the delay loops
EOT by timeout: This is how it is done in the WS2812. I opted not do go this way, because it forces stringent timing requirements on your protocol. What if the datastream from the host-device is paused for some reason, for example an interrupt or a task switch?
- The EOF could be removed by instead using a counter variable on the idle state (slightly more efficient protocol). So, inside the interrupt (re-)set a counter variable to 255 (or some number) and then in the main loop decrement the counter variable and enable/change the output when it reaches 0. So, as long as new bytes are being shifted in, the counter variable keeps getting reset, but once idle the output gets latched after some short delay. Obviously the delay would have to be longer than the expected time between each byte for this to work right.
Sure, but the point of the design was to use one MCU per Display :)
- It looks like there are two extra pins available, so it seems like a single IC could easily support two 7-segment displays by using multiplexing. Obviously it would mean adding two transistors or mosfets and changing the main loop to time divide between the two, and the interrupt code to stay in receive mode for longer. But might be slightly cheaper end result, and how often is just one 7-segment useful anyways. EDIT: Actually I just noticed that there are two other pins that are only being used for ICP that could also be used to make a 4x 7-segment multiplexed display with one IC. If on-board programming is needed, isolation resistors might be required.
Well, why would you limit it to 8 devices? But anyhow, one could also imagine a protocol with packet routing that directly allows to address specific devices. There could be an autonumeration phase where the devices assign addresses to themselves based on the position in the chain.
Another thought is that it is unlikely to often need a chain of more than about 8 of these to begin with, so potentially the 3 un-used bits in each byte could be used as an address, meaning each one could be directly connected to the input (instead of being chained), and they would only update when their address matched.Now that I think about some more, each one would have to know what their address is, which would mean giving up on 2 displays per MCU (need the pins for address setting), and would also have to give up on autobaud (need all 3 un-used bits), and would be limited to only 8 displays, so probably not worth looking into.
The output drivers of the PDK MCUs are unusually weak. They barely drive 10mA. You can connect any LED to it without series resistor. Whether that is a good and stable design is another question, though...
- I'm curious if the current limiting resistor is needed at all? It looks like the IO pins can only source/sink so much current anyway, although it is unclear if damage would occur without the resistor, or if the IO pins would just naturally limit the current?
- Final thought (for now)... I wonder if it is possible/useful to implement sleep mode after setting/changing the outputs? The pin change interrupt will wake the device when communication occurs, although it might take longer for the interrupt to be invoked (has this latency been tested yet?) Again, this may not be worth it because these MCUs take less than 1mA anyways (a fraction of what the 7-segment LEDs take), and if using two display with multiplexing then sleep mode gets more complicated (might be able to use a wake-up timer to sleep between alternating digits). Another option might be to lower the system clock when doing the multiplexing in the main loop, and raise it again in the interrupt (again not sure how that impacts the interrupt latency)
One topic I can really relate to is that there are many breakout boards that have too much PCB overhang next to the headers. This basically wastes one row of pins for nothing. Philipp, your boards are also guilty of this, see pic :).On the other hand, that overhang makes it easier to route stuff (e.g. to the LEDs and the programming header). But feel free to open an issue on GitHub, so I'll check if I could reroute to save that one row on each side. [Edit: I just opened the issue myself: https://github.com/free-pdk/f-eval-boards/issues/3]
Also, how about introducing some silkscreen description of the pins and the device?I don't want to add silkscreen forthe device (as each board can be used for multiple devices, as long as thtey have the same pinout. But I indeed want to add silkscreen for the pins in the next version.
I would also add a copper fill as a ground plane as best practice, but it probably has little impact in this case.There already is (on the bottom side).
One topic I can really relate to is that there are many breakout boards that have too much PCB overhang next to the headers. This basically wastes one row of pins for nothing. Philipp, your boards are also guilty of this, see pic :).On the other hand, that overhang makes it easier to route stuff (e.g. to the LEDs and the programming header). But feel free to open an issue on GitHub, so I'll check if I could reroute to save that one row on each side.
You could reduce the copper trace width for easier routing. Since the Padauk cannot drive high currents anyways, 10mil lines should be more than sufficient.
If you need something narrow for breadboards, directly using DIP devices might also be an option for you.]
I usually use stock breakout-boards when I want to test a device on a breadboard. See pic. You can get them on ebay or aliexpress for next to nothing.
One topic I can really relate to is that there are many breakout boards that have too much PCB overhang next to the headers. This basically wastes one row of pins for nothing. Philipp, your boards are also guilty of this, see pic :).
On other occasions, I have directly mounted the device in the target circuit and used a SOIC clamp for programming.
I will probably create my own version anyway, as my priorities are a bit different. For one, I would rather have a narrower board that is a bit more optimized for use in a breadboard.
Hi,
Today I started working on PFC154 (industrial part?) and to my surprise after analyzing the READ and WRITE I found:
PFC154 program word = 14 bits, but read / write using 19 bits.
5 extra bits are attached to the beginning of every program word. Some extra bits usually are for error corrections, lets' see..
Some samples from logic analyzer reading: 14 bit data => 5 extra bits:
3FFF => 1F
0070 => 08
2F00 => 0E
0182 => 04
First try: classic Hamming ECC
Confirmation by using this web site http://www.ecs.umass.edu/ece/koren/FaultTolerantSystems/simulator/Hamming/HammingCodes.html (http://www.ecs.umass.edu/ece/koren/FaultTolerantSystems/simulator/Hamming/HammingCodes.html)
After entering the binary 14 bit values from above, website will show result attached to the end of the bistring.
=> All matching! It is a classic Hamming ECC using the standard syndrom :)
It is a bit unexpected, but it looks like the "industrial grade parts" are really having some extra features.
JS
Today I started working on PFC154 (industrial part?) and to my surprise after analyzing the READ and WRITE I found:Nice find, thanks for sharing.
[Original post for STM32 "mini-pill" (1/2 Blue Pill)]
...I decided to go ahead to create a bottom board... I call this the STM32 Mini-Pill. It is essentially 1/2 of the infamous "Blue-Pill" board...
[Original post for STM32 "mini-pill"/"blue-pill" Padauk Programmer Top Hat]
...I ended up creating a (mostly compatible) variation that is a top-hat for said boards...
>easypdkprog -v probe
Probing IC... found.
TYPE:FLASH RSP:0xAA1 VPP=4.50 VDD=2.00
IC is supported: PFS154 ICID:0xAA1
>easypdkprog -n PFS154 write Examples\helloworld_pfs154.ihx
Erasing IC... done.
Writing IC... done.
Calibrating IC
* IHRC SYSCLK=8000000Hz @ 4.00V ... calibration result: 7951482Hz (0x84) done.
>easypdkprog -n PFS154 -r 4.0 start
Running IC (4.00V)... IC started, press [Esc] to stop.
Hello World!
Hello World!
IC stopped
Here's a few more pictures.
I cleaned up the board-to-board connection, and removed the unused pins on the overhanging section of the IC socket. I kinda like leaving the overhang because it protects the otherwise exposed pins of the zif adapter.
Here's a few more pictures.
I cleaned up the board-to-board connection, and removed the unused pins on the overhanging section of the IC socket. I kinda like leaving the overhang because it protects the otherwise exposed pins of the zif adapter.
That looks like a very clean design! This should certainly be attractive for people who want to build and populate their own programmer. Maybe you should switch the two tiny diodes to larger ones, so it is still possible to work without a microscope :)
I love the puzzle and art of pcb design. I'm a bit jealous of being able to use 0603 or 0402 sized components, because it looks like they can really help shrink the board size further, and provide more layout options. But, I just find them too small to be worth trying to hand solder, and I am not ready to commit to automated assembly yet. If I make a second version of the programmer top hat, I will look into using larger sized diodes, but for now I have no use for any more programmer boards, so no incentive for a re-spin at the moment.
I also started my own repository to gather Padauk documentation, library files, and source code for my projects (https://github.com/serisman/Padauk). I don't mean to compete with anything you or JS or spth have done, but I needed to get some of what I was working on checked in and backed up so it wasn't just on my hard drive. At the very least it is a play area to try some things out slightly differently than the other repos.
I love the puzzle and art of pcb design. I'm a bit jealous of being able to use 0603 or 0402 sized components, because it looks like they can really help shrink the board size further, and provide more layout options. But, I just find them too small to be worth trying to hand solder, and I am not ready to commit to automated assembly yet. If I make a second version of the programmer top hat, I will look into using larger sized diodes, but for now I have no use for any more programmer boards, so no incentive for a re-spin at the moment.
I love it too, it's almost like meditation :). You should look into the JLCPCB assembly service, it's probably much cheaper than you think.
I also started my own repository to gather Padauk documentation, library files, and source code for my projects (https://github.com/serisman/Padauk). I don't mean to compete with anything you or JS or spth have done, but I needed to get some of what I was working on checked in and backed up so it wasn't just on my hard drive. At the very least it is a play area to try some things out slightly differently than the other repos.
Well, I basically only have my own repository because my toolchain is a bit different from the one in the free-pdk repository. We should somehow all work together on cleaning that up and create better documentation so other people have a less steep learning curve. Maybe we could activate the Wiki on Github?
I think different widths are a good idea. I personally don't think breakout boards are worth it (especially for the OTP types), but some people may prefer to work that way.
- I added a second pin header to allow plugging in wide breakout boards. More about this below. Unfortunately this means that the programmer will not fit into JS casing anymore without using a hacksaw... Let me know if you think this is a bad idea.
JS,
FYI... I just submitted a Pull Request (https://github.com/free-pdk/easy-pdk-programmer-software/pull/25) for adding preliminary support for PMS152 as well as fixed a few bugs that I found after researching the datasheets and Padauk IDE files. I tried to write a PMS152, after un-commenting the appropriate code in fpdkicdata.c and re-compiling easypdkprog. It seemed to mostly write correctly, but failed on calibration, and when read back, there are a few differences. So, it may require some more code changes in easypdkprog before it is fully supported. I already wasted two ICs before deciding to stop until someone more familiar with the code could take a look.
JS,
FYI... I just submitted a Pull Request (https://github.com/free-pdk/easy-pdk-programmer-software/pull/25) for adding preliminary support for PMS152 as well as fixed a few bugs that I found after researching the datasheets and Padauk IDE files. I tried to write a PMS152, after un-commenting the appropriate code in fpdkicdata.c and re-compiling easypdkprog. It seemed to mostly write correctly, but failed on calibration, and when read back, there are a few differences. So, it may require some more code changes in easypdkprog before it is fully supported. I already wasted two ICs before deciding to stop until someone more familiar with the code could take a look.
Hi,
Writing of PMS152 was never tested from me. I just copied some values around to have place holders. A capture with logic analyzer is needed to reveal full details.
=> Do you still have the exact same hex file you wrote and a read back from the IC?
Until now there was no demand for PMS152 so it was pushed back on my list.
But, since you really try to develop something for this IC and you also open sourced your project I'm more than motivated to put PMS152 on top of the list now :)
I had a brief look at your PMS152.h and it looks good.
Some things I noticed:
- it looks like you used the main branch as source since some of the unknown ROP defines are already deciphered and in development branch (see PFS173.h).
- you should try the H9 and L9 macro for IHRC/ILRC calibration since it might be that PADIER needs to be set explicit in order to get input (development branch has H9/L9 macros and easypdkprog has calibration code for H9/L9 14 bit).
=> You also should target your pull requests to the development branch.
JS
=> You also should target your pull requests to the development branch.
JS,
I re-targeted my pull request to the development branch, re-applied my mini-pill changes, re-build and uploaded the new 1.3 firmware, and re-compiled easypdkprog. But now I can't even probe OTP ICs (I tried both PMS150C and PMS152). Flash based ICs still seem fine (I can probe/erase/write/read to both PFS154 and PFS173). So, it seems like OTP support may be broken right now in the development branch. Can you duplicate this on your end?
>easypdkprog -n PMS152 write Examples\helloworld_pms152.ihx
Writing IC (186 words)... done.
Calibrating IC
* IHRC SYSCLK=8000000Hz @ 4.00V ... calibration result: 8006747Hz (0x4E) done.
>easypdkprog -n PMS152 -r 4.0 start
Running IC (4.00V)... IC started, press [Esc] to stop.
Hello World!
Hello World!
IC stopped
- you should try the H9 and L9 macro for IHRC/ILRC calibration since it might be that PADIER needs to be set explicit in order to get input (development branch has H9/L9 macros and easypdkprog has calibration code for H9/L9 14 bit).
I think different widths are a good idea. I personally don't think breakout boards are worth it (especially for the OTP types), but some people may prefer to work that way.
- I added a second pin header to allow plugging in wide breakout boards. More about this below. Unfortunately this means that the programmer will not fit into JS casing anymore without using a hacksaw... Let me know if you think this is a bad idea.
I think different widths are more interesting to fit different kinds of IC sockets, so sourcing fitting ones becomes easier. Currently you need ones with 7.62mm spacing, but some seem to me like they have 10.16mm spacing:
https://www.aliexpress.com/item/1107288077.html (https://www.aliexpress.com/item/1107288077.html)
I think you'd have to add another row for them, but that shouldn't be a problem.
As the case is 3d printed, I don't think it is an issue to change it.
- you should try the H9 and L9 macro for IHRC/ILRC calibration since it might be that PADIER needs to be set explicit in order to get input (development branch has H9/L9 macros and easypdkprog has calibration code for H9/L9 14 bit).
JS,
It looks like the 14 bit version is H10, not H9, and there is not yet a L10 equivalent. Does that seem correct? If so, I can add the L10 equivalent. Looks like we need a new equivalent of B1A for bandgap calibration as well.
Also, it looks like H10 starts off at 0x00 instead of 0xFF, meaning the first measured value is 0x01 instead of 0x00. Doesn't that mean the calibration value will also be off by one (or is that tweaked elsewhere)?
I'm wondering if we would be better off getting SDCC to add the PADIER=0xFF (and any other needed default overrides) as part of the initialization code so we don't have to have so many different calibration routines, and our programs can then rely on the same defaults across MCUs as well. I think the Padauk IDE already does it this way. Maybe if SDCC can't/shouldn't do it, we can find a way to insert it in the IC specific .h include files.
during development for PFS172 I found that using a value of 0xFF in IHRCR locked up the IC so I created the 10 variant (1 more instruction to start with 0 - the new offset is respected in calibration)
I think we should rework calibration to use the "works for all" 10 version for all IC variants, even if it "wastes" 2 instructions in code memory on some ICs.
I also plan to make a more generic calibration routine so we can specify the location of ILRCR and BGTR register as a parameter in tuning macro.
struct PORT_bits
{
uint8_t p0:1;
uint8_t p1:1;
uint8_t p2:1;
uint8_t p3:1;
uint8_t p4:1;
uint8_t p5:1;
uint8_t p6:1;
uint8_t p7:1;
}; // __attribute__((__packed__));
#define BF_PA (*(volatile struct PORT_bits *)&PA)
void main(void)
{
PAC |= _BV(LEDPIN); // This syntex will infer set0/set1
for (;;) {
BF_PA.p0=1;
// PA ^= _BV(LEDPIN); // Toggle LED
delay_ms(500);
BF_PA.p0=0;
delay_ms(500);
}
}
SDCC : gbz80/tlcs90/z80n/pic14/ds400/pdk13/pdk14/pdk15 4.0.2 #11683 (Linux)
260 ; bitfields.c: 55: BF_PA.p0=1;
000040 01 2F 261 mov a, #0x01
a 000042 262 or _pa+0, a
...
00004C FE 2F 270 mov a, #0xfe
a 00004E 271 and _pa+0, a
I got my dev boards in the mail today, and soldered one up with a PFS173-S16 this evening. I'll build another one with a PFS154-S16 later.Nice! I like the pin descriptions.
I did have to change the resistor on PA6 to 22k (instead of the 10k that the PA3,PA4,PA5 are able to use) in order to actually successfully program the IC through the header. The datasheet seems to indicate that 10k is all the isolation that's needed, but the characteristics of the easy-pdk-programmer must be different. Maybe the timing could be adjust to compensate? I'm not sure why the other pins seem fine with 'only' 10k resistors though.The original programmer probably uses a bus driver to convert the logic levels to ones that are consistent with VDD of the device. That should improve noise immunity a bit.
The other 'issue' I noticed is that the programmer appears to be pulling PA5 low while it is connected, even while it is idle. This makes the code think that the button is always pressed (and the PA5 LED is always lit up). If the programmer is disconnected, it works properly. I think the programmer is trying to idle (i.e. high-z) the line, but the op-amp is pulling it low. I reported this as an issue in GitHub, but I'm not sure if anything can or
will be done about it. Possibly the easiest solution would be to allow the programmer to idle the PA5/VPP line high (maybe through an extra command line option with easypdkprog?).
I whipped up an example program that makes use of the on-board LEDs and BTN.
setPinOutput(PIN_LED2);
Code: [Select]setPinOutput(PIN_LED2);
Do we really have to copy the Arduino style? With bitfields (see above) we could directly turn individual pins into variables so you can write e.g. PA5=1;. The compiler should be able to generated optimal code once fixed.
Code: [Select]setPinOutput(PIN_LED2);
We, of course don't have to do anything. ;) That code is easily changeable if/when something better is available.
If you don't like that, don't look at some of the more recent updates I just pushed. >:D
Code: [Select]setPinOutput(PIN_LED2);
We, of course don't have to do anything. ;) That code is easily changeable if/when something better is available.
If you don't like that, don't look at some of the more recent updates I just pushed. >:D
You mean "setup()" and "main()"? Well ... :)
Of course an optional Arduino-like include could not hurt.
But I was thinking there is a lack of consistency in the general toolchains that exist around PDK. It would be good to have at least one point of reference that we can all agree on extending on together. (olbigatory: https://xkcd.com/927/)
There are now at least 4 different repositories that have examples sitting somewhere in a deeply nested folder. All of them based on a different set of system includes. But as someone wanting to start development, it is simply a pain to find somethign that is consistent.
For example, there are still glaring issues when trying to use "printf" (Some of the examples use "puts" for a reason) . I implemented some optimized routines that took a lot of effort, to be at least able to do basic printf-style debugging (https://github.com/cpldcpu/SimPad/blob/master/Toolchain/library/PDK_softuart.c), but there is simply no place to put them oither than my own repositiy.
I also still don't know how to build a librariy with conditional linking of functions to be able to cope with the limited program memory.
Could we agree on starting a new repository on "free-pdk" that contains a central repository for the toolchain and examples? (Also looking at JS and Phillipp)
I got my dev boards in the mail today, and soldered one up with a PFS173-S16 this evening. I'll build another one with a PFS154-S16 later.
I agree. But we aren't there yet. I did start working on a refactoring of the include files on a branch in the easy-pdk-programmer-software repo earlier today, with a goal of trying to clean it up a bit, make it more extensible, and separate out the easy-pdk specific code from the more general pdk stuff that maybe could eventually be packaged into SDCC. If you have a chance, take a look and provide feedback on the (work-in-progress) pull request: https://github.com/free-pdk/easy-pdk-programmer-software/pull/33. Please keep in mind this isn't 'finished' or 'ready to use' yet, and maybe not all the ideas I was playing around with are good ideas, so please be gentle. ;DSounds reasonable
Even if I do go the pdkuino route with my repo, it would ideally just be a layer on top of the base pdk include files, not a replacement for them.
For example, there are still glaring issues when trying to use "printf" (Some of the examples use "puts" for a reason) . I implemented some optimized routines that took a lot of effort, to be at least able to do basic printf-style debugging (https://github.com/cpldcpu/SimPad/blob/master/Toolchain/library/PDK_softuart.c), but there is simply no place to put them oither than my own repositiy.
I also still don't know how to build a librariy with conditional linking of functions to be able to cope with the limited program memory.
Yeah, the limited resources are definitely something we have to find a way to manage. I haven't tried to use printf-style debugging yet, mostly because I assumed it would be too resource intensive. For the things I have been playing around with so far, a logic analyzer is actually more useful anyway.
For SDCC, the only way I have found for it to have conditional linking (or exclusion of unused functions) is if each one is in it's own file and compiled into a library. I think the SDCC manual mentions that somewhere. My toolchain is setup in this fashion, although it's hard to see it working since I only have one library file checked in so far.
Could we agree on starting a new repository on "free-pdk" that contains a central repository for the toolchain and examples? (Also looking at JS and Phillipp)
I personally don't have access to the free-pdk repos to start something like that, but would be happy to collaborate there if that was setup.
I used 22k resistors for all the LEDs on this one, but for some reason I can't program it at all with any resistor on the PA6 pin (I also tried 33k and 47k). It could be that the IDC cable has higher resistance, or maybe the PFS154 is more sensitive than the PFS173, or maybe using 22k instead of 10k resistors on the other pins is affecting it in some way. I'll have to do more testing later, but just taking the one resistor off makes it work again (although the LED won't work without it).
(Attachment)
QuoteI used 22k resistors for all the LEDs on this one, but for some reason I can't program it at all with any resistor on the PA6 pin (I also tried 33k and 47k). It could be that the IDC cable has higher resistance, or maybe the PFS154 is more sensitive than the PFS173, or maybe using 22k instead of 10k resistors on the other pins is affecting it in some way. I'll have to do more testing later, but just taking the one resistor off makes it work again (although the LED won't work without it).
(Attachment)
Have you looked at the voltage levels on PA6 with a scope? Btw, is your resistor pulling up or down?
QuoteI used 22k resistors for all the LEDs on this one, but for some reason I can't program it at all with any resistor on the PA6 pin (I also tried 33k and 47k). It could be that the IDC cable has higher resistance, or maybe the PFS154 is more sensitive than the PFS173, or maybe using 22k instead of 10k resistors on the other pins is affecting it in some way. I'll have to do more testing later, but just taking the one resistor off makes it work again (although the LED won't work without it).
(Attachment)
Have you looked at the voltage levels on PA6 with a scope? Btw, is your resistor pulling up or down?
I haven't. I probably need a new scope. Mine is ancient (a really old Tektronix 2213A - 60MHz analog crt scope) and kind of a pain to use. I've been thinking about getting a newer digital storage scope for a while now. Have any recommendations for a reasonable one?
The resistors are pull-up.
(Attachment Link)
Hm... the combination of pull-up (your board) and pull-down on PA5 (programmer) will surely lead to an undefined potential between GND and VDD. The impedance on PA6 should be high enough, though. No obvious reason why it would not work?
I made an 8 pins Padauk micro breakout board. I want to share my design with you guys so you guys can use it.
https://easyeda.com/LovelyA72/ezpdk8
It acts as an adapter board between SOP and DIP. Also, since most of the padauk micros are OTP, I can write the name of the program on the board with a sharpie(white silkscreen area). It also marks the pinout for the chip to make the chip more convenient to work with.I made an 8 pins Padauk micro breakout board. I want to share my design with you guys so you guys can use it.
https://easyeda.com/LovelyA72/ezpdk8
Thanks for sharing. It looks pretty basic, the only additional component appears to be a bypass capacitor. Can you explain your thoughts on why you prefer this over just using a generic SOP-8/16 adapter PCB or SOP-8/16 ZIF socket to DIP8/16 adapter?
ihrcr = *((const unsigned char*)(0x87ed));
// took me hours to find where from the 0x8000 comesI also built the free-pdk programmer and started to learn Padauk microcontroller. I finished reading PFS154 datasheet and SDCC manual.
A few parts are pretty challenging for beginners, for example the calibration..., it took me almost a whole day to figure out how the hello world program works. :phew:
This was the most diifficult hello world code I've ever seen :)Code: [Select]ihrcr = *((const unsigned char*)(0x87ed));
// took me hours to find where from the 0x8000 comes
https://github.com/free-pdk/sdcc-pdk-code-examples/blob/master/hello-s16/hello.c
I don't complain, I am very happy to find this topic, you guys made excellent job.
Anyway I am not sure for beginners it is a good idea to start with SDCC. Are there any pure assembler available for this MCU for those who don't want to buy the Padauk programmer?
Anyway I am not sure for beginners it is a good idea to start with SDCC. Are there any pure assembler available for this MCU for those who don't want to buy the Padauk programmer?
Work is underway to try and standardize include files and example programs: (e.g. https://github.com/free-pdk/easy-pdk-programmer-software/pull/33)
I have published some i2c slave code examples for PFS154/PMC150C:
https://github.com/kaweksl/pdk-codebucket
EDIT: Those peephole rules look really useful. I wasn't even aware you could do that with SDCC. Maybe I'll be able to stop writing inline assembly now! I wonder what it would take to get SDCC to perform these optimizations by default?
volatile unsigned char c;
void f(void)
{
c |= 0x04;
}
What kind of i2c speed are you able to achieve?
The peephole rules from https://github.com/kaweksl/pdk-codebucket/blob/master/peephole_rules/peephole_pdk14.def will "optimize" that into a use of set1. However, the address of c is not known until later at link time. The linker might decide to place c in the upper half of the address space, while set1 only works on the lower half of the address space.
There would be ways to make better use of set1 in SDCC, but it's a bit more complex (involves changes in register allocation, code generation and fixing https://sourceforge.net/p/sdcc/bugs/3075/ (https://sourceforge.net/p/sdcc/bugs/3075/)); I hope to have something working for I/O by the end of the week.
There would be ways to make better use of set1 in SDCC, but it's a bit more complex (involves changes in register allocation, code generation and fixing https://sourceforge.net/p/sdcc/bugs/3075/ (https://sourceforge.net/p/sdcc/bugs/3075/)); I hope to have something working for I/O by the end of the week.
OT: what program was used for creating this type of image?
(https://free-pdk.github.io/images/PFS154_S14.png)
Bit / reset instructions are working for I/O in SDCC 4.0.2 #11707 now.Oh, that's interesting. :-+ Does this mean that we can use __bit now (or even bitfields), or just that SDCC will choose to generate more set0/set1 instructions for more case?
What kind of i2c speed are you able to achieve?
100kHz only, at 400kHz interrupt fires to late, maybe it could be achieved with constant pulling. Some day i will try make 400kHz address sampling and for rest I would use clock stretching.
spth,
I noticed when I was trying to optimize some of the code examples (specifically the adctest.c example) that certain functions that I am used to using with SDCC didn't seem to be available.
For one, I couldn't find a way to get _ultoa or _utoa to actually work. I did get _uitoa to work for up to 16-bit unsigned ints, but couldn't get the 32-bit or 8-bit optimized versions working. And, none of the smaller sized printf functions seemed to be there either (i.e. printf_tiny, printf_small, printf_fast, etc).
It seems like you are the resident SDCC expert (are you one of the developers?) Do you know if these are known issues where the library code just hasn't been ported yet, or am I doing something wrong? Is there a list of supported library functions somewhere for these pdk devices?
For the "pdkuino.h" does it means that we can program pdk like an Arduino, or even make an Arduino core based on it?
#define PIN_LED PA,4
...
setPinOutput(PIN_LED);
setPinHigh(PIN_LED);
PAC &= ~(1<<4)
PA |= (1<<4)
Bit / reset instructions are working for I/O in SDCC 4.0.2 #11707 now.Oh, that's interesting. :-+ Does this mean that we can use __bit now (or even bitfields), or just that SDCC will choose to generate more set0/set1 instructions for more case?
__sfr __at(0x17) SFR;
void f(void)
{
SFR |= 0x40; // Will use set1
SFR &= 0x7f; // Will use set0
SFR ^= 0x13; // Will use xor IO, a on pdk15
}
spth is the main developer of the PDK support in SDCC.
The printf from the standard includes results in code that is too big to fit into of the Padauk MCUs.
I implemented some size optimized printf-like functions fore debugging here:
https://github.com/cpldcpu/SimPad/blob/master/Toolchain/library/PDK_softuart.c
This was with the aim of having a minimal memory overhead for debugging.
One could probably implement a size optimized printf as well. But that needs to tie-in to standard libraries, that have not been set up yet. Your effort should be a good basis to finally tackle this as well.
It just means that SDCC will generate more set0 / set1.
~~~~
\_\_sfr \_\_at(0x17) SFR;
void f(void)
{
SFR |= 0x40; // Will use set1
SFR &= 0x7f; // Will use set0
SFR ^= 0x13; // Will use xor IO, a on pdk15
}
~~~~
__bit would be for variables in data memory, but isn't implemented yet (__sbit would be the equivalent for I/O, not yet implemented either). Also bit-fields still only work for normal objects (as covered by the C standard), not for __sfr I/O i.e. an SDCC extension).
For the "pdkuino.h" does it means that we can program pdk like an Arduino, or even make an Arduino core based on it?
Well, we are pretty far away from that right now.
The biggest obstacle is that Arduino technically uses a C++ compiler, but SDCC is only a C compiler. These PDK devices weren't even really designed with C in mind, let alone C++. It is unlikely there will ever be a C++ compiler, or that it would be worth using if there was one.
[…]
There is also a possibility to integrate the toolchain into the Arduino IDE (although, IMO there are much better IDEs out there). I ran across this the other day, which accomplishes an SDCC toolchain available to import into the Arduino IDE: https://github.com/DeqingSun/ch55xduino (https://github.com/DeqingSun/ch55xduino)
There is still a lot of work to make the software libraries and example programs as clean and easy to use as Arduino provides, but hopefully we can at least start to bridge that gap.
The biggest obstacle is that Arduino technically uses a C++ compiler, but SDCC is only a C compiler. These PDK devices weren't even really designed with C in mind, let alone C++. It is unlikely there will ever be a C++ compiler, or that it would be worth using if there was one.For those who really want C++ on Padauk: There is the LLVM+SDCC toolchain (http://www.colecovision.eu/llvm+sdcc/ (http://www.colecovision.eu/llvm+sdcc/)), but that is experimental stuff that needs more work, and I haven't worked on it since late 2016. AFAIR, back then, I got it to work good enough to put Dhrystone through it, and get it to work on STM8.
There is also a possibility to integrate the toolchain into the Arduino IDE (although, IMO there are much better IDEs out there). I ran across this the other day, which accomplishes an SDCC toolchain available to import into the Arduino IDE: https://github.com/DeqingSun/ch55xduino (https://github.com/DeqingSun/ch55xduino)You might also want to have a look at the sduino project, which created an arduion-like using STM8 with SDCC as compiler.
The biggest obstacle is that Arduino technically uses a C++ compiler, but SDCC is only a C compiler. These PDK devices weren't even really designed with C in mind, let alone C++. It is unlikely there will ever be a C++ compiler, or that it would be worth using if there was one.For those who really want C++ on Padauk: There is the LLVM+SDCC toolchain (http://www.colecovision.eu/llvm+sdcc/ (http://www.colecovision.eu/llvm+sdcc/)), but that is experimental stuff that needs more work, and I haven't worked on it since late 2016. AFAIR, back then, I got it to work good enough to put Dhrystone through it, and get it to work on STM8.
Oh interesting. But, I would imagine with the limited RAM and CODE sizes we are dealing with on these Padauk MCUs, that is asking for trouble, right?
spth,
I noticed when I was trying to optimize some of the code examples (specifically the adctest.c example) that certain functions that I am used to using with SDCC didn't seem to be available.
For one, I couldn't find a way to get _ultoa or _utoa to actually work. I did get _uitoa to work for up to 16-bit unsigned ints, but couldn't get the 32-bit or 8-bit optimized versions working. And, none of the smaller sized printf functions seemed to be there either (i.e. printf_tiny, printf_small, printf_fast, etc).
It seems like you are the resident SDCC expert (are you one of the developers?) Do you know if these are known issues where the library code just hasn't been ported yet, or am I doing something wrong? Is there a list of supported library functions somewhere for these pdk devices?
A few parts are pretty challenging for beginners, for example the calibration..., it took me almost a whole day to figure out how the hello world program works. :phew:
This was the most diifficult hello world code I've ever seen :)Code: [Select]ihrcr = *((const unsigned char*)(0x87ed));
// took me hours to find where from the 0x8000 comes
https://github.com/free-pdk/sdcc-pdk-code-examples/blob/master/hello-s16/hello.c
Work is underway to try and standardize include files and example programs: (e.g. https://github.com/free-pdk/easy-pdk-programmer-software/pull/33)
All functions from the C standard that are in SDCC headers should just work.
_ultoa, etc are SDCC-specific extensions that just haven't been ported yet (the situation with these needs to first be improved anyway - they are not tested in regression tests, and they have bad names - as compiler-specific extensions hteir names should start with two underscores to not conflict with functions written by the user).
P.S.: I just opened a ticket for these functions: https://sourceforge.net/p/sdcc/bugs/3077/
mov a, p
mov p, a
idxm p, a
ceqsn a, p
etc...
I quickly realized that I was badly missing an easy overview of the available pins and their functions (the overview in the datasheet is not that nice to look at).
Therefore I made a simple tool to generate pinout diagrams. For now, I added diagrams for all PFS173 packages.
The source code is at GitHub; adding diagrams for the other Padauk mikrocontrollers shouldn't be hard, if desired: https://github.com/cmfcmf/ic-pinout-diagram-generator/blob/96578800d1e2ad50d6beccc5705d3ac240b117b6/src/App.js#L5-L226 (https://github.com/cmfcmf/ic-pinout-diagram-generator/blob/96578800d1e2ad50d6beccc5705d3ac240b117b6/src/App.js#L5-L226)
The main issue right now is that the diagrams are super wide and look bad on smaller screens.
Let me know what you think!
https://christianflach.de/ic-pinout-diagram-generator (https://christianflach.de/ic-pinout-diagram-generator)
The source code is at GitHub; adding diagrams for the other Padauk mikrocontrollers shouldn't be hard, if desired: https://github.com/cmfcmf/ic-pinout-diagram-generator/blob/96578800d1e2ad50d6beccc5705d3ac240b117b6/src/App.js#L5-L226 (https://github.com/cmfcmf/ic-pinout-diagram-generator/blob/96578800d1e2ad50d6beccc5705d3ac240b117b6/src/App.js#L5-L226)
All functions from the C standard that are in SDCC headers should just work.
_ultoa, etc are SDCC-specific extensions that just haven't been ported yet (the situation with these needs to first be improved anyway - they are not tested in regression tests, and they have bad names - as compiler-specific extensions hteir names should start with two underscores to not conflict with functions written by the user).
P.S.: I just opened a ticket for these functions: https://sourceforge.net/p/sdcc/bugs/3077/
Thanks spth!
An additional question...
When looking at the generated .asm files, I am seeing code like:Code: [Select]mov a, p
mov p, a
idxm p, a
ceqsn a, p
etc...
But, I don't see any reference to a register named 'p' in the datasheets or .INC files. Do you know if this is just a memory address that SDCC reserves for its own use, or an undocumented register, or something else?
//Assuming variables are place in presented order
uint16_t t16counter; // ldt16 will work
uint8_t somevar;
uint16_t sect16count; //ldt16 will fail, not aligned
uint8_t secsome;
uint16_t tht16count; //ldt16 will work
One thought... Since you are color-coding the blocks, you don't necessarily need to keep them in aligned columns. That would reduce the width a bit.
It would be great to have these published to https://free-pdk.github.io/ (https://github.com/free-pdk/free-pdk.github.io). If would be nice to have a page per IC with pinout diagrams and other useful information.
Hi cmfcmf,
Very nice. Is it possible to generalise it for other MCUs, maybe take the input data from a file, and an easier way to edit? A generator-generator?
One thought... Since you are color-coding the blocks, you don't necessarily need to keep them in aligned columns. That would reduce the width a bit.
It would be great to have these published to https://free-pdk.github.io/ (https://github.com/free-pdk/free-pdk.github.io). If would be nice to have a page per IC with pinout diagrams and other useful information.
I have added an option to adjust the font size and toggle between "aligned" and "dense" mode as well as download buttons.
I agree that the diagrams should be on https://free-pdk.github.io/. I think it would make a lot of sense to use GitHub's Jekyll integration to generate the documentation pages from Markdown instead of writing plain HTML.
I'll see if I can get something nice to work.
When looking at the generated .asm files, I am seeing code like:Code: [Select]mov a, p
mov p, a
idxm p, a
ceqsn a, p
etc...
But, I don't see any reference to a register named 'p' in the datasheets or .INC files. Do you know if this is just a memory address that SDCC reserves for its own use, or an undocumented register, or something else?
p is a "pseudo-register", i.e. a memory location handled by the compiler as if it was a register. It is physically located at address 0 (which means we know it is aligned, and in the lower half of the address space, so all instructions work on this location).
P.S.: In retrospective, I think more pseudo-registers should be used. But this is a trade-off: More pseudo-registers allow SDCC to generate better code, but they also need to be saved at interrupts, increasing interrupt latency. Still, I now think the sweet spot is at 3 consecutive bytes of pseudo.registers, starting at address 0 (that way, one could have p0, p1, p2. p0 together with p1 would be used for access to the 16-bit timer and for ldtabl. Having both p0 and p2 would allow more efficient copies between two stack locations). But changing the number of pseudo-registers is a long-term thing, and also needs to be coordinated with future pdk16 support.
Is it safe to assume that 'p' can be modified in an inline assembly method without worrying about saving/restoring? i.e. does the caller already save/restore 'p' if it uses it, or should the callee do the save/restore?
One thought... Since you are color-coding the blocks, you don't necessarily need to keep them in aligned columns. That would reduce the width a bit.
It would be great to have these published to https://free-pdk.github.io/ (https://github.com/free-pdk/free-pdk.github.io). If would be nice to have a page per IC with pinout diagrams and other useful information.
I have added an option to adjust the font size and toggle between "aligned" and "dense" mode as well as download buttons.
I agree that the diagrams should be on https://free-pdk.github.io/. I think it would make a lot of sense to use GitHub's Jekyll integration to generate the documentation pages from Markdown instead of writing plain HTML.
I'll see if I can get something nice to work.
Jekyll would be great. We could then also use that space for instruction/tutorials.
One thought... Since you are color-coding the blocks, you don't necessarily need to keep them in aligned columns. That would reduce the width a bit.
It would be great to have these published to https://free-pdk.github.io/ (https://github.com/free-pdk/free-pdk.github.io). If would be nice to have a page per IC with pinout diagrams and other useful information.
I have added an option to adjust the font size and toggle between "aligned" and "dense" mode as well as download buttons.
I agree that the diagrams should be on https://free-pdk.github.io/. I think it would make a lot of sense to use GitHub's Jekyll integration to generate the documentation pages from Markdown instead of writing plain HTML.
I'll see if I can get something nice to work.
Jekyll would be great. We could then also use that space for instruction/tutorials.
I have created a PR [1] that introduces a new design for https://free-pdk.github.io/ and also integrates the pinout diagrams as well as an overview of the many different free-pdk repositories. There is a lot of room for further improvements, but this should get the ball rolling when it comes to tutorials and more detailed instructions. Adding pages is as easy as adding new markdown files (no more HTML :)).
I have not yet added any information on the SDCC examples and headers, since that is an ongoing discussion.
[1] https://github.com/free-pdk/free-pdk.github.io/pull/3
I have created a PR [1] that introduces a new design for https://free-pdk.github.io/ and also integrates the pinout diagrams as well as an overview of the many different free-pdk repositories. There is a lot of room for further improvements, but this should get the ball rolling when it comes to tutorials and more detailed instructions. Adding pages is as easy as adding new markdown files (no more HTML :)).
I have not yet added any information on the SDCC examples and headers, since that is an ongoing discussion.
[1] https://github.com/free-pdk/free-pdk.github.io/pull/3
I have created a PR [1] that introduces a new design for https://free-pdk.github.io/ and also integrates the pinout diagrams as well as an overview of the many different free-pdk repositories. There is a lot of room for further improvements, but this should get the ball rolling when it comes to tutorials and more detailed instructions. Adding pages is as easy as adding new markdown files (no more HTML :)).
I have not yet added any information on the SDCC examples and headers, since that is an ongoing discussion.
[1] https://github.com/free-pdk/free-pdk.github.io/pull/3
https://free-pdk.github.io/
It's live now, thanks a lot!
Now it's much easier to contribute some much needed documentation. Everyone, feel free to contribute. You can directly submit pull-requests here: https://github.com/free-pdk/free-pdk.github.io/tree/development
I will add a section about ordering the lite-programmer once I received and validated the r1 samples - they are being made right now.
I have created a PR [1] that introduces a new design for https://free-pdk.github.io/ and also integrates the pinout diagrams as well as an overview of the many different free-pdk repositories. There is a lot of room for further improvements, but this should get the ball rolling when it comes to tutorials and more detailed instructions. Adding pages is as easy as adding new markdown files (no more HTML :)).
I have not yet added any information on the SDCC examples and headers, since that is an ongoing discussion.
[1] https://github.com/free-pdk/free-pdk.github.io/pull/3
https://free-pdk.github.io/
It's live now, thanks a lot!
Now it's much easier to contribute some much needed documentation. Everyone, feel free to contribute. You can directly submit pull-requests here: https://github.com/free-pdk/free-pdk.github.io/tree/development
I will add a section about ordering the lite-programmer once I received and validated the r1 samples - they are being made right now.
Excellent! Nice work!
A few things I noticed while playing around with the pinout diagrams:
- It would be nice if the diagrams were centered on the page.
- Maybe provide a quick way to check/uncheck all.
- For the 'Programming Pins', instead of RESET, maybe use ICVPP like it is labeled on the programmer schematic. And maybe add an associated ICVDD on the VDD pin to help clarify that it is directly manipulated during programming.
- PR submitted: https://github.com/cmfcmf/ic-pinout-diagram-generator/pull/3
- I can help explain the datasheet for current sink/drive if needed. What actual questions do you have?
- PR submitted: https://github.com/cmfcmf/ic-pinout-diagram-generator/pull/4
I also just submitted PRs for:
- Slightly better consistency with descriptions - https://github.com/cmfcmf/ic-pinout-diagram-generator/pull/5
- Add support for PMS152 - https://github.com/cmfcmf/ic-pinout-diagram-generator/pull/6
- Add support for PMS150C/PMS15A - https://github.com/cmfcmf/ic-pinout-diagram-generator/pull/7
PFS154 | PFS173 |
"negative drive current", e.g. -5mA | "positive drive current, e.g. 5mA |
"low" vs. "normal" current | "normal" vs. "strong" current |
My confusion with the drive/sink currents in the PFS154 datasheet arose from the fact that it listed the drive/sink currents differently than the PFS173 datasheet:
PFS154 PFS173 "negative drive current", e.g. -5mA "positive drive current, e.g. 5mA "low" vs. "normal" current "normal" vs. "strong" current
But, looking at your PR, I gathered that both seem to mean the same thing.
Centering the diagrams is on my TODO list, however it currently breaks the image download buttons.
When will the Mini-pill programmer available? It'll be fun to build one because it's such an impressive design!
Since all of these padauk micros are surface mounted, I learned quite a lot of surface mounting soldering during the last two months. :-+
Just don't do what I did on the first one. After carefully tacking down the first corner and repositioning the board so I could tack down the second corner, my OCD got the better of me and without thinking about it, I put my finger on the STM32 to 'clean' off the flux residue. Let's just say, the pins were never straight again. |O I still might be able to fix it, but it was easier/quicker to just grab a spare pcb/ic and try again, this time even more carefullly.
In this description there is a mistake at STT16 M | LDT16 M | IDXM M,A | IDXM A,M instructions:
https://free-pdk.github.io/PADAUK_FPPA_14_bit_instruction_set.html (https://free-pdk.github.io/PADAUK_FPPA_14_bit_instruction_set.html)
000011c<7-bit MEM addr>c // 7+7+1=15 bit, but this is only 14 bit device
Thanks for sharing JS 8) :-+
Both of these projects make me wonder how easy it would be to combine them with an inexpensive NOR flash IC (i.e. W25Q80 or similar) to greatly increase the quantity/duration of the sounds/patterns and allow them to be changed even without having to re-compile.
already completed a project with external SPI flash - a good quality audio player (plays 8 bit @32kHz).A video Demo of some sort would be very nice 8) ;)
I created a PCB which holds an 8 pin PADAUK (e.g. PMS150C/PFS154/PFS173) and added a 16MBit SPI flash and a small class D amplifier.
I use it inside of my hackintosh to play the startup chime immediately after a power cycle. 8)
Thanks.
Another confusing instructions are T0SN M.n | T1SN M.n | SET0 M.n | SET1 M.n. The table shows 6-bit MEM addr, but for M address you need 7 bit address to be able to address the whole memory. (128bytes PFS154) For IO space needs 6 bit because it is only 64bytes.
I wrote a pure assembler, finished now, testing is in progress. That's why I need to know how every instruction works.
A video Demo of some sort would be very nice 8) ;)What kind of video demo? A video from my hackintosh (intel NUC) starting up?
.rom
wdreset
set0 clkmd.1
set1 pac.0
mov a,#01h
label1:
xor pa,a
nop
nop
...
97 nops total
goto label1
I experiance so many strange things around this MCU :D
I run my PFS154 on ILRC but according to my calculation it runs approx. at 143kHz. I wrote a loop with 97nop + 1 goto + 1 xor (to invert led), that's 100 instruction, the execution of the 100 instruction takes 700us, so to execute 1 instruction takes 7us. I don't find any explanation for this. According to the datasheet it should run at 55kHz. I know ILRC is not accurate but I did not expect 143kHz.
.rom
wdreset
mov a,#ffh
mov pbc,a
mov a,clkmd
mov pb,a
label1:
wdreset
nop
nop
nop
goto label1
I wrote a very simple code again, after reset I put the clkmd register value to port B.Code: [Select].rom
wdreset
mov a,#ffh
mov pbc,a
mov a,clkmd
mov pb,a
label1:
wdreset
nop
nop
nop
goto label1
According to PFS154 datasheet clkmd value after reset should be: 0xF6
I read 0x9E
This means clock select type is 1, and clock mode is IHRC/64 = so 16MHz / 64 = 250kHz
If one instruction is executed in 2 cycles, and I did not calibrated the IHRC, that could answer the question why my PFS154 running at 143kHz
It's very annoying if we can not trust in the data sheet.
Also anyone know how PADAUK see that whole open-source toolchain ? They gonna try support/kill it or maybe do nothing about it ?
What kind of video demo? A video from my hackintosh (intel NUC) starting up?That would be nice, also other cool projects that you do, like the polysound demo >:D
Also anyone know how PADAUK see that whole open-source toolchain ? They gonna try support/kill it or maybe do nothing about it ?
./easypdkprog -v probe
Searching programmer... found: /dev/ttyACM3
FREE-PDK EASY PROG - Hardware:1.2 Firmware:1.2 Protocol:1.2
Probing IC... found.
TYPE:FLASH RSP:0xAA1 VPP=4.50 VDD=2.00
IC is supported: PFS154 ICID:0xAA1
/Bingo
But I did not find info how security (MTP code protection), boot-up time, drive (IO low/normal driving) works, so the rest of Code Options chapter is unclear for me.
misc.5 controls the wake-up time but I am not sure it is the same thing what mentioned in Code Options chapter.
Just made one of Tim's lite programmers.
My first STM32 SMD soldering job, have only tried AVR SMD before :phew:
Tim sent me two , and i totally screwed up the first one ... Tacked down 2 sides but began drag soldering on the tacked side |O
MCU badly misaligned , and when trying to correct i badly bent 4 pins.
Well the 2'nd went ok i think , i can DFU program it w. the programer sw.
Now off to solder a PADA to a SMD-DIP board.
Just made one of Tim's lite programmers.
My first STM32 SMD soldering job, have only tried AVR SMD before :phew:
Tim sent me two , and i totally screwed up the first one ... Tacked down 2 sides but began drag soldering on the tacked side |O
MCU badly misaligned , and when trying to correct i badly bent 4 pins.
Well the 2'nd went ok i think , i can DFU program it w. the programer sw.
Now off to solder a PADA to a SMD-DIP board.
Buy yourself good flux (paste/gel), it's unbelievable what difference it can make, it's magic. I build 2 original programmers and i was struggling with first one, for 2nd i used better flux and it was smooth, soldered tqfp48 without using copper wick , joints nicely shine. Now i have programmer for stable and dev easy-pdk branch.
But I did not find info how security (MTP code protection), boot-up time, drive (IO low/normal driving) works, so the rest of Code Options chapter is unclear for me.
misc.5 controls the wake-up time but I am not sure it is the same thing what mentioned in Code Options chapter.
Assumption (DS) IHRC = 16MHz
SysClock = IHRC/16
Timer16 irq (bit8) - every 512 cycles
ticks every 16000000/512 = 31250 clock cycles should be ~32uS
I'm toggling PB3 in the timer ISR , just to be able to put a scope on
Scope - PB3 toggle
Tick IHRC = 58,4uS
Tick sysclock = 888uS
483 ; main.c: 64: AUTO_INIT_SYSCLOCK();
484 ; genAssign
00010A 1C 2F 485 mov a, #0x1c
00010C 83 01 486 mov __clkmd, a
000000 232 _millis_setup:
233 ; ../include/millis.h: 29: T16M = (uint8_t)(T16M_CLK_IHRC | T16M_CLK_DIV1 | T16M_INTSRC_8BIT);
234 ; genAssign
000000 80 2F 235 mov a, #0x80
000002 86 01 236 mov __t16m, a
478 ; -----------------------------------------
479 ; function _sdcc_external_startup
480 ; -----------------------------------------
481 ; Register assignment is optimal.
00010A 482 __sdcc_external_startup:
483 ; main.c: 65: AUTO_INIT_SYSCLOCK();
484 ; genAssign
00010A 1C 2F 485 mov a, #0x1c
00010C 83 01 486 mov __clkmd, a
487 ; main.c: 70: AUTO_CALIBRATE_SYSCLOCK(TARGET_VDD_MV);
488 ; genInline
00010E 52 2C 489 and a, #'R'
000110 43 2C 490 and a, #'C'
000112 01 2C 491 and a, #(1)
000114 40 2C 492 and a, #((1000000))
000116 42 2C 493 and a, #((1000000)>>8)
000118 0F 2C 494 and a, #((1000000)>>16)
00011A 00 2C 495 and a, #((1000000)>>24)
00011C A0 2C 496 and a, #((4000))
00011E 0F 2C 497 and a, #((4000)>>8)
000120 0B 2C 498 and a, #(0x0b)
499 ; main.c: 82: return 0; // Return 0 to inform SDCC to continue with normal initialization.
500 ; genReturn
501 ; genLabel
502 ; peephole j0 removed unused label 00101$.
503 ; main.c: 83: }
504 ; genEndFunction
000122 00 02 505 ret #0x00
What does this
487 ; main.c: 70: AUTO_CALIBRATE_SYSCLOCK(TARGET_VDD_MV);
And forward do ??
(...)
It does a lot of magic w. accumulator a , but never saves it anywhere - It just does that stuff , and then returns 0x00 in a.
easypdkprog -V
easypdkprog 1.2
$ dfu-util -d 0483:df11 -a "@Internal Flash /0x08000000/064*0002Kg" --dfuse-address 0x08000000 -D EASYPDKPROG.bin
$ dfu-util -d 0483:df11 -a "@Internal Flash /0x08000000/064*0002Kg" --dfuse-address 0x08000000 -D EASYPDKPROG.dfu
dfu-util 0.9
Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2016 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
Opening DFU capable USB device...
ID 0483:df11
Run-time device DFU version 011a
Claiming USB DFU Interface...
Setting Alternate Setting #0 ...
Determining device status: state = dfuERROR, status = 10
dfuERROR, clearing status
Determining device status: state = dfuIDLE, status = 0
dfuIDLE, continuing
DFU mode device DFU version 011a
Device returned transfer size 2048
DfuSe interface name: "Internal Flash "
Downloading to address = 0x08000000, size = 29068
Download [=========================] 100% 29068 bytes
Download done.
File downloaded successfully
The data sheet is also right... Usually PADAUK initializes the default values inside of the startup code they insert when you use the PADAUK IDE.
Since you use your own assembler / compiler you have to re-create the startup code and initializations.
BTW: PADAUK startup code wastes up to 10% of the valuable code memory.
Anyway, a good practice is to always set the complete value yourself.
JS
which programmer version you use ? (firmware and software)What does this
487 ; main.c: 70: AUTO_CALIBRATE_SYSCLOCK(TARGET_VDD_MV);
And forward do ??
(...)
It does a lot of magic w. accumulator a , but never saves it anywhere - It just does that stuff , and then returns 0x00 in a.
It is placeholder for programmer. Before flashing, it search for that code, reads desired MHz, and voltage, and replace that code with calibration routine. After flashing programmer use that routine to calibrate clock (by measuring pin change frequency, and switching pin), after that, calibration value is written and most of calibration routine is overwritten with nop (with OTP you can clear bit but can't set bit)
I'll give the DFU version a go
It's this one correct ?
https://github.com/free-pdk/easy-pdk-programmer-software/tree/development/Firmware (https://github.com/free-pdk/easy-pdk-programmer-software/tree/development/Firmware)
git clone https://github.com/free-pdk/easy-pdk-programmer-software.git (https://github.com/free-pdk/easy-pdk-programmer-software.git)
...
Did program the programmer w. the dfuCode: [Select]$ dfu-util -d 0483:df11 -a "@Internal Flash /0x08000000/064*0002Kg" --dfuse-address 0x08000000 -D EASYPDKPROG.dfu
dfu-util 0.9
Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2016 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
Opening DFU capable USB device...
ID 0483:df11
Run-time device DFU version 011a
Claiming USB DFU Interface...
Setting Alternate Setting #0 ...
Determining device status: state = dfuERROR, status = 10
dfuERROR, clearing status
Determining device status: state = dfuIDLE, status = 0
dfuIDLE, continuing
DFU mode device DFU version 011a
Device returned transfer size 2048
DfuSe interface name: "Internal Flash "
Downloading to address = 0x08000000, size = 29068
Download [=========================] 100% 29068 bytes
Download done.
File downloaded successfully
Still getting 2 sec between blinks.
...
I have just resoldered the SPI side of the Programmer MCU , all looks ok.
Still 2 Sec intervals
easypdkprog -n PFS154 write .output/BlinkLED_WithIRQ_PFS154.ihx
Erasing IC... done.
Writing IC (170 words)... done.
Calibrating IC
* IHRC SYSCLK=1000000Hz @ 4.00V ... calibration result: 997283Hz (0x84) done.
bingo600, it definitely sounds like you are not getting a successful calibration, and that is most likely why the timing is off.
As kaweksl has already indicated, this is most likely because the free-pdk-examples currently require the 'development' branch of the easy-pdk-programmer-software for successful calibration. The calibration routines were changed compared to the previously released version (i.e. master).
You seem to have found the correct development branch, but it is unclear if you have actually re-complied the firmware and software. Both are needed. You can't just use the .dfu firmware from the development branch, as it hasn't been updated yet. And, the easypdkprog software needs to be re-compiled as well. You can't just use the previous 1.2 release.
When using the re-compiled .dfu firmware and the re-compiled easypdkprog you should get output like this (after running make program):Code: [Select]easypdkprog -n PFS154 write .output/BlinkLED_WithIRQ_PFS154.ihx
Erasing IC... done.
Writing IC (170 words)... done.
Calibrating IC
* IHRC SYSCLK=1000000Hz @ 4.00V ... calibration result: 997283Hz (0x84) done.
If you are not seeing those last two lines, something is off, and the IC is not properly calibrated.
If it still isn't working after making sure you are using re-compiled firmware and software, can you post the results of running make program so we can troubleshoot further?
git pull
remote: Enumerating objects: 5, done.
remote: Counting objects: 100% (5/5), done.
remote: Compressing objects: 100% (3/3), done.
remote: Total 5 (delta 2), reused 5 (delta 2), pack-reused 0
Unpacking objects: 100% (5/5), done.
From https://github.com/free-pdk/easy-pdk-programmer-software
3a557cc..78983e5 master -> origin/master
be5ea01..78983e5 development -> origin/development
* [new tag] 1.3 -> 1.3
Updating 3a557cc..78983e5
Checking out files: 100% (153/153), done.
arm-none-eabi-size build/EASYPDKPROG.elf
text data bss dec hex filename
33176 488 13088 46752 b6a0 build/EASYPDKPROG.elf
arm-none-eabi-objcopy -O binary -S build/EASYPDKPROG.elf build/EASYPDKPROG.bin
cp build/EASYPDKPROG.bin build/EASYPDKPROG.dfu
dfu-suffix -v 0483 -p df11 -a build/EASYPDKPROG.dfu
dfu-suffix (dfu-util) 0.9
Copyright 2011-2012 Stefan Schmidt, 2013-2014 Tormod Volden
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
Suffix successfully added to file
$ dfu-util -d 0483:df11 -a "@Internal Flash /0x08000000/064*0002Kg" --dfuse-address 0x08000000 -D EASYPDKPROG.dfudfu-util -d 0483:df11 -a "@Internal Flash /0x08000000/064*0002Kg" --dfuse-address 0x08000000 -D EASYPDKPROG.dfu
dfu-util 0.9
Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2016 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
Opening DFU capable USB device...
ID 0483:df11
Run-time device DFU version 011a
Claiming USB DFU Interface...
Setting Alternate Setting #0 ...
Determining device status: state = dfuERROR, status = 10
dfuERROR, clearing status
Determining device status: state = dfuIDLE, status = 0
dfuIDLE, continuing
DFU mode device DFU version 011a
Device returned transfer size 2048
DfuSe interface name: "Internal Flash "
Downloading to address = 0x08000000, size = 33664
Download [=========================] 100% 33664 bytes
Download done.
File downloaded successfully
$ make clean program
rm -r -f .build .output
sdcc -mpdk14 -c --std-sdcc11 --fverbose-asm --opt-code-size -DPFS154 -DF_CPU=1000000 -DTARGET_VDD_MV=4000 -I. -I../include -o .build/main.rel main.c
sdar -rc .build/lib.lib
sdcc -mpdk14 --out-fmt-ihx -o .output/BlinkLED_WithIRQ_PFS154.ihx .build/main.rel .build/lib.lib
makebin -p .output/BlinkLED_WithIRQ_PFS154.ihx .output/BlinkLED_WithIRQ_PFS154.bin
---------- Segments ----------
. .ABS. 00000000 00000000 = 0. bytes (ABS,CON)
. .ABS. 00000000 00000000 = 0. bytes (ABS,CON)
HEADER1 00000000 00000002 = 2. bytes (ABS,CON)
HEADER3 00000000 00000010 = 16. bytes (ABS,CON)
PREG2 00000000 00000002 = 2. bytes (ABS,CON)
RSEG0 00000000 00000002 = 2. bytes (ABS,CON)
DATA 00000002 00000015 = 21. bytes (REL,CON)
HOME 00000022 00000002 = 2. bytes (REL,CON)
GSINIT 00000024 00000014 = 20. bytes (REL,CON)
GSFINAL 00000038 00000002 = 2. bytes (REL,CON)
CODE 0000003A 00000124 = 292. bytes (REL,CON)
SSEG FFFFFFFF 00000001 = 1. bytes (REL,CON)
------------------------------
Size of BlinkLED_WithIRQ_PFS154.bin: 350 bytes
easypdkprog -n PFS154 write .output/BlinkLED_WithIRQ_PFS154.ihx
Erasing IC... done.
Writing IC (175 words)... done.
Calibrating IC
* IHRC SYSCLK=1000000Hz @ 4.00V ... calibration result: 997066Hz (0x84) done.
$ easypdkprog -V
easypdkprog 1.2
Did a new Pull
Seems like Devel & Master has been "alligned"
I'm not a GIT Guru - is the below url correct for a "Git clone" , or should i have used some kind of tag to get devel ??
This devel
https://github.com/free-pdk/easy-pdk-programmer-software/tree/development
Has this as git chekout (no devel in the name)
https://github.com/free-pdk/easy-pdk-programmer-software.git
And Yipieee ..... Calibrating ;D ;D ;DCode: [Select]$ make clean program
rm -r -f .build .output
sdcc -mpdk14 -c --std-sdcc11 --fverbose-asm --opt-code-size -DPFS154 -DF_CPU=1000000 -DTARGET_VDD_MV=4000 -I. -I../include -o .build/main.rel main.c
sdar -rc .build/lib.lib
sdcc -mpdk14 --out-fmt-ihx -o .output/BlinkLED_WithIRQ_PFS154.ihx .build/main.rel .build/lib.lib
makebin -p .output/BlinkLED_WithIRQ_PFS154.ihx .output/BlinkLED_WithIRQ_PFS154.bin
---------- Segments ----------
. .ABS. 00000000 00000000 = 0. bytes (ABS,CON)
. .ABS. 00000000 00000000 = 0. bytes (ABS,CON)
HEADER1 00000000 00000002 = 2. bytes (ABS,CON)
HEADER3 00000000 00000010 = 16. bytes (ABS,CON)
PREG2 00000000 00000002 = 2. bytes (ABS,CON)
RSEG0 00000000 00000002 = 2. bytes (ABS,CON)
DATA 00000002 00000015 = 21. bytes (REL,CON)
HOME 00000022 00000002 = 2. bytes (REL,CON)
GSINIT 00000024 00000014 = 20. bytes (REL,CON)
GSFINAL 00000038 00000002 = 2. bytes (REL,CON)
CODE 0000003A 00000124 = 292. bytes (REL,CON)
SSEG FFFFFFFF 00000001 = 1. bytes (REL,CON)
------------------------------
Size of BlinkLED_WithIRQ_PFS154.bin: 350 bytes
easypdkprog -n PFS154 write .output/BlinkLED_WithIRQ_PFS154.ihx
Erasing IC... done.
Writing IC (175 words)... done.
Calibrating IC
* IHRC SYSCLK=1000000Hz @ 4.00V ... calibration result: 997066Hz (0x84) done.
First time i ever saw Calibrating , when programming.
I have no idea what i did wrong , besides not specifying some magic git command on checkout.
And prob. being saved by master now updated to development.
But what did i do wrong ???
Edit: easypdkprog still shows 1.2Code: [Select]$ easypdkprog -V
easypdkprog 1.2
./easypdkprog -v
gives pc side software version./easypdkprog --verbose probe
givesSearching programmer... found: /dev/ttyACM0
FREE-PDK EASY PROG - Hardware:1.2 Firmware:1.3 Protocol:1.3
Probing IC... Nothing found.
Edit: easypdkprog still shows 1.2Code: [Select]$ easypdkprog -V
easypdkprog 1.2
I'll have to check that out later. Possibly JS missed a release step?
Improvement for output of easypdkprog -V
easypdkprog 1.2
$ git rev-parse HEAD
78983e5aee2ab4bc16628405a0da99ca290f9af3
Or
$ git log -1
commit 78983e5aee2ab4bc16628405a0da99ca290f9af3 (HEAD -> master, tag: 1.3, origin/master, origin/development, origin/HEAD)
Could you in the makefile run a: git rev-parse HEAD , save it in a "GIT_VER"
Then insert a -DGIT_BUILD=$GIT_VER , and use that GIT_BUILD as a string in the -V output ?
That could come in handy , when noobs like me don't know how to checkout development via git ?
easypdkprog -V
easypdkprog 1.2 - Git: 78983e5aee2ab4bc16628405a0da99ca290f9af3
All of the above git commands supplied by "Google" , i'm still at git clone & git pull level.
SVN is my daily tool.
/Bingo
That sounds like a good suggestion. Why don't you open a feature request (i.e. issue) on GitHub?
$ git checkout development
$ git log -1
commit 78983e5aee2ab4bc16628405a0da99ca290f9af3 (HEAD -> development, tag: 1.3, origin/master, origin/development, origin/HEAD, master)
Author: freepdk <free-pdk@users.noreply.github.com>
Date: Mon Jul 13 11:18:15 2020 +0200
update firmware binary
$ easypdkprog -V
easypdkprog 1.3-3-gef65826
$ easypdkprog probe --verbose
Searching programmer... found: /dev/ttyACM3
FREE-PDK EASY PROG - Hardware:1.2 Firmware:1.3-3-gef65826 Protocol:1.3
Probing IC... found.
TYPE:FLASH RSP:0x1AA1 VPP=4.50 VDD=2.00
IC is supported: PFS154 ICID:0xAA1
You may download my assembler and I wrote a small tutorial for it.
http://www.endresz.eu/padauk/padauk.html (http://www.endresz.eu/padauk/padauk.html)
Hope you will find it usefull!
Would this patch work for addin git vers to the firmware ??
$ easypdkprog -V
easypdkprog 1.3-10-gc5fabd3
$ easypdkprog probe --verbose
Searching programmer... found: /dev/ttyACM3
FREE-PDK EASY PROG - HW:1.2 SW:1.3 PROTO:1.3 (1.3-10-gc5fabd3)
Probing IC... found.
TYPE:FLASH RSP:0x1AA1 VPP=4.50 VDD=2.00
IC is supported: PFS154 ICID:0xAA1
You may download my assembler and I wrote a small tutorial for it.
http://www.endresz.eu/padauk/padauk.html (http://www.endresz.eu/padauk/padauk.html)
Hope you will find it usefull!
Nice! You should post it on Github so it is added to the project list.
I have to ask though: Have you tried SDASPDKxx, the assembler that comes with SDCC?
You may download my assembler and I wrote a small tutorial for it.
http://www.endresz.eu/padauk/padauk.html (http://www.endresz.eu/padauk/padauk.html)
Hope you will find it usefull!
Nice! You should post it on Github so it is added to the project list.
I have to ask though: Have you tried SDASPDKxx, the assembler that comes with SDCC?
I only tried to write inline asm code in SDCC and I used the naked function keyword but still resulted a lot of extra asm code. I was unable to find any method to write code only in asm so I wrote my own assembler.
I'm working on the Github page.
I was unable to find any method to write code only in asm so I wrote my own assembler.
sdas Assembler V02.00 + NoICE + SDCC mods (Padauk 14)
Copyright (C) 2012 Alan R. Baldwin
This program comes with ABSOLUTELY NO WARRANTY.
Usage: [-Options] file
Usage: [-Options] outfile file1 [file2 file3 ...]
-d Decimal listing
-q Octal listing
-x Hex listing (default)
-g Undefined symbols made global
-a All user symbols made global
-b Display .define substitutions in listing
-bb and display without .define substitutions
-c Disable instruction cycle count in listing
-j Enable NoICE Debug Symbols
-y Enable SDCC Debug Symbols
-l Create list file/outfile[.lst]
-o Create object file/outfile[.rel]
-s Create symbol file/outfile[.sym]
-p Disable automatic listing pagination
-u Disable .list/.nlist processing
-w Wide listing format for symbol table
-z Disable case sensitivity for symbols
-f Flag relocatable references by ` in listing file
-ff Flag relocatable references by mode in listing file
-I Add the named directory to the include file
search path. This option may be used more than once.
Directories are searched in the order given.
Some home-made projects using pdk
Replacement for PFC8574, NanoPi Duo controlling 1602 LCD with i2c using python
(Attachment Link)
PMS150C-U06 as I2C relay controller , I can't find my SOT23 LDO's so had to glue sot223
(Attachment Link)
That LCD adapter is similar to a project I had in mind. But, why emulate the PCF8574 i2c extender when you could have a much more efficient/faster protocol that directly controls the LCD? If I remember correctly, the PCF8574 requires a lot of overhead, specifically to properly toggle the LCD's EN line.
I assume the source code is in your https://github.com/kaweksl/pdk-codebucket (https://github.com/kaweksl/pdk-codebucket) repo?Mostly same, needed to add some peephole rules since pdk13 has less instructions, also i switched from pin change interrupt to comparator interrupt, since pms150c-u6 don't have pin change interrupt, also added i2c address selection via external resistor value.
For me whole point of i2c is to save pins on master uc, reduce wires, speed has low priority. Also liquidcrystal_i2c library is not using PCF8574 sequential write (not sending address every byte) , which could speed up things.
Creating dedicated i2c bridge would make sense (for me) only if it would take "high level commands", like setCursor, backlight, printascii, and push it to lcd. But for that im not sure if we have enough idle time between transferring i2c bytes to do that on the fly, and we can't do parallel processing. So that would require to use:
I was just pointing out that if the goal is an i2c lcd adapter, there are faster / more efficient ways to drive an lcd over i2c than what the PCF8574 i2c expander allows (even with sequential write).
(...)
This is where the lite r1 programmers are stuck :( Looks like JLCPCBs Europaket is not such a good idea after all. I guess one of the packages they included created a customs issue...
Here's a fun little project I whipped up on a breadboard today: https://github.com/serisman/pdk-continuity-tester (https://github.com/serisman/pdk-continuity-tester)
It is a standalone continuity tester, that uses the Comparator to test for continuity, and has an aggressive battery saving mode (< 0.5 uA while sleeping).
That's a really neat project! Honestly, I would not have thought about using a MCU for this in the first place, so it is a good example for a use case of ultra-low-cost MCUs.
I wonder about the usage of the pin change for wakeup: This somehow implies that there is a trickle charge to pull the pin up while the MCU is asleep. So this is valid for both the Padauk MCUs and the ATtiny85?
Btw, one could probably reduce active power consumption by making everything interrupt driven. But I guess that is inconsequential.
QuoteBtw, one could probably reduce active power consumption by making everything interrupt driven. But I guess that is inconsequential.
Not sure how interrupts would actually help here. I suppose I could remove the idle counter if active power consumption really mattered (i.e. only keep the MCU awake in order to drive the Buzzer/LED while there is continuity), but 99.999% of the active power consumption is going to the Buzzer and power indicator LED. The MCU itself only uses 0.3 mA (or so) while awake anyway (1MHz @ ~3V).
Well, 0.5-1 mA should be enough for the LED, so it is more like 25-40%. But as mentioned, this should be inconsequential.
Well, 0.5-1 mA should be enough for the LED, so it is more like 25-40%. But as mentioned, this should be inconsequential.
A good portion of the active current is actually going to the Buzzer (probably 80% or so), and I don't really want to make that any quieter. I measured around 10 mA (@3V) with everything active, which is about the same as the ATtiny85 version. That could probably be optimized a bit (i.e. use slower ILRC instead of IHRC, dimmer power LED, quieter Buzzer), but certainly with diminishing returns.
EDIT: Yeah, I just verified that without the Buzzer connected, the active current is less than 1 mA (LED and MCU). So, currently the buzzer is using 90+% of the active current.
So one should introduce a "quiet" mode, for power users who don't have a lot of power available :) (no, not serious)
Here is a challenge: Operate it from a single LR41 cell (1.5V).
I measured the voltage on PFS154 digital output, when I output low level I measure 0.47V and 4.56V is the high level. PFS154 is powerred from 5V USB (actully 5.02V). So the low is pretty high, the high is pretty low.
Most of the digital IC will sense this voltage levels correct but on PIC and Atmel processors the low is very close to 0V and the high is the supply voltage.
Are there any configuration to get better results?
Here's a fun little project I whipped up on a breadboard today: https://github.com/serisman/pdk-continuity-tester (https://github.com/serisman/pdk-continuity-tester)
I measured the voltage on PFS154 digital output, when I output low level I measure 0.47V and 4.56V is the high level. PFS154 is powerred from 5V USB (actully 5.02V). So the low is pretty high, the high is pretty low.
Most of the digital IC will sense this voltage levels correct but on PIC and Atmel processors the low is very close to 0V and the high is the supply voltage.
Are there any configuration to get better results?
Here's a fun little project I whipped up on a breadboard today: https://github.com/serisman/pdk-continuity-tester (https://github.com/serisman/pdk-continuity-tester)
Nice little project. Thanks for sharing.
JS
Does the PFS173-S20 really exist? It is not listed on LCSC nor on Alibaba. It's only in datasheet...
Sure it exists and it is available in small quantities e.g. from Taobao:How do you chat and contact with them?
https://item.taobao.com/item.htm?spm=a1z10.5-c.w4002-15889356058.11.4f019facMXA64B&id=598987867714
0.5 RMB / pcs - for 50pcs (apx. USD 3.58) + shipping.
The seller is trustworthy. I ordered several times from there.
BTW: There are some Taobao forwarders which will help you to ship the things from taobao.
Adventure time :-)
Does the PFS173-S20 really exist? It is not listed on LCSC nor on Alibaba. It's only in datasheet...
Sure it exists and it is available in small quantities e.g. from Taobao:
https://item.taobao.com/item.htm?spm=a1z10.5-c.w4002-15889356058.11.4f019facMXA64B&id=598987867714
0.5 RMB / pcs - for 50pcs (apx. USD 3.58) + shipping.
The seller is trustworthy. I ordered several times from there.
BTW: There are some Taobao forwarders which will help you to ship the things from taobao.
Adventure time :-)
Hi all - first post!
I ordered the open source programmer PCB and I'm having trouble soldering the small components (my ego is writing cheques my eyesight can't cash...) which makes the resultant non-functional board difficult for me to troubleshoot. Is there any reason why the board can't be mostly through-hole (see attachment)? And if this is going to work:
- can all the SMD schottky diodes be replaced with 1N5817?
- can the 47uF cap be electrolytic and therefore have polarity?
- can the 6.8uH inductor be radial?
- are there through-hole equivalents for BSS138 and BSS84 (basically just trying to limit the SMD stuff)
- I've re-arranged the components for ease of use in putting the board together, but will the resultant long traces be a possible problem?
- there are 5 holes on the board (1 and then 4 together) but I have no idea for what purpose!?
I will keep soldering (I have 5 PCBs to trash in this experiment and I'm damn stubborn), but looking forward I was hoping that an old man version might be better suited to my needs. Thoughts and feedback appreciated!
OneCircuit
www.onecircuit.blogspot.com (http://www.onecircuit.blogspot.com)
How do you chat and contact with them?
Which agent do you use ?
I ordered the open source programmer PCB and I'm having trouble soldering the small components (my ego is writing cheques my eyesight can't cash...) which makes the resultant non-functional board difficult for me to troubleshoot. Is there any reason why the board can't be mostly through-hole (see attachment)? And if this is going to work:
If the PFS154 and PFS173 are not recognised, and nothing is able to be programmed - what would you recommend I swap out? Or should I just knuckle down and go for MKIII? I am getting better at SMD!
Have you checked voltages with "easypdkprogtest.exe"=?
Reference voltages when running easypdkprogtest:
+-------+
| O |
(DAC-VPP) 1.18V -> |5 P 4| <- -2.7V
1.18V -> |6 A 3| <- 2.49V (DAC-VDD)
(VPP) 5.0V <- |7 M 2| <- 2.49V
14.9V -> |8 P 1| -> 5.0V (VDD)
| .|
+-------+
Reference voltages when running easypdkprogtest:What's up with your 15V supply? It should be going to pin 8 of the opamp, and yours is apparently 1.69V. Is your dc-dc converter disabled, or faulty?
+-------+
| O |
(DAC-VPP) -2V -> |5 P 4| <- -6V
-2.42V -> |6 A 3| <- -0.78V (DAC-VDD)
(VPP) 0.32V <- |7 M 2| <- -1.44V
1.69V -> |8 P 1| -> 0.34V (VDD)
| .|
+-------+
What's up with your 15V supply? It should be going to pin 8 of the opamp, and yours is apparently 1.69V. Is your dc-dc converter disabled, or faulty?
Also the break-out boards, that can be plugged into the programmer, arrived.
VUSB won't fit into most padauks as they are around 1K ROM and 80 B RAM.
Check CH552 it is low cost, has HW usb and requires only 2 caps to operate.
Check CH552 it is low cost, has HW usb and requires only 2 caps to operate.If it can be done on a padauk, it would cost a lot less, It can be replaced for USB to UART.
VUSB won't fit into most padauks as they are around 1K ROM and 80 B RAM.
tim_ has a project from a few years ago (https://cpldcpu.wordpress.com/2014/03/19/%c2%b5-wire-usb-on-an-attiny-10/ (https://cpldcpu.wordpress.com/2014/03/19/%c2%b5-wire-usb-on-an-attiny-10/)) (https://github.com/cpldcpu/u-wire (https://github.com/cpldcpu/u-wire)) where he got a subset of the V-USB stack working on an ATtiny10 using 988 bytes of flash and 32 bytes of SRAM.
So, it might actually be possible to get something working on these Padauk MCUs. It would probably require 'overclocking' and/or using the undocumented 16MHz sysclock mode. Other than the novelty factor, I'm not sure how useful it would actually be, though.
I finally designed a PCB for my Padauk based 7-segment digital clock.
I also moved the project to its own repository and added some README files:
https://github.com/serisman/pdk-digital-clock
It will take about two weeks before the PCBs are delivered to me, but I feel pretty confident in the design. I've been running it on a breadboard for a few weeks now.
Feel free to suggest new 'features' or make pull requests with enhancements or bug fixes.
000000011001001010000100100001000110010010000100100001001001010010000100It's a beauty >:D ^-^
000000011001001010000100011001001000010010000100100001001001010010000100
000000011001001010000100100001001000010001100100100001001001010010000100
000000010101010110000100100001001000010010000100100001001001010010000100
Quote000000011001001010000100100001000110010010000100100001001001010010000100It's a beauty >:D ^-^
000000011001001010000100011001001000010010000100100001001001010010000100
000000011001001010000100100001001000010001100100100001001001010010000100
000000010101010110000100100001001000010010000100100001001001010010000100
INTEN IO_RW 0x04
$ 7 @4 : X, TM3 | PWMG2
$ 4 @3 : X, COMP | PWMG1
I am trying to implement tone function.
I am looking for a way to do microseconds delay (like delayMicroseconds() in Arduino). However, existing delay functions are either for milliseconds only or way too large and use all the SRAM.
Any help would be greatly appriciated!
The delay.h file from the free-pdk-examples repo (https://github.com/free-pdk/free-pdk-examples/blob/master/include/delay.h) has a _delay_us(us) macro in addition to the _delay_ms(ms) macro and only uses up (at most) 7 bytes of SRAM (less if you comment out the delay loop methods that aren't needed).
If you already tried using that delay.h file and are still running out of SRAM, it could be one of the following issues:
- Possibly there is a bug in the version of SDCC you are using? Try the latest nightly.
- If you are including delay.h in multiple .c source files, each one seems to get their own allocation of the method parameters for some reason. The file should really be broken out to separate delay.h and delay.c files to fix this. I'll update the examples repo at some point.
Thank you for the advice! However, Even I stripped the delay.h to the smallest possible, I still got a SRAM full error.
Here is my source code: https://gist.github.com/Kashouryo/fcf1a8a6995ab7934b9abf936646f6ad
||ASlink-Warning-RAM value 134 too large (128B max)|
_delay_us(100);
uint8_t testVal = 100;
_delay_us(testVal);
uint8_t testVal = 32; // 2 cycles - value = ((100uS -3) /3)
__asm
00001$: // 3 cycles per loop
dzsn _testVal // 1 cycle + 1 cycle for final skip
goto 00001$ // 2 cycles
__endasm;
You might be able to put some/most of this in a macro and/or possibly SDCC would already generate optimal loop code by just using a while (--testVal); loop or something similar.Do you have a more complete example of what you are trying to accomplish?I am trying to implement an Arduino-like tone function that outputs a specific frequently on a pin.
Do you have a more complete example of what you are trying to accomplish?I am trying to implement an Arduino-like tone function that outputs a specific frequently on a pin.
What's up with your 15V supply? It should be going to pin 8 of the opamp, and yours is apparently 1.69V. Is your dc-dc converter disabled, or faulty?
It's a mess for sure - I'm going to start again and hopefully have better success with MKIII. :-//
Take care,
OneCircuit
Hi all,
Trying my MKIV programmer with "easypdkprog probe" and get the following...
PFS154 probe
Probing IC... found.
TYPE:FLASH RSP:0x1AA1 VPP=4.50 VDD=2.00
IC is supported: PFS154 ICID:0xAA1
...blinky works...
PFS173 probe
Probing IC... found.
TYPE:FLASH RSP:0x1EA2 VPP=4.50 VDD=2.00
IC is supported: PFS173 ICID:0xEA2
...blinky works...
PMS150C probe
Probing IC... found.
TYPE:FLASH RSP:0xF VPP=4.50 VDD=2.00
Unsupported IC
...no blinky... :-\
But "easypdkprog list" gives...
PMS150C (0xA16): OTP : 1024 (13 bit), RAM: 64 bytes
...so I've tried multiple chips from two different batches of PMS150C but no luck! Any suggestions?
Take care,
OneCircuit
Meanwhile here is something interesting. MCUs from Shenzhen Zhien:
hxxp://www.zhienchina.com/product/MCU.html
They seem to be making Padauk MCUs as well. But they have other MCUs with embedded Padauks.
Here is an example:
XDM2102x series, a PMS150C + TP4056 Charger + 1 Amp Motor charger, all in one.
Seems like the software is recognising your PMS150C as a flash micro. Make sure your cli software and your programmer firmware are up to date.
Hi all,
Trying my MKIV programmer with "easypdkprog probe" and get the following...
PFS154 probe
Probing IC... found.
TYPE:FLASH RSP:0x1AA1 VPP=4.50 VDD=2.00
IC is supported: PFS154 ICID:0xAA1
...blinky works...
PFS173 probe
Probing IC... found.
TYPE:FLASH RSP:0x1EA2 VPP=4.50 VDD=2.00
IC is supported: PFS173 ICID:0xEA2
...blinky works...
PMS150C probe
Probing IC... found.
TYPE:FLASH RSP:0xF VPP=4.50 VDD=2.00
Unsupported IC
...no blinky... :-\
But "easypdkprog list" gives...
PMS150C (0xA16): OTP : 1024 (13 bit), RAM: 64 bytes
...so I've tried multiple chips from two different batches of PMS150C but no luck! Any suggestions?
Take care,
OneCircuit
On the plus side - my second SMD version had some small success - it recognised the PMS150C, but not the PFS154 or PFS173. It was unable to program any of them...
PMS150C:
easypdkprog probe
Probing IC... found.
TYPE:OTP RSP:0x285A0 VPP=4.50 VDD=2.00
IC is supported: PMS150C / PMS15A ICID:0xA16
Please always use the "-v" option to give verbose output. This will show more details in case something is wrong.
BTW... I just saw that you wrote some time ago that you already had success with PMS150C:
Confused.....
...
The trouble now is, I can't seem to flash the firmware with `dfu-util`. Power seems to be going to the board, as checked at the 1x4 male header, but nothing shows up in `lsusb`.
...
Is there something obvious I'm missing or is my best option to start poking SMD bits with my multimeter?
...
The trouble now is, I can't seem to flash the firmware with `dfu-util`. Power seems to be going to the board, as checked at the 1x4 male header, but nothing shows up in `lsusb`.
...
Is there something obvious I'm missing or is my best option to start poking SMD bits with my multimeter?
Did you remember to press and hold the button while plugging it in to enable bootloader mode?
Yup. Tried every boolean combination of Button First | Plugging In | Button While Doing lsusb. No change in the output.
Yup. Tried every boolean combination of Button First | Plugging In | Button While Doing lsusb. No change in the output.
Long time ago I had serious doubts when looking on the schematic of the programmer. The chip would allow programming via SWD and also via bootloader, but instead placing a suitable connector on the board, a pushbutton was placed.
I myself refuse to smudge my HDD by installing such a dfu-util. Programming via bootloader would be the cleanest and easiest way, but the schematic does not provide it. So the best way for you is to use a eval-board from ST and use the onboard ST-Link from this board to program the programmer. A better way would be using a JLink from Segger and manually connect the /reset to it.
And do not forget: fresh chips from ST often need to be bulk erased and unlocked before they are ready to be programmed.
Yup. Tried every boolean combination of Button First | Plugging In | Button While Doing lsusb. No change in the output.
... Programming via bootloader would be the cleanest and easiest way, but the schematic does not provide it. So the best way for you is to use a eval-board from ST and use the onboard ST-Link from this board to program the programmer. A better way would be using a JLink from Segger and manually connect the /reset to it.
And do not forget: fresh chips from ST often need to be bulk erased and unlocked before they are ready to be programmed.
I myself refuse to smudge my HDD by installing such a dfu-util.
I am working on an 8 bit PWM tone project. The current status is WIP but in a useable state.
https://github.com/Kashouryo/Padauk-tone
I am working on an 8 bit PWM tone project. The current status is WIP but in a useable state.
https://github.com/Kashouryo/Padauk-tone
May i ask why you have included "code" your tone.h file ?
That is a bit unconventional.
/Bingo
I am working on an 8 bit PWM tone project. The current status is WIP but in a useable state.
https://github.com/Kashouryo/Padauk-tone
May i ask why you have included "code" your tone.h file ?
That is a bit unconventional.
/Bingo
That's actually quite common in padauk projects that I read before.
It seems that the PFS173 power on reset does not work if the slew rate is too low. My power supply takes around 50 ms to ramp to final voltage. This will lead to the PFS173 not starting at all. See waveform here:
There are also several "code options" mentioned in the datasheet. Has anybody already figured out how these can be activated? f.E. seetting the PWM clock source to IHRC*2.
Yeah, but that is not done because this is acceptable style, but because SDCC is not able to remove unused functions from the binary... I know I am also guilty of this, but generally no code should be in the include files.
I haved documented the code options and how to use them here: https://free-pdk.github.io/tutorial#code-options (https://free-pdk.github.io/tutorial#code-options)
Yup. Tried every boolean combination of Button First | Plugging In | Button While Doing lsusb. No change in the output.
Does your device enumerate when you plug it in while the button is pressed? It should show up as "STM32 BOOTLOADER". If it does not, then there is certainly a hardware issue, like a solder bridge or incomplete connection. Trying to program the device with SWD will not make that issue go away. Choose wisely where you spend your effort :)
Did you check the 3.3V supply? Did you check the USB connection on the PCB?
:palm:
I feel like quite the fool now. It turns out that tacky flux like you'd use in a reflow oven is quite the insidious chemical.
All I had to do was replace the button, flux seems to have wormed its way inside and disabled it. A fresh button from the batch passed continuity, the original didn't.
One sudo whack at it later and it's flashed. Next will be getting it to talk to a real chip, it complains there's "nothing found" with more verbosity saying "command ack failed / wrong icid".
I guess it's round two with the multimeter :D
I wonder if a dunk in isopropyl would clear the button out. Not like I don't have a dozen more on hand, but I might still try it as an investigation of the flux.
I certainly won't be doing the next board the same way!
:palm:
I feel like quite the fool now. It turns out that tacky flux like you'd use in a reflow oven is quite the insidious chemical.
All I had to do was replace the button, flux seems to have wormed its way inside and disabled it. A fresh button from the batch passed continuity, the original didn't.
One sudo whack at it later and it's flashed. Next will be getting it to talk to a real chip, it complains there's "nothing found" with more verbosity saying "command ack failed / wrong icid".
I guess it's round two with the multimeter :D
I wonder if a dunk in isopropyl would clear the button out. Not like I don't have a dozen more on hand, but I might still try it as an investigation of the flux.
I certainly won't be doing the next board the same way!
Yeah, after a couple iterations, the typical points of failure become obvious :)
You should compile "easypdkprogtest" and check for the voltages to verify that the programming voltage control works properly.
Hmm... what are the voltages supposed to be? I got 19.83, 5.01, and vref=3.31.
Based on the source for the test, pressing the button should light an LED, but it didn't.
Also, there's a keypress time-out function, but it didn't respond to that either. I had to kill the program with ^C.
Gave it about four runs, same results each time... but now the programmer's just vanished from USB. I guess something failed on the board and took the STM offline.
Uhm, the voltages should be 5.0 V, 5.0V and 3.3 V. 19.85 certainly is too high, this is even above the nominal boost converter output. Did you miss any resistors anywhere, or are some values are mixed up?
I have been working with the PFS173 again, only to bump into some additional oddities. Not sure where else to document this:
Power on reset
It seems that the PFS173 power on reset does not work if the slew rate is too low. My power supply takes around 50 ms to ramp to final voltage. This will lead to the PFS173 not starting at all. See waveform here:
When I detach and attach the connection manually, everything is fine:
11 Bit PWM
It took me quite a while to figure out why the PWM frequency was never the one I tried to set: The 11 Bit PWM is actually a 10 bit counter. The eleventh bit is generated by a ANDing the LSB with the clock. Therefore only 1024 maximum counts should be assumed when calculating the PWM frequency.
It seems that the input enable register PBDIER has a default reset state of 0x00, while that datasheet states that it is 0xff. I wonder whether this is actually an errata or maybe the registers are usually set by Mini-C.
It seems that the input enable register PBDIER has a default reset state of 0x00, while that datasheet states that it is 0xff. I wonder whether this is actually an errata or maybe the registers are usually set by Mini-C.
The latter is true, see also https://free-pdk.github.io/tutorial#registers (https://free-pdk.github.io/tutorial#registers)
It seems that the input enable register PBDIER has a default reset state of 0x00, while that datasheet states that it is 0xff. I wonder whether this is actually an errata or maybe the registers are usually set by Mini-C.
The latter is true, see also https://free-pdk.github.io/tutorial#registers (https://free-pdk.github.io/tutorial#registers)
Hm... I cannot imagine that all registers contain random values at reset, because there certainly are some combinations that would cause undesireable behavior.
Maybe only a few registers are off. But that's something that can be easily checked.
Hm... I cannot imagine that all registers contain random values at reset, because there certainly are some combinations that would cause undesireable behavior.
Maybe only a few registers are off. But that's something that can be easily checked.
True - the wording can certainly be improved. When I wrote "undefined", I meant "is initialized to a fixed value that may differ from the datasheet, therefore its better to always set all registers explicitly". Of course, it would be even better to have a definitve list of all µCs and their respective true initial register values.
Dumping initial state of I/O area
00: F0 F0 A6 9E 00 08 00 00
08: 00 00 00 00 00 00 00 00
10: 20 00 00 00 00 00 00 00
18: 00 00 00 00 00 00 00 00
20: 40 00 FF E0 E0 E0 E0 E0
28: E0 E0 E0 00 00 E0 60 61
30: 00 00 00 00 00 00 00 00
38: 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00
48: 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00
58: 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00
68: 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00
78: 00 00 00 00 00 00 00 00
Dumping initial state of I/O area
00: F0 55 A6 9E 00 08 00 55
08: 55 55 55 55 55 55 55 55
10: 20 00 00 00 00 00 00 55
18: 00 00 00 55 55 55 55 55
20: 40 00 FF E0 55 55 55 55
28: 55 55 55 00 55 E0 60 21
30: 00 00 55 55 00 00 55 55
38: 55 55 55 55 55 55 55 55
40: 00 55 55 55 55 55 00 55
48: 55 55 55 55 00 55 55 55
50: 55 55 55 55 55 55 55 55
58: 55 55 55 55 55 55 55 55
60: 55 55 55 54 55 55 55 55
68: 55 55 55 55 55 55 55 55
70: 55 55 55 55 55 55 55 55
78: 55 55 55 55 55 55 55 55
Hm... there seems to be something undocumented at the adresses 0x2d, 0x2e, 0x2f
Hmmm.... 0x2d is cleary a control register. Reset state is 0xE0. Bits 7-5,3,1,2 are R/W, Bits 4 and 2 RO. 0x2e and 0x2f appear to be read only.
Any ideas what could this be? It's also not mentioned in the official includes. These could possibly be test registers.
Hm... there seems to be something undocumented at the adresses 0x2d, 0x2e, 0x2f
Hmmm.... 0x2d is cleary a control register. Reset state is 0xE0. Bits 7-5,3,1,2 are R/W, Bits 4 and 2 RO. 0x2e and 0x2f appear to be read only.
Any ideas what could this be? It's also not mentioned in the official includes. These could possibly be test registers.
I think I have an idea what it could be...
Some time ago when I was deep into research I found out about the really undocumented RFC (Resistance to Frequency Converter). This might be used as a poor men's touch interface or ADC?
You can still find some comments only in some of the PDK .INC files.
After digging a bit deeper I found some info in an old Puolop datasheet for PTBO165C : http://www.htsemi.com/xiazai.aspx?aa=/include/upload/download/_20180709113738742.pdf&bb=PTBO165CXXS (http://www.htsemi.com/xiazai.aspx?aa=/include/upload/download/_20180709113738742.pdf&bb=PTBO165CXXS)
Sections 3 and 4:
3. RF Inverters Functions Description
4. RFC (Resistance to Frequency Converter) Functional Description
This small data sheet explains register settings and how to use them. From the PDK .INC files it is also obvious that this feature is present in some more IC (not only in 165C). Maybe it is just not working and that's why missing from data sheet or it is sold as extra feature in different IC marketing derivates.
RFCC IO_RW 0x36 (0x2D, -)
$ 7 ~ 5, 0 : PA4, PB4, PA0, PB3, X, PB2, X, PB1,
PA3, PB0, PB7, X, PB6, X, DISABLE : 0xE
$ 4 : X, START : WR_BIT
$ 3 : R_TYPE, C_TYPE // PA4 only for C_TYPE
// ICE Only support R_TYPE
$ 2 : X, Overflow
$ 1 : X, Output // PB5
RFCCRH IO_RO 0x37 (0x2E, -)
RFCCRL IO_RO 0x38 (0x2F, -)
interrupt latency
I measured interrupt latency to be 6 cycles till the first instruction of the interrupt handler. Can anyone confirm this? Jitter is 2 cycles, assuming an infinite rjmp loop in the main program.
It seems that the PFS173 spends two more cycle on something else...
Dumping initial state of I/O area
00: F0 55 66 9E 00 87 00 55
08: 55 55 55 55 55 55 55 55
10: 01 00 00 55 00 00 00 55
18: 00 55 54 55 00 00 55 55
20: 00 55 55 55 55 55 00 55
28: 55 55 55 55 00 55 55 55
30: 55 55 00 00 55 55 F4 00
38: 00 55 55 55 55 55 55 55
JS, would you please add the STM32 Bin file along the DFU one too,
In a new design I have connected bootpin to ground, I can only program the STM32 with j-link and it would accept bin file or hex file.
Thanks
Thanks JS,
How we can set LVR for PFS173,
Is there any example code?
I want to set it to 4.0V
Thanks JS, I have done it, But I have a problem, the MCU some times would not boot after applying voltage to it, I thought maybe adding LVR would solve it, But the problem still remains, Do you have any other suggestion?
The PFS173 is powered from a DC/DC convertor, (the convertor has a slow startup voltage).
Dear JS
Thanks for your help, Unfortunately I have an analog oscilloscope, So I can not capture the wave form,
But I can share my code
Also This is the schematic, Note that Vin is coming from a secondary isolated winding from a flyback convertor.
Probably calibration is timing out. Put calibrate function call before delay loop
Maybe take a look at application note below. It clearly says that it's for PMC150/PMC153/ PMC156/PMC166 but who knows, maybe its 'bug' 'fixed' in orginal IDE .
http://www.padauk.com.tw//upload/ApplicationNote/PMC-APN006-PMC150_153_156_166_against_rapid_change_in_power_v003_EN_.pdf (http://www.padauk.com.tw//upload/ApplicationNote/PMC-APN006-PMC150_153_156_166_against_rapid_change_in_power_v003_EN_.pdf)
Maybe create some minimal code that changes pin state (something like from AN oscilloscope plot) and make some tests.
Not exactly matching the problem, but the suggestion to set INTRQ to 0 is a good one.Where the INTRQ should be 0?
Looks like in case IC (auto) resets some bits of INTRQ might be / get set and in case the interrupt handler does not process (clear all INTRQ bits) interrupt will run for ever (after exit of interrupt, IC sees at least one INTRQ bit is (still) set and interrupt is executed again, ..
EASY_PDK_INIT_SYSCLOCK_8MHZ(); //use 8MHz sysclock
EASY_PDK_CALIBRATE_IHRC(8000000,4000); //tune SYSCLK to 8MHz @ 4.000V
//EASY_PDK_FUSE(FUSE_SECURITY_OFF|FUSE_BOOTUP_SLOW);
//for(int cnt=0;cnt<10000;cnt++);
EASY_PDK_INIT_SYSCLOCK_8MHZ(); //use 8MHz sysclock
EASY_PDK_CALIBRATE_IHRC(8000000,4000); //tune SYSCLK to 8MHz @ 4.000V
JS, The new changes would not do any calibration!This is correct. It uses FACTORY CALIBRATION VALUE so the programmer does not need to do calibration. This was what I wanted to do. Now you can put the delay inside and program the IC without problems.
Can you confirm that the UART TX can be put on PA6 pin, I'm using PFS173 8pin version
Regards
Where the INTRQ should be 0?
EASY_PDK_FUSE(FUSE_SECURITY_OFF|FUSE_BOOTUP_SLOW);
Now I just have commented out
JS, The old code would not do calibration either! it was doing it before
I have done one time this codeCode: [Select]EASY_PDK_FUSE(FUSE_SECURITY_OFF|FUSE_BOOTUP_SLOW);
Now I just have commented out
Thanks JS,
The Code does not make any calibration, No matter what I put in startup code, I have done all the possible combinations!
[build] ?ASlink-Warning-Invalid address for instruction
[build] file module area offset
[build] Refby CMakeFiles\spl loop CODE 000050
[build] Defin CMakeFiles\spl loop DATA 010000
[build]
I suspect that clocksSpent may be not word-aligned as LDT16 instruction requires and I just accidentally was being lucky when code successfully compiled for pdk13?Hello! I am having problems with reading 16-bit timer value using an open-source toolchain:
- When trying to read the T16C value directly in the code, I am receiving the "Unimplemented __sfr16 load" from SDCC.
- I tried to use line of ASM code "__asm__("ldt16 _clocksSpent");" (where clocksSpent is my global uint16_t variable name). This compiles for pdk13 (PMS150C), but when compiling for pdk15 (PFS173) I am getting the following linker error:Code: [Select][build] ?ASlink-Warning-Invalid address for instruction
I suspect that clocksSpent may be not word-aligned as LDT16 instruction requires and I just accidentally was being lucky when code successfully compiled for pdk13?
[build] file module area offset
[build] Refby CMakeFiles\spl loop CODE 000050
[build] Defin CMakeFiles\spl loop DATA 010000
[build]
Does anyone have similar error? Is there are any workaround for this?
; save context
push af
mov a, p
push af
mov a, p + 1
push af
; load TM16C
ldt16 p
mov a, p
mov _clocksSpent, a
mov a, p+1
mov _clocksSpent+1
; restore context
pop af
mov p + 1, a
pop af
mov p, a
pop af
However, if additional context saving is required, 13 cycles to load the word feels pretty slow in comparison to single ldt16 instruction. Maybe in the end, it is better to just move variable declarations around :-\
Thanks, JS!
Yes, moving around variable declarations helps, works great as a temporary solution!
The second way (with virtual p register) seems more reliable, though. The only concern I have here is that I may accidentally clobber the previous (potentially important) p,a,f register values when running inline assembly? I suppose, additional push af / pop af and push/pop of with p register value may be required? Or p/a/f registers can be overwritten by the inline assembly without any consequences?Code: [Select]; save context
However, if additional context saving is required, 13 cycles to load the word feels pretty slow in comparison to single ldt16 instruction. Maybe in the end, it is better to just move variable declarations around :-\
push af
mov a, p
push af
mov a, p + 1
push af
; load TM16C
ldt16 p
mov a, p
mov _clocksSpent, a
mov a, p+1
mov _clocksSpent+1
; restore context
pop af
mov p + 1, a
pop af
mov p, a
pop af
First check: Please check that you use latest "pfs173.h"The file is the latest version
You can verify when you look in pfs173.h and find the following lines:
//set calibration macros
#define EASY_PDK_CALIBRATE_IHRC(frequency,millivolt) EASY_PDK_CALIBRATE_RC_M( EASY_PDK_CALTYPE_IHRC, 0x0B, frequency, millivolt )
Next check: Do you use the latest version of easypdk prog?
You can check by adding the -v option to easypdkprog command line:
easypdkprog -v --icname=PFS173 write build/lvrstartup.ihx
Searching programmer... found: /dev/tty.usbmodem1234567855AA1
FREE-PDK EASY PROG - HW:1.2 SW:1.3 PROTO:1.3
Erasing IC... done.
Blank check IC... done.
Writing IC (1592 words)... done.
Verifiying IC... done.
Calibrating IC
* IHRC SYSCLK=8000000Hz @ 5.00V ... calibration result: 8021146Hz (0x80) done.
unsigned char _sdcc_external_startup(void)
{
PBC=BIT0;
PB=BIT0;
PB=0;
MISCLVR = MISCLVR_4V;
CLKMD = CLKMD_IHRC_DIV2 | CLKMD_ENABLE_IHRC; // 16/2=8 Mhz main clock
EASY_PDK_CALIBRATE_IHRC(F_CPU, 5000); // tune SYSCLK to 9.6MHz @ 5.00V
return 0; // perform normal initialization
}
Oh wow, nice find, JS!
The CPU starts executing at VCC=2V (ch1) and keeps resetting until 4V is reached. Then it does indeed execute at 8 MHz in a stable way.
We should somehow introduce this as a standard include because it is a very annoying pitfall.
According to the datasheets I just checked, we should be able to achieve 8 MHz down to 3.5V. Can you verify things are still stable with a lower LVR?
According to the datasheets I just checked, we should be able to achieve 8 MHz down to 3.5V. Can you verify things are still stable with a lower LVR?
The PFS173 I have been using for testing worked down to 2.35V at 8MHz. I suppose that should not be taken for granted as it will change with higher temperature and device to device variation.
I guess 3.5V is safe.
DEVICE: PFS154 PFS172 PFS173 PMS150C PMS152 PMS154C PMS171B
MISCLVR or FUSE: MISCLVR(basic) MISCLVR MISCLVR FUSE MISCLVR FUSE MISCLVR
>= 8 MHz needs >= 3.5V 3V 3.5V 3V 3.5V 3.5V 3V
>= 4 MHz needs >= 2.5V 2.2V 2.5V 2.2V 2.5V 2.5V 2.2V
>= 2 MHz needs >= 2V 1.8V 2.2V 2V 1.8V 1.8V 1.8V
unsigned char _sdcc_external_startup(void)
{
MISCLVR = MISCLVR_4V;
CLKMD = CLKMD_IHRC | CLKMD_ENABLE_IHRC; // 16 Mhz main clock
PDK_USE_FACTORY_IHRCR_16MHZ();
return 0; // perform normal initialization
}
#define __stt16(var) __asm__("mov a, "_STR_VAR(var)"\n"\
"mov p, a\n"\
"mov a, "_STR_VAR(var)"+1\n"\
"mov p+1, a\n"\
"stt16 p\n");
// ....
static uint16_t tm16Value = 0;
void reset_timer16_counter(void) {
uint8_t timerMode = T16M;
T16M = T16M_CLK_DISABLE;
__stt16(tm16Value);
T16M = timerMode;
}
0x004c: 0x0186 MOV A, IO(0x06) ;T16M
0x004d: 0x1700 MOV [0x00], A ; <---- sdcc uses p as local variable storage
0x004e: 0x5700 MOV A, 0x00
0x004f: 0x0106 MOV IO(0x06), A ;T16M
0x0050: 0x1f02 MOV A, [0x02]
0x0051: 0x1700 MOV [0x00], A ; <---- value overwritten by the __asm__ block
0x0052: 0x1f03 MOV A, [0x03]
0x0053: 0x1701 MOV [0x01], A
0x0054: 0x0600 STT16 [0x00]
0x0055: 0x1f00 MOV A, [0x00] ; <---- restored wrong value
0x0056: 0x0106 MOV IO(0x06), A ;T16M
0x0057: 0x007a RET
Interesting, it seems now also the undocumented clk setting can be used to activate 16 MHz in the PFS173:
[…]
My 8 MHz blinky is twice as fast, so it seems to work. I never tried it before, maybe it worked all along?
Edit: Minimum voltage for 16 MHz is 3.9V. So I suppose that it is quite marginal and even 5V might fail at higher temperatures. I guess that is why they did not document this setting.
Thanks JS, But there is a wired error at compile time!
what's going on wrong?
#include <stdint.h>
I added automatic LVR setup for high clock rates to the Examples folder of the easy-pdk-programmer-software *development branch*.
=> https://github.com/free-pdk/easy-pdk-programmer-software/tree/development/Examples/src and defines in "easypdk" folder there.
Nice! I noticed you also added 16 MHz at 4 Volt for the PFS154 and at 4.5V for the PFS173. Does it mean that the PFS154 is more stable at 16V than the PFS173?
PFS173: VDD=5.7V, SYSCLOCK=16MHZ, CALIBRATED to 24MHZ ;D (the higher VDD seems to make a huge difference, @5.0V max was 18Mhz):
PFS154: VDD=5.9V, SYSCLOCK=16MHZ, CALIBRATED TO 23MHZ ;D
Searching programmer... found: /dev/tty.usbmodem1234567855AA1
FREE-PDK EASY PROG - HW:1.2 SW:1.3 PROTO:1.3
Erasing IC... done.
Blank check IC... done.
Writing IC (186 words)... done.
Verifiying IC... done.
Calibrating IC
* IHRC SYSCLK=23000000Hz @ 5.90V ... calibration result: 23088037Hz (0x9E) done.
Hi, I'm trying to find out what I need to know about the pins of Padauk's OTP device if they are to be programmed AFTER PCB assembly, not before. The datasheet doesn't say that.
Obviously there are two aspects to it:
- the programming signals must not damage other components connected to the Padauk
- the other components must not interfere with the programming of the Padauk
This should be a non-issue for pins where for example push buttons are connected. But what about pins for example connected to the middle pin of a 5KOhms potentiometer between GND and VCC? Also, is VCC during programming something usual such as 3V3 or can it be way up which risks damaging other components?
I can imagine it could also be an option to have jumpers on the PCB which are manually closed after programming, but I would really need the information of which pins are concerned and what I need to know about them. Can you point me to that information?
Sooo, in case someone is looking for a new 8 bit MCU to reverse. There seems to be a a new chinese competitor to Padauks strategy, aptly named "Fremont Micro Devices". Of course, they are absolutely not based in Fremont. (Correction, they seem to have an office there, but it's not even listed on their homepage)I got my hands on 50x FT60F211 thinking they would be compatible enough to be not only used with PIC development tools, but also being programmed with a PIC programmer, which would make them a much much easier to use alternative to Padauk. Sadly, when trying to read them as any kind of 8 pin PIC, my TL866CS complains that it's got an overcurrent issue. Oh well.
https://lcsc.com/products/Other-Processors-And-Microcontrollers-MCUs_11116.html?q=fremont%20micro%20devices (https://lcsc.com/products/Other-Processors-And-Microcontrollers-MCUs_11116.html?q=fremont%20micro%20devices)
https://www.fremontmicro.com/en/product/mcu/index.aspx (https://www.fremontmicro.com/en/product/mcu/index.aspx)
They have a line up of flash based 8 bit microcontrollers. The cheapest one (FT60F210) is only $0.05, beating the PFS154. The documentation is a bit unclear whether they are really flash based, but there are several references. They don't look too exciting. The core is again PIC-related. One interesting feature is integrated EEPROM. They also have slightly more complex periphery than Padauk in the larger devices.
The programming interface seems to be low voltage, which is interesting. A big caveat is that the documentation only seems to be chines.
Well, it's not too interesting, as there are already Padauk MCUs.
edit: Okay, the MCU core is a PIC16 clone. The IDE actually comes with an ancient version of the Hi-tech C-compiler.
Since I was interested, instead of hijacking this thread I've created a new one with all the information I've gathered so far: https://www.eevblog.com/forum/projects/fremont-micro-devices-microcontroller-programming/ (https://www.eevblog.com/forum/projects/fremont-micro-devices-microcontroller-programming/)
Help is welcome!
I just tried it from another computer an the was no problem at all (with the same easypdkprog.exe). As soon as I am at home I will try it again. I think maybe the program is blocked (I used the exe from the releases and did not compile myself).
It seems like the programm had a problem with some of my other COM Ports (virtual bluetooth COM Ports), thats why it stuck at the search for the programmer
I habe another program,
I already build up one programmer and now build some more as a gift and as spare. So far the boards seem to work and I could flash them with the firmware. Tee problem I have with the new boards is, that if I connect them to the PC they always enter the mode to program them. I could not figure out why till now. I measured the connections and they seem to be okay. If I press the botton for the programming mode I get 3.3V on Pins Boot0 und PA15, but if I release the button I get 1.0V instead of 0V. So far I testet the pulldown resistor and it is connected correct and also switched the 20k to 10k without result (only the measured voltage droped a tiny bit). I could not figure out what I did wrong. I have to of this boards which show the same behavior. THe only difference to my first and working pdk programmer ist the supplier of the chips. The first came from lcsc but the chips from the other boards came frome a seller from ebay, because I could not find the chip from any distributor (lcsc, mouser, digikey, ...). Could it be that I have got fake chips (but if thats the case it is strange that I could program them without a problem).
Yes I checked that thr flashing ist corect. I flashed the same firmware for both (my first and the new programmers). The firmware ist flashed and the progress bar reaches by all programmers the 100% and fineshes flashing.
What can I try next?
Can you provide the output of DFU util so we can have a look?
Readout of the the programmer worked with dfu-util. I compared the working programmer, the two not working and the firmware file.
The file from the working programmer and the firmware were the same. The file from the two not working programmers had some clear text errors like "Flash WRP is not setting...", "Flash WRP setting error!", "Checksum FAIL!!", ...
Readout files 2 and 3 are frome the "defect" programmers, file 1 from the working.
Thank you for the hint with the to high temperature. The were new but at first I soldered them the wrong way and had to desolder them (280°C for a few minutes) to turn them the right way.
Could you tell me from the readout, if the flash is really bad and if I have to switch the uC?
Start the ST Flash Loader Demonstrator, select the COM port from your connected FTDI adapter, click Next and if all goes well the STM32F072 is detected.
In case you can not detect the IC make sure, use a power bank or your phone charger and plug it into USB port of easy pdk programmer while holding the button.
(This prevents STM32 ROM bootloader to enter USB DFU which it would do in case USB activity is detected, instead it wait for UART connect which you will do with the ST tool).
Also you might need to exchange RX and TX (not sure how your FTDI adapter is labeled).
When STM32F072 was detected properly you can select a firmware to flash (you can use the DFU file directly - even that it asks you for bin file). When you try to flash it the ST tool will tell you that it needs to remove the WRITE PROTECTION, click on "yes" and this should do the trick.
Start the ST Flash Loader Demonstrator, select the COM port from your connected FTDI adapter, click Next and if all goes well the STM32F072 is detected.
In case you can not detect the IC make sure, use a power bank or your phone charger and plug it into USB port of easy pdk programmer while holding the button.
(This prevents STM32 ROM bootloader to enter USB DFU which it would do in case USB activity is detected, instead it wait for UART connect which you will do with the ST tool).
Also you might need to exchange RX and TX (not sure how your FTDI adapter is labeled).
When STM32F072 was detected properly you can select a firmware to flash (you can use the DFU file directly - even that it asks you for bin file). When you try to flash it the ST tool will tell you that it needs to remove the WRITE PROTECTION, click on "yes" and this should do the trick.
I tried it with both not working programmer, but none of them was detected. I made sure the PINs are connected correctly and the power came from a phone charger. I also pressed the button while connection to power. The ST Flash Tool always ran in a timeout.
When STM32F072 was detected properly you can select a firmware to flash (you can use the DFU file directly - even that it asks you for bin file). When you try to flash it the ST tool will tell you that it needs to remove the WRITE PROTECTION, click on "yes" and this should do the trick.
PA |=1<<4:
PAC |=1<<4; // HI
PAC &=~(1<<4); // Z
PA |=1<<4:
PA |=1<<3; // turn on PA3
PAC |=1<<4; // This will not activate the pin anymore!
PAC &=~(1<<4); // Z
GPCC = GPCC_COMP_ENABLE | GPCC_COMP_MINUS_BANDGAP_1V2; // Activate comparator. Negative input is bandgap, positive input is resistor ladder
// SAR ADC using the internal resistor ladder
__asm
mov a, #0x20 ; GPCS.4 = 0 GPCS.5 = 1
or a, #0x08 ; Bit 3
mov __gpcs,a
t0sn __gpcc, #6
xor a, #0x08
or a, #0x04 ; Bit 2
mov __gpcs,a
t0sn __gpcc, #6
xor a, #0x04
or a, #0x02 ; Bit 1
mov __gpcs,a
t0sn __gpcc, #6
xor a, #0x02
or a, #0x01 ; Bit 0
mov __gpcs,a
t0sn __gpcc, #6
xor a, #0x01
and a,#15 // Result is now in A register.
set0 __gpcc,#7 ; turn comparator off
ret
__endasm;
Hello,
1st of all, big thank you to everyone who worked on this incredible project.
I have an issue, I have carefully assembled the Easy-pdk-programmer pcb 2 times (although I think I got PTSD from soldering it) and both times I get the same result; 9193-33 regulator (U2 on schematic) heats up rather quickly and PC does not recognize that a device has been plugged into USB. I can find no shorts or cold joints. Is it possible I cooked one of the components while soldering? I know this is super vague but any suggestions before I try to solder a 3rd board and ruin that one too would be great. Thanks.
*edit* I get less than 1 ohm of resistance across C5, C7, C8, C9, C12. That will mean that the Vout of the regulator is essentially shorted to ground (which explains why board doesn't start) but can't tell in-circuit what the issue is. seems like maybe I should try and re-solder the microcontroller because it has a bunch of pins where 3.3v and GND are adjacent, so most likely that is where the problem is?
I may have found a strange bug (feature?) in the IO ports of the PFS154.
I used the following code to switch a PGIO between logical high ("Hi") and high impedance state ("Z").Code: [Select]PA |=1<<4:
PAC |=1<<4; // HI
PAC &=~(1<<4); // Z
This works fine. But if another port is accessed in between, it appears that the state of PA is lost?Code: [Select]PA |=1<<4:
PA |=1<<3; // turn on PA3
PAC |=1<<4; // This will not activate the pin anymore!
PAC &=~(1<<4); // Z
Very odd. Has anybody seen similar?
Hi everyone:
Padauk IDE 0.91 version. It update PDK "29" version
Don't depdk it?
Really.... ? ? ? ?
Self modifying code now in PADAUK IDE to "protect" the "obfuscation" and then the only "new" thing is xoring 4 different values from key and changing 0x12345678 to 0x123457AE ?
:-DD
=> depdk / dispdk got support for IDE 0.91 pdk files (check github)
JS
While investigating this, I measured the transient power consumption of the PFS154. (I used a self-made wide bandwidth transimpedance amplifier with JFET input to amplify the current). You can see an example of a power signature for LRC execution below.Could you show more details how you created this power trace with your JFET amplifier? What kind of bandwidth do you estimate for it?
A further thought on PMS15A and PMS150C: The die in PMS15A and PMS150C might be the same, the initial information stored in the OTP ROM might differ between these two ICs. And that's how the official Padauk programmer distinguishes these ICs.
Can you read a blank PMS15A of yours and share the readout "easypdkprog -n PMS150C -b read pms15aempty.bin".
Can you read a blank PMS15A of yours and share the readout "easypdkprog -n PMS150C -b read pms15aempty.bin".
There are differences between 150C and 15A's readouts. From 0x7Ec to the end of the binary file.
;XXX: timer16 setup -- this is broken
mov a, #(( 1<<0 | 1<<3 | 4<<5 )) ; ovf@bit9, clk/4, ihrc
mov t16m, a
mov a, #2 ; enable timer16 int, disable all others
mov inten, a
; ...
engint
I've been experimenting with the PMS150c recently, and I have hit a snag: What's the correct way to initialize Timer16 to fire an interrupt in assembly?
Here's my attempt (full code attached):Code: [Select];XXX: timer16 setup -- this is broken
mov a, #(( 1<<0 | 1<<3 | 4<<5 )) ; ovf@bit9, clk/4, ihrc
mov t16m, a
mov a, #2 ; enable timer16 int, disable all others
mov inten, a
; ...
engint
I want timer16 to cause an interrupt every 512 cycles. The IVR then changes the PWM duty cycle of timer2 (timer2 works).
Looking at the generated code (with dispdk, also attached), it seems like it should work :/
Thanks in advance for any help!
here is most likely your error, T16 int is BIT2 = 1<<2 = 4 ==> mov a, #4
In case you like some more comments:
* your setup of TM16 is wrong, according to your comment you want every 512 cycles to get an interrupt. For this you need to setup BIT8 overflow (see data sheet: "9.2.5. TIMER time out" for full details)
* your comment about "no calibration" is incorrect. In fact without setting IHRCR it will stay 0 after reset which causes for IHRC/4 something around 2.5MHz instead of the 4MHz (this also affects your PWM timing)
* your interrupt does not have the pushaf / popaf (this could cause problems if you ever add some more code to your "loop")
* pac all set as output will not save power... (unused pins should be set as input)
* your comment about "no calibration" is incorrect. In fact without setting IHRCR it will stay 0 after reset which causes for IHRC/4 something around 2.5MHz instead of the 4MHz (this also affects your PWM timing)
I noticed that it was way too slow; I intend to use the instructions from the EASY_PDK_CALIBRATE_RC_M macro once I got the other parts working. And while i have your attention: I guess, just pasting those ANDs in and removing the --nocalibrate flag is enough? And I assume it's possible to calibrate to "odd" values, like 4.096MHz?
Hi everyone:
I compile calib-and-fuse-demo.c.
When I use program PMS150 OTP, how to calibration IHRC?
Then I want to know free PDK how to calibrate ihrcI think these are all you'll need. Not as simple as ".ADJUST_IC SYSCLK=IHRC/2;" but you get more control over the calibration process.
unsigned char _sdcc_external_startup(void)
{
// example, edit to suit
AUTO_INIT_SYSCLOCK();
AUTO_CALIBRATE_SYSCLOCK(TARGET_VDD_MV);
return 0; //perform normal initialization
}
and a, #( 4194304 ) ;4MHz = 4194304HzAFAIK, MHz is defined as 10^6, not as 2^20. so 4MHz should be 4000000Hz.
Calibration worked perfectly, thanks for the explanation.I know that... I gave this example since you asked for fractional MHz frequency value like 4.096MHz. I just forgot to update the comment ;-)and a, #( 4194304 ) ;4MHz = 4194304HzAFAIK, MHz is defined as 10^6, not as 2^20. so 4MHz should be 4000000Hz.
Next, and hopefully last 2 issues: my Timer16 interrupt is triggered twice in a row, and sometimes is offset. I attached a screenshot; the blue channel goes high whenever the IVR is active. And there are always two peaks next to each other. Also, it looks like it is "jittering" a lot: the interrupt is triggered early/late by the exact duration of a double-trigger (the double-double-peak on the left is "persistent phosphor" from two runs in a row...if that makes sense).
I am wondering what those two issues could be caused by and how to prevent them. The datasheet mentions that the T16 interrupt happens whenever the bit _changes_, but that should also be at regular intervals, not directly after the IVR was exited.
Hi gir:The problem is related to PMS150C. Do you say you can run it on PMS150C with stopexe and without jitter? Maybe your resolution of the logic analyzer is not high enough.
I run your test file.
It's fine
Hong
thanks,
I find "fpdkiccalib.c"
...
Yes, It 's magic code than Padauk. :-DD
Thanks JS, I managed to flash the Dev branch to the ARM and now it's working, But still only probing is working |O |O |O any Idea what might goes wrong?
Now you have to check your hardware variant. On the picture I saw that C1 is not populated and also Y1 is missing. A cap on the 15V rail is essential since VCC/VDD draw some power during programing. The crystal is used to get better tuning results after the CPU is flashed, without it the drift might be much higher or you create a very special clock path using the HSI48 with sync to USB frames (then programmer can not be used stand alone - a feature planned for future use, just like WRITER).
Also, since you changed the opamp, it might be possible that the output voltages differ. You can use the "easypdkprogtest" program to check that the output voltage is correct:
DO THIS WITHOUT A MCU CONNECTED TO THE PROGRAMMER
make easypdkprogtest
./easypdkprogtest
vdd: 5.01 vpp: 4.98 (vref= 3.30)
Please check that VDD and VPP are 5V and VREF is 3.3V. Also measure them on your PCB.
In case VDD and VPP voltages are incorrect you need to tune the DAC reference values for your specific hardware (in fpdk.c you need to change FPDK_VDD_DAC_MAX_MV / FPDK_VPP_DAC_MAX_MV).
JS
Hello,
I build the pdk programmer a few times, but 2 of the programmer do not work. I can interface the STMs but cant programm or probe the padauk uCs. I run the easypdkprogtest from github and got as an result
vdd: 13.65 vpp: 13.55 (vref= 3.29)Thanks JS, I managed to flash the Dev branch to the ARM and now it's working, But still only probing is working |O |O |O any Idea what might goes wrong?
Now you have to check your hardware variant. On the picture I saw that C1 is not populated and also Y1 is missing. A cap on the 15V rail is essential since VCC/VDD draw some power during programing. The crystal is used to get better tuning results after the CPU is flashed, without it the drift might be much higher or you create a very special clock path using the HSI48 with sync to USB frames (then programmer can not be used stand alone - a feature planned for future use, just like WRITER).
Also, since you changed the opamp, it might be possible that the output voltages differ. You can use the "easypdkprogtest" program to check that the output voltage is correct:
DO THIS WITHOUT A MCU CONNECTED TO THE PROGRAMMER
make easypdkprogtest
./easypdkprogtest
vdd: 5.01 vpp: 4.98 (vref= 3.30)
Please check that VDD and VPP are 5V and VREF is 3.3V. Also measure them on your PCB.
In case VDD and VPP voltages are incorrect you need to tune the DAC reference values for your specific hardware (in fpdk.c you need to change FPDK_VDD_DAC_MAX_MV / FPDK_VPP_DAC_MAX_MV).
JS
I found this post here so I assume that something is wrong with my programmer. What can I do or check next? (As Tools I have an lab bench power supply, an oscilloscop and a multimeter)
I already checked R6. It has the correct value and is also solderd correctly.
I already checked R6. It has the correct value and is also solderd correctly.
In this case most likely the opamp U3 is damaged.
While running easypdkprogtest measure with your multimeter in DC voltage mode (one lead connected to GND):
U3:
pin8: 14.9V
pin4: -2.6V
pin3: 2.5V
pin2: 2.5V
pin1: 5V
pin5: 1.18V
pin6: 1.18V
pin7: 5V
What are your values?
JS
I already checked R6. It has the correct value and is also solderd correctly.
In this case most likely the opamp U3 is damaged.
While running easypdkprogtest measure with your multimeter in DC voltage mode (one lead connected to GND):
U3:
pin8: 14.9V
pin4: -2.6V
pin3: 2.5V
pin2: 2.5V
pin1: 5V
pin5: 1.18V
pin6: 1.18V
pin7: 5V
What are your values?
JS
My values are:
U3:
pin8: 15.0V
pin4: 4.5V
pin3: 3.8V
pin2: 6.2V
pin1: 13.7V
pin5: 3.8V
pin6: 3.82V
pin7: 13.6V
pin4: 4.5V <=== this should be a negative voltage !
==> check C14 / D2 / D3 / C3 - most likely the diodes are not soldered properly or in wrong orientation.
JS
Hi:
I compile pdk13 asm at PMS150
flow:
sdaspdk13 -losx sram.asm
sdldpdk -i -m -x -u sram
packihx sram.ihx > sram.hex
at sram.lst
00004E 50 1C 73 call push0
000050 2A 18 74 goto loop
It's correct.
but ihex
call push0 -> call 0x28
goto loop -> call 0x30
"sdlpdk -i -m -x -u sram"
Is the parameter setting wrong?
HI JS:
how to find ""0123f5b78da6c9e4".
It look random data.
Congratulations on the PMS150G!
Now the question is: how do we compile for PMS150G?
This chip contains a few additional features than PMS150C(e.g. PA5 can be used as a push-pull pin) but it runs slower(2MB).
.area OSEG (OVR,DATA)
tmp: .ds 22
var: .ds 1 ; 0x16
.area CSEG (CODE,ABS)
.org 0x0000
init:
SET1 var, #3
sdaspdk13 -o test.rel test.asm
sdldpdk -ni test.ihx test.rel
dispdk 2A16 test.ihx
0x0000: 0x0376 SET1 [0x06].3
spdk -t PDK13 test.ihx
0>pc 0
? 0x000 0376 set0 54, #3
mov a, #0
and a, #1
t0sn f, z
goto foo
Flag= 0x01( 1)
? 0x040 0c00 t0sn [0], #0
Flag= 0x01( 1)
? 0x041 1845 goto #69
mov a, #1
and a, #1
t0sn f, z
goto foo
Flag= 0x04( 4)
? 0x040 0c00 t0sn [0], #0
Flag= 0x04( 4)
? 0x041 1845 goto #69
Looking at the documentation (https://free-pdk.github.io/instruction-sets/PDK13), it looks like there was an error creating the table: the last two columns (constant and memaddr) are flipped in the header/body of the table (see attached screenshot). So which one is right?
Looking at the documentation at least made me realize that set1 M.n can only work on the first 16 SRAM-addresses. Given that, I think the assembler (or linker) should give an error here. Or is there something else going on?
edited to add: the 4-bit limitation is not mentioned in the datasheet, afaict.
Also, ucsim seems to not handle 't0sn IO.n'? the first example sets flag.zero, the second example clears it (this seems to work, looking at the Flag= output of ucsim). But in both cases ucsim continues execution with the next instruction (the goto)?!Code: [Select]mov a, #0
and a, #1
t0sn f, z
goto foo
Flag= 0x01( 1)
? 0x040 0c00 t0sn [0], #0
Flag= 0x01( 1)
? 0x041 1845 goto #69
mov a, #1
and a, #1
t0sn f, z
goto foo
Flag= 0x04( 4)
? 0x040 0c00 t0sn [0], #0
Flag= 0x04( 4)
? 0x041 1845 goto #69
Documentation says first 16 SRAM addresses can be used which translates to 4 bit for the address (4 bit can encode 16 addresses).
I agree that the assembler could bring up a warning / error in this case (you can create a ticket for sdcc developers).
Are you sure the goto instruction is actually executed in both cases?
Attached file "reload.zip"
It's io loop.
picture 1. don't "A5A5A5A4" key
picture 2. have "A5A5A5A4" magic key
PA3, P4, P5 connect to ardunio
It's generate "A5A5A5A4"
PA6 is PMG150C or PMG150G clock source.
When PA6 clock stop, then PA0, PA7 stop.
My project is done, btw: https://gir.st/chiptunes.html | https://git.gir.st/Chiptunes-pms150c.git
It plays 16 minutes of chiptune music when it's plugged in and requires no external components (well, except a coin cell).
Hi js
A quick question regarding the 16 bit timer.
In mini-c there's an instruction that called stt16. Which can set the value of T16 counter with one single 16 bit value(word). Is it possible to do so in Free PDK?
Thank you
__sfr16? Is that a macro or sth?
An example will be greatly appreciated.
Thank you
-------------- Build: Release in PWMBell154 (compiler: Small Device C Compiler)---------------
sdcc.exe -mpdk14 --opt-code-size -std=c11 -IC:\Software\FreePDK\include -IC:\Software\sdcc\include -c main.c -o obj\Release\main.rel
sdcc.exe -LC:\Software\sdcc\lib -o bin\Release\PWMBell154.ihx -mpdk14 --opt-code-size -std=c11 -lpdk14 obj\Release\main.rel
at 1: warning 118: option '-s' no longer supported 'use --code-loc instead'
?ASlink-Warning-Invalid address for instruction
file module area offset
Refby obj\Release\ma main CODE 000078
Defin obj\Release\ma main DATA 000007
at 1: warning 118: option '-s' no longer supported 'use --code-loc instead'
Process terminated with status 1 (0 minute(s), 0 second(s))
0 error(s), 1 warning(s) (0 minute(s), 0 second(s))
Hi JSThe warning suggests that you did not place the temp variable "uint16_t t16c_tmp;" at an even address (word alignment is needed for 16 bit access).
Thanks for the code example! however, the code doesn't work as expected. No matter which value I wrote during the T16 interrupt, the frequency stayed the same.
T16C does work and can modify the frequency. However, it only worked with 8 bit values(as you said, it's not implemented. They should really implement the 16bit part of it. Since in Mini-C you can just do "stt16 a16BitValue;" and everything works)
I also saw this error during the compilation.
?ASlink-Warning-Invalid address for instructionCode: [Select]-------------- Build: Release in PWMBell154 (compiler: Small Device C Compiler)---------------
sdcc.exe -mpdk14 --opt-code-size -std=c11 -IC:\Software\FreePDK\include -IC:\Software\sdcc\include -c main.c -o obj\Release\main.rel
sdcc.exe -LC:\Software\sdcc\lib -o bin\Release\PWMBell154.ihx -mpdk14 --opt-code-size -std=c11 -lpdk14 obj\Release\main.rel
at 1: warning 118: option '-s' no longer supported 'use --code-loc instead'
?ASlink-Warning-Invalid address for instruction
file module area offset
Refby obj\Release\ma main CODE 000078
Defin obj\Release\ma main DATA 000007
at 1: warning 118: option '-s' no longer supported 'use --code-loc instead'
Process terminated with status 1 (0 minute(s), 0 second(s))
0 error(s), 1 warning(s) (0 minute(s), 0 second(s))
Hi,
we now have support for PFC232. A flash based "Multi-Core" IC (in development branch). 8) 8) 8)
Hi,
we now have support for PFC232. A flash based "Multi-Core" IC (in development branch). 8) 8) 8)
Thanks for that.
Can you give some more details about that R6 mod witch is required for that to work ?
EDIT:
Ok, i found info that R6 have to be changed to 20k
And there is another question I have. For experimenting I use the PFS154, a breadboard and my lab bench power supply. It seems the uC has always problems and does not function as expected, if I enable the power output of my power supply. I have to apply power first and then put the uC on the breadboard or disconnect the power cable and connect it again.
I looked at the power on behavior. There are no peaks, only the loading curve of the output capacitors can be seen.
What could be the problem?
P.S. @gir:
I modified your bsv makefile to compile for pdk14 and changed 2 things in my emulator (512 instead of 256 syclocks, trigger TM16 int (0x04) instead of TM2 int) and it played the tune very well.
I think you can easily load noiseplug on your hardware (you only need to change the PWM output to use PA4)
I stumbled over a comment on github (all in chinese) which is asking if we want to research the PFC886 together...
There is a repository with source here: https://github.com/stm8stm8stm8/pfc886/blob/main/pwm08b.C (https://github.com/stm8stm8stm8/pfc886/blob/main/pwm08b.C)
Which according to the comment contains code for the "PFC886" IC which is also labeled "MF520".
After following the bread crumbs it turns out that PADAUK offers a special IC for brushless DC motors called the MF520:
http://www.padauk.com.tw/en/product/show.aspx?num=138&kind=44 (http://www.padauk.com.tw/en/product/show.aspx?num=138&kind=44)
In fact this seems to be an 8 core PADAUK with flash support :) 8)
EDIT:After some more digging I found a video of the "making of" the above source code:
https://www.bilibili.com/video/av712877080/ (https://www.bilibili.com/video/av712877080/)
The video contains some captures of the PFC886 datasheet (again all in chinese :-) )
EDIT2: In the video I was able to see that this IC has 512 byte of RAM :o
Interesting....
Code: [Select]tm1651_clk =0; tm1651_yanshi();
if(tm1651_a1.1){tm1651_dio =1;} else{tm1651_dio =0;}
tm1651_clk =1;tm1651_yanshi();
#include "extern.h"
tm1651_clk bit pb.0;
tm1651_dio bit pb.7;
byte tm1651_byte;
#define tm1651_send(b) { tm1652_byte = b; tm1651_send_byte(); }
void tm1651_start()
{
$ tm1651_clk out,high; //输出,高
$ tm1651_dio out,high;
.delay 100
tm1651_dio = 0;
.delay 100
}
void tm1651_send_byte()
{
byte bits = 8;
while (bits > 0) {
tm1651_clk = 0;
.delay 100
SR tm1651_byte$1
SWAPC tm1651_dio
tm1651_clk = 1;
.delay 100
bits--;
}
//等待确认
$ tm1651_dio in,pull;
tm1651_clk = 0;
while (tm1651_dio) {
nop;
}
tm1651_clk = 1;
$ tm1651_dio out,low;
}
void tm1651_stop()
{
tm1651_clk = 0;
tm1651_dio = 0;
.delay 100
tm1651_clk = 1;
.delay 100
tm1651_dio = 1;
.delay 100
}
void FPPA0 (void)
{
.ADJUST_IC SYSCLK=IHRC/4
$ tm1651_clk out,high; //输出,高
$ tm1651_dio out,high;
.delay 100
while (1) {
//写数据到显示寄存器,自动地址增加
tm1651_start();
tm1651_send(0b0100_0000);
tm1651_stop();
//设置地址00H
tm1651_start();
tm1651_send(0b1100_0000);
tm1651_send(0b1111_1111);
tm1651_send(0b0000_0000);
tm1651_send(0b0000_1111);
tm1651_send(0b1111_0000);
tm1651_stop();
//显示开,10/16
tm1651_start();
tm1651_send(0b1000_1011);
tm1651_stop();
}
}
I'm not sure, though, because I do not have any Padauk MCUs, or the Padauk Mini-C compiler; I am just guessing...@js_12345678_55AA
This is unpublished data.
E-mail To you.or** 如有业务或工程应用问题, 欢迎联络我司业务窗口 Kevin Liu : kevin_liu@padauk.com.tw **
new:MCS11
http://www.padauk.com.tw/cn/product/show.aspx?num=79&kind=85 (http://www.padauk.com.tw/cn/product/show.aspx?num=79&kind=85)
http://www.padauk.com.tw/upload/doc/MCS11_datasheet_v0%2020_20180420.pdf (http://www.padauk.com.tw/upload/doc/MCS11_datasheet_v0%2020_20180420.pdf)
I also added support for PFC151 and PFC161 ... which are *surprise surprise* ... the *SAME IC*.
Even original writer can write a PFC151 when a PFC161 program is loaded.
I wonder if the PFC161 is a PFC151 with the cacitive touch peripheral added vs. the PFC151 being a PFC161 where the capacitive touch peripheral failed test.
I'd like to try it out. cannot execute lack IDEDownload and install sdcc-4.1.0-x64-setup.exe (https://sourceforge.net/projects/sdcc/files/sdcc-win64/4.1.0/) first, and then codeblocks-20.03-setup.exe (https://www.codeblocks.org/downloads/binaries/). Then, Code::Blocks will be your IDE.
I'd like to try it out. cannot execute lack IDE
可以用仿真芯片吗? Can I use a simulation chip?
PCB Manufacturer Support only <20mb file
我想做一个烧录器,工厂只接受小于20mb文件,仅支持GERBER文件最大外尺寸10*10cm
烧录芯片的文件,现在芯片昂贵,有什么廉价芯片可以代换吗8051,stc,padauk?
PCB Manufacturer Support only <20mb fileYou have to use a micro that contains a DAC(NOT PWM) and have a sufficient amount of flash storage. Since the firmware is open source, you can port the firmware to any platform. (What's the license of these codes again?) Make sure you comply the source code license and disclose the source code when needed.
我想做一个烧录器,工厂只接受小于20mb文件,仅支持GERBER文件最大外尺寸10*10cm
烧录芯片的文件,现在芯片昂贵,有什么廉价芯片可以代换吗8051,stc,padauk?
Bus 003 Device 005: ID 0483:5740 STMicroelectronics Virtual COM Port
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 2 Communications
bDeviceSubClass 2 Abstract (modem)
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x0483 STMicroelectronics
idProduct 0x5740 Virtual COM Port
bcdDevice 2.00
iManufacturer 1 free-pdk.github.io
iProduct 2 Easy PDK Programmer
iSerial 3 1234567855AA
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 0x0043
bNumInterfaces 2
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xc0
Self Powered
MaxPower 100mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 2 Communications
bInterfaceSubClass 2 Abstract (modem)
bInterfaceProtocol 1 AT-commands (v.25ter)
iInterface 0
CDC Header:
bcdCDC 1.10
CDC Call Management:
bmCapabilities 0x00
bDataInterface 1
CDC ACM:
bmCapabilities 0x02
line coding and serial state
CDC Union:
bMasterInterface 0
bSlaveInterface 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82 EP 2 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0008 1x 8 bytes
bInterval 16
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 1
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 10 CDC Data
bInterfaceSubClass 0
bInterfaceProtocol 0
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x01 EP 1 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 0
can't get device qualifier: Resource temporarily unavailable
can't get debug descriptor: Resource temporarily unavailable
Device Status: 0x0001
Self Powered
[ 4797.390785] usb 3-10: new full-speed USB device number 5 using xhci_hcd
[ 4797.540232] usb 3-10: New USB device found, idVendor=0483, idProduct=5740, bcdDevice= 2.00
[ 4797.540237] usb 3-10: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 4797.540240] usb 3-10: Product: Easy PDK Programmer
[ 4797.540242] usb 3-10: Manufacturer: free-pdk.github.io
[ 4797.540244] usb 3-10: SerialNumber: 1234567855AA
[ 4797.611233] cdc_acm 3-10:1.0: ttyACM0: USB ACM device
[ 4797.611506] usbcore: registered new interface driver cdc_acm
[ 4797.611507] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
10*10 pcb 拼板已做好,我有j-link,怎么将文件下载到芯片STM32F072 supports USB-DFU. You don't need a jlink to flash the firmware. Just hold the button while plugging the USB and you should be in the DFU mode. 你不需要jlink来下载固件。STM32F072支持USB-DFU。
Does your account have permissions on /dev/ttyACM0? Often it's just a matter of making yourself a member of the group that the is the group owner of the try device. The group is often dialup or something like that and the device permissions are often 0664. Sometimes you need to install a udev rule to chgrp and chown the device upon detection when plugged in.
Searching programmer... found: /dev/ttyACM0
FREE-PDK EASY PROG - Hardware:1.2 Firmware:1.3 Protocol:1.3
Erasing IC... done.
Blank check IC... FPDK_ERROR: chip is not blank
Erasing IC... done.
Writing IC (81 words)... done.
Calibrating IC
* IHRC SYSCLK=1000000Hz @ 4.00V ... calibration result: 0Hz (0x00) out of range.
ERROR: Calibration failed
vdd: 4.93 vpp: 4.98 (vref= 3.30)
Late addition: my PFS173 chips are fine with the same setup and code - just the PFS154s that are suddenly not cooperative :(
QuoteLate addition: my PFS173 chips are fine with the same setup and code - just the PFS154s that are suddenly not cooperative :(
UPDATE: Just those few PFS154 chips. Have thrown them out and performed cleansing ceremony. Sorry for interruption, normal service resumed... :-+
Could you ERASE and then READ one of those "faulty" PFS154?
SDCC has an assembler. Just run SDCC with the appropriate options (IIRC it does the right thing if the file extension is that of assembler) and it will skip the C compile step. But you still need the startup code so you might want to retain the main() in C and call your assembly code. Or insert inline assembly code in the C code.
https://www.kuaishou.com/f/XTxuFXDaAWv1Wz (https://www.kuaishou.com/f/XTxuFXDaAWv1Wz)苏sir你还是发英语吧,用百度翻译一下都好啊。大家都会方便很多。
错误就是我应该选win版本就好了,需要.exe文件,软件根本就不会用,有使用指导么?太难了
https://www.kuaishou.com/f/X6Eb6Az5izrRf6m (https://www.kuaishou.com/f/X6Eb6Az5izrRf6m)
https://www.kuaishou.com/f/X6Eb6Az5izrRf6m (ftp://www.kuaishou.com/f/X6Eb6Az5izrRf6m)
软件是如何运行的?
How does the software work?
Recently, about a dozen new Padauk devices becam available at LCSC. Part numbers start with XDT, and I cannot find any datasheets anywhere. They are not mentioned on the Padauk website. The Padauk MINI-C software does not mention them either (there is one XDT device mentioned in there - the XDT0164, but that one isn't among the ones available at LCSC).
Does anyone have any idea about those devices?
Have you tried "easypdkprogtest" and measured all voltages?Hi Tim,
https://item.taobao.com/item.htm?spm=a230r.1.14.1.f1fc51c4BL5XXZ&id=649017329840&ns=1&abbucket=8#detail (https://item.taobao.com/item.htm?spm=a230r.1.14.1.f1fc51c4BL5XXZ&id=649017329840&ns=1&abbucket=8#detail)
https://item.taobao.com/item.htm?spm=a230r.1.14.1.f1fc51c4BL5XXZ&id=649017329840&ns=1&abbucket=8#detail (https://item.taobao.com/item.htm?spm=a230r.1.14.1.f1fc51c4BL5XXZ&id=649017329840&ns=1&abbucket=8#detail)
XDM4102 and XDM4104. Very interesting. 1.9 KW of program memory. According to the data from Mini-C, these are pdk14 devices. I guess they use the program memory space to map the 2KB EEPROM. That could allow these devices to update their own firmware in the field. It would be great to have datasheets.
P.S.: According to http://www.qy6.com/syjh/showbus8356932.html, (http://www.qy6.com/syjh/showbus8356932.html,) the XDM4105 is basically a PFS173 with EEPROM, the XDM4104 a PFS154 with extra EEPROM , the XDM4103 a PMS152 with extra EEPROM. But according to that page, the program memory has hte full size (so it looks more like two dies in one package). I guess we need to get and decap some to know.
@spth
mr.spth
I'm very interested in your open source the programmable hard devices .the operation instructions provided are not clear enough and
I'd like to request some additional documentation regarding the programmer's operation instructions. I'd also like to request the
latest Windows binary development release of the programmer software. annex: Test Chip compatible software
thank you
Su
I can't give it to you because I don't have an import and export certificate.You can buy it on Taobao.
https://item.taobao.com/item.htm?spm=a230r.1.14.1.359b404c0Msywi&id=650818241626&ns=1&abbucket=15#detail (https://item.taobao.com/item.htm?spm=a230r.1.14.1.359b404c0Msywi&id=650818241626&ns=1&abbucket=15#detail)
时间先生
我对你们的开源可编程硬件设备非常感兴趣。提供的操作说明不够清楚,我想要求提供一些关于程序员操作说明的附加文档。我还想申请最新的
Windows二进制开发版本的程序员软件。附件:测试芯片兼容软件
非常感谢。
su
由于我没有进出口凭证,无法给你.你可以在淘宝上购买.
https://item.taobao.com/item.htm?spm=a230r.1.14.1.359b404c0Msywi&id=650818241626&ns=1& (https://item.taobao.com/item.htm?spm=a230r.1.14.1.359b404c0Msywi&id=650818241626&ns=1&)
mew chip FT32F072C8AT7 LQFP48
https://www.fremontmicro.com/product/32%20bit%20mcu/arm%20core_1/20210316/1769.aspx (https://www.fremontmicro.com/product/32%20bit%20mcu/arm%20core_1/20210316/1769.aspx)
https://item.taobao.com/item.htm?spm=a1z09.2.0.0.df072e8dE6k6EJ&id=656098151997&_u=923hlh4e710 (https://item.taobao.com/item.htm?spm=a1z09.2.0.0.df072e8dE6k6EJ&id=656098151997&_u=923hlh4e710)
FT32F0 The file is too la.rge. What's your QQ number or email number.
This chip is good:
this is:
http://www.wch-ic.com (http://www.wch-ic.com)
http://www.wch.cn/products/category/5.html#data (http://www.wch.cn/products/category/5.html#data)
http://www.wch.cn/products/CH32V103.html? (http://www.wch.cn/products/CH32V103.html?)
padauk new mcu pfc460 26io sop28 tsop28Looks really interesting. If only they were available...
It's kinda quiet here...
I am currently trying to make audioplayer work on a PFS154.
However, the example does not work at all. After probing on the SPI line I found that not only the timing is a mess, the padauk is driving the MISO pin which it needs to be listening to instead of driving.
I am wondering this might be a compiler issue since I can't see any pin manipulation on the MISO pin.
uint8_t pdkspi_sendreceive(uint8_t s)
{
__asm
mov a, #8 ; loop 8 times
1$:
set0.io _ASMS(SPI_PORT), #(SPI_OUT_PIN) ; SPI-OUT = 0
t0sn _pdkspi_sendreceive_PARM_1, #7 ; s.7==0 ?
set1.io _ASMS(SPI_PORT), #(SPI_OUT_PIN) ; SPI-OUT = 1
set1.io _ASMS(SPI_PORT), #(SPI_CLK_PIN) ; SPI-CLK = 1
sl _pdkspi_sendreceive_PARM_1 ; s<<=1
t0sn.io _ASMS(SPI_PORT), #(SPI_IN_PIN) ; SPI-IN==0 ?
set1 _pdkspi_sendreceive_PARM_1, #0 ; s.0=1
set0.io _ASMS(SPI_PORT), #(SPI_CLK_PIN) ; SPI-CLK = 0
dzsn a ; loop--
goto 1$ ; loop again if>0
__endasm;
return s;
}
P.S: Unfortunately updating all existing projects right now is not a good idea, since the stable release version of SDCC does not support the new ".io" syntax :-(
#if __SDCC_REVISION >= 12558
mov.io-style asm code
#else
mov-style asm code
#endif
The PFS172/173 series seems to be discontinued and no longer available. The follow up is the PFS122/123 series which only seems to have a 12bit ADC instead of the 8bit ADC. At least the PFS122 is available right now:Those look particularly interesting - reading through the datasheet they have a "limited voltage programming mode" where it uses 5.0V volts only, which means a simpler programmer with no voltage shifting shenanigans could be doable.
https://lcsc.com/search?q=pfs122
Will there be a support in easypdkprog too?
The PFS172/173 series seems to be discontinued and no longer available. The follow up is the PFS122/123 series which only seems to have a 12bit ADC instead of the 8bit ADC. At least the PFS122 is available right now:Support can be added as soon as I can get hold of some ICs.
https://lcsc.com/search?q=pfs122
Will there be a support in easypdkprog too?
Those look particularly interesting - reading through the datasheet they have a "limited voltage programming mode" where it uses 5.0V volts only, which means a simpler programmer with no voltage shifting shenanigans could be doable.In the development branch you can see already some devices (e.g. PFC151/PFC161/PFC154/PFS172/PFC232) which use limited voltage programing mode.
Attachment NY8AO51H Timings
uint16_t nop_bin[16+1024] = {
0xF8E5, 0x269D, 0xE258, 0xBC49, 0x7987, 0xA2DE, 0x4B2F, 0x74E7, 0x5035, 0x3ACD, 0x75A6, 0x55F9, 0xB4DF, 0xA969, 0x74FA, 0x98F6,
0xB372, 0x3850, 0x28FF, 0xFAE5, 0x114A, 0x067A, 0x8AE0, 0x6E5D, 0x5B98, 0x10EE, 0xFC57, 0x018E, 0xAA34, 0x3EEB, 0xB9B1, 0x3FE8,
0x1FB8, 0xF516, 0x8C97, 0x3541, 0xAB8B, 0xAB60, 0xA9EB, 0x9F77, 0x2C11, 0xFBBA, 0x7E49, 0x4A19, 0xB4F9, 0xF44C, 0xFF1D, 0x5725,
0xBB1C, 0x34D9, 0x962D, 0x3EEC, 0x81A8, 0x2291, 0xFD9C, 0x819C, 0xBB93, 0x36F1, 0xD957, 0xE6D3, 0x79BF, 0x5024, 0x30B9, 0xEDE4,
0x1606, 0x17D2, 0x6707, 0x4965, 0x6AFC, 0xA08F, 0xB60B, 0x9F51, 0x7134, 0x705D, 0xB19A, 0x4277, 0xB870, 0x4A9E, 0x3B14, 0xC7C7,
0x9FF7, 0x43A5, 0x79EC, 0xDEE7, 0xA7B7, 0x0791, 0x1AC1, 0x5217, 0xD55C, 0xBFF9, 0x0B5B, 0xEF6D, 0x9B7B, 0xBBB4, 0x4C9D, 0x2C93,
0x1DE9, 0x0832, 0x6721, 0x1440, 0xE11B, 0x6F5C, 0xBE65, 0x93D8, 0xCFE6, 0xB454, 0x2178, 0x669C, 0xCF0C, 0xA55F, 0xDB1F, 0xE1D8,
0xBAF7, 0xA4F8, 0xAA67, 0xB028, 0x2EBF, 0xD59D, 0x137F, 0xB0D3, 0x3ECC, 0xC3DD, 0xCA2C, 0xE482, 0x849B, 0xBB92, 0x11B8, 0xA774,
0xD23A, 0x005C, 0x6BA8, 0xAA92, 0x2512, 0xFFBE, 0x9A8E, 0xE4A4, 0x2027, 0x545F, 0x0767, 0x439C, 0x2851, 0x76D4, 0xB5D0, 0x68D0,
0x68FB, 0xAD46, 0x48A3, 0x5BB8, 0x529B, 0x14EA, 0x1890, 0xAF33, 0x3EEA, 0x9EF8, 0x41CB, 0x2B51, 0x8CF5, 0xB71B, 0xAF6A, 0x637D,
0x42D8, 0x24B7, 0x1CD4, 0x4553, 0xC519, 0xD9A1, 0xBF8E, 0x03F9, 0xF3AC, 0x3A90, 0x8E6F, 0x9190, 0x21EF, 0x9410, 0x5E40, 0x14F4,
0xA98C, 0xA6A9, 0x5743, 0x5B9E, 0x0FBE, 0x9F0D, 0xD743, 0xA75D, 0x3263, 0x202A, 0x85C2, 0xBBB3, 0xA81E, 0xC067, 0x40AB, 0x8376,
0x64C7, 0x01B7, 0xFB89, 0x96D8, 0xABD6, 0x50A9, 0x6D82, 0x0A47, 0x1168, 0xD100, 0xF24B, 0x50E7, 0x2A00, 0x8BF0, 0x5E66, 0x49D1,
0x226B, 0x697A, 0x5F2D, 0x5717, 0xB16C, 0x5B04, 0x47A1, 0x83B6, 0x451F, 0xCFEB, 0x65C9, 0x9DAC, 0x8D1E, 0x273A, 0x9320, 0xEDB9,
0xEDCF, 0xD3BB, 0xF237, 0x741C, 0x4046, 0x2C8D, 0xACF5, 0x01A8, 0x0E88, 0xD126, 0xAF6E, 0xDB00, 0xE5D3, 0x839E, 0x52EF, 0xF703,
0xE662, 0xF998, 0x7BC6, 0x206B, 0x5EAD, 0xBB0F, 0x61BE, 0xA6B6, 0xA242, 0x1C60, 0x0B06, 0x14A4, 0x5F12, 0x2E84, 0x71E4, 0x0629,
0x91EB, 0x12CC, 0xF9D8, 0x6BFC, 0x4060, 0x71A8, 0x2712, 0xCE7B, 0x06E6, 0xDDAF, 0x11BC, 0x1F09, 0x7531, 0xA775, 0x2593, 0x18C2,
0x0669, 0xDF87, 0x5EC6, 0xC736, 0x8D26, 0xD5C0, 0xE8B6, 0x74BA, 0xABFC, 0xFEA4, 0xE096, 0x6880, 0x9E65, 0x256B, 0x6E04, 0x060F,
0xCCCE, 0x992B, 0x360B, 0x6392, 0x4CE9, 0xCF7A, 0xE31B, 0x5E99, 0x220D, 0xAAD3, 0xFE7D, 0xFF02, 0x532E, 0x8275, 0xC2CE, 0xCB49,
0x68A6, 0x568F, 0x8CCA, 0xCE88, 0x6FE2, 0x3E50, 0x9492, 0xB5CD, 0xA013, 0xE144, 0xE0B0, 0x35A5, 0x1582, 0xEAB8, 0x666A, 0x0A86,
0x721C, 0x5D22, 0xA6E9, 0x4779, 0x3B95, 0x20BB, 0x0310, 0x7886, 0x070D, 0x4D8E, 0x2DF6, 0x91CD, 0xDA26, 0x5079, 0xCB70, 0x298D,
0x8336, 0x2AAB, 0x4DBD, 0xC567, 0x7002, 0x3E76, 0xC9B7, 0x3E2A, 0x6FC0, 0xE92A, 0xEC39, 0x8B77, 0xD18B, 0x7A5A, 0x4281, 0x7DFA,
0x9DDD, 0xBD29, 0x80F6, 0x6279, 0xDCC8, 0xF330, 0x6DDF, 0xF18E, 0xD501, 0x4430, 0xCF32, 0x7A5D, 0xA602, 0x910E, 0xC09F, 0x366D,
0x8310, 0x778E, 0xC65A, 0x0AB4, 0x786C, 0x32FF, 0x7765, 0xFA23, 0xFF22, 0xCDC1, 0x9B45, 0x64B6, 0x3180, 0x5C45, 0x6781, 0x9AA7,
0x4E56, 0xD3E6, 0x09FE, 0xB075, 0xD576, 0x11F4, 0x864F, 0x8DAA, 0x1476, 0x4FDF, 0xD0D2, 0x7A7B, 0xFB27, 0x1AE9, 0x0F4C, 0x3E03,
0x8F99, 0xC95C, 0x0253, 0x9A56, 0x5C87, 0x4583, 0x98A4, 0x1A28, 0xD93D, 0xE8C1, 0x7C18, 0xB73D, 0x5F4F, 0xD54D, 0xB58D, 0x9319,
0xAC92, 0x3876, 0x75DA, 0x7102, 0xDE99, 0x0E14, 0x8669, 0xD08F, 0x9F91, 0x800C, 0xD8BC, 0x76F2, 0x45F5, 0xDEE0, 0x9FAE, 0x1AE8,
0xF8E5, 0x269D, 0xE258, 0xBC49, 0x7987, 0xA2DE, 0x4B2F, 0x74E7, 0x5035, 0x3ACD, 0x75A6, 0x55F9, 0xB4DF, 0xA969, 0x74FA, 0x98F6,
0xB372, 0x3850, 0x28FF, 0xFAE5, 0x114A, 0x067A, 0x8AE0, 0x6E5D, 0x5B98, 0x10EE, 0xFC57, 0x018E, 0xAA34, 0x3EEB, 0xB9B1, 0x3FE8,
0x1FB8, 0xF516, 0x8C97, 0x3541, 0xAB8B, 0xAB60, 0xA9EB, 0x9F77, 0x2C11, 0xFBBA, 0x7E49, 0x4A19, 0xB4F9, 0xF44C, 0xFF1D, 0x5725,
0xBB1C, 0x34D9, 0x962D, 0x3EEC, 0x81A8, 0x2291, 0xFD9C, 0x819C, 0xBB93, 0x36F1, 0xD957, 0xE6D3, 0x79BF, 0x5024, 0x30B9, 0xEDE4,
0x1606, 0x17D2, 0x6707, 0x4965, 0x6AFC, 0xA08F, 0xB60B, 0x9F51, 0x7134, 0x705D, 0xB19A, 0x4277, 0xB870, 0x4A9E, 0x3B14, 0xC7C7,
0x9FF7, 0x43A5, 0x79EC, 0xDEE7, 0xA7B7, 0x0791, 0x1AC1, 0x5217, 0xEC2E, 0x16DE, 0x1A38, 0xB0BC, 0x7C78, 0x2BB1, 0x16F2, 0xECB8,
0x743E, 0x07AD, 0xCDE1, 0x63C8, 0x55B2, 0x5621, 0xFAE4, 0x0666, 0xF694, 0x1D73, 0x301B, 0x394D, 0x280F, 0x355A, 0x8170, 0x21F3,
0xD320, 0xAB67, 0x00A7, 0xC7A0, 0x9A16, 0xECE0, 0x57FE, 0x256D, 0x07BE, 0x6AFA, 0xDB4F, 0xBB53, 0x6398, 0x2B97, 0x4BD7, 0x675F,
0xBBED, 0x0FC3, 0xC168, 0xDD1A, 0x91BB, 0xC6C3, 0xDE0F, 0x711A, 0x1955, 0xFD78, 0x1604, 0x1C4D, 0xCF52, 0xE6D1, 0xEFBF, 0xA8FB,
0x012C, 0xA2D9, 0xE263, 0x2C30, 0xE632, 0x2D97, 0x5C11, 0x3A8D, 0x0798, 0x37DF, 0x50A8, 0x7480, 0x6BF6, 0x271E, 0xF505, 0xA356,
0x2B0F, 0x2B28, 0xB614, 0x32DB, 0x71B0, 0xE0DC, 0xFB0F, 0x9647, 0xCADE, 0x93B7, 0x9F0C, 0xCE41, 0xC6EC, 0x0415, 0x042F, 0xD4DF,
0xC05B, 0xA936, 0xFD83, 0x2C16, 0xBB17, 0xA670, 0x93C2, 0x32E3, 0x0B11, 0x890D, 0x94A1, 0xE462, 0x4F1D, 0x5062, 0x1AC4, 0x435D,
0x0D10, 0x0E28, 0x5149, 0xE150, 0x1F7F, 0x69D4, 0x2903, 0x9FF9, 0x281A, 0x7827, 0xE328, 0x0F36, 0xCD03, 0x1BF5, 0x0409, 0x89FA,
0x4BBC, 0x66E5, 0xF5ED, 0x209F, 0x05C5, 0x6279, 0x0320, 0x1608, 0x7C6D, 0x66CC, 0x74AA, 0xC27D, 0x6A1D, 0xB73F, 0xC94F, 0x2D92,
0x8418, 0xDC24, 0x58F7, 0x0394, 0xF4EF, 0x15F0, 0xE874, 0x9416, 0x37FA, 0x7801, 0xBE0D, 0x84D1, 0x02D0, 0x139B, 0x0880, 0x3728,
0x8FB5, 0xF607, 0xD106, 0x57E3, 0xEA04, 0x8272, 0x253F, 0x3308, 0x9B30, 0xB547, 0x1A65, 0x4B75, 0xB811, 0xBE81, 0x2B8B, 0xC602,
0xF83C, 0x1D53, 0x5318, 0x1C74, 0xF4C9, 0x48D5, 0x6393, 0x5BC5, 0x3F94, 0x7488, 0x00DF, 0x40D8, 0x9232, 0x3770, 0x7FFC, 0xD8E9,
0x6FBE, 0xD018, 0xF406, 0xB0BE, 0x398F, 0xECBD, 0xAC37, 0xE104, 0x928E, 0x5783, 0xF1F5, 0x3751, 0x7966, 0xB56E, 0x346B, 0xC624,
0xA519, 0x96B4, 0x9CCB, 0x141A, 0xF840, 0xF607, 0xA79A, 0xCB27, 0x1B7F, 0x03F4, 0xEF1E, 0xA0D3, 0xB42D, 0x1270, 0x98A1, 0x0B62,
0x0171, 0x5910, 0x260A, 0xB900, 0xDB4B, 0x072D, 0xD013, 0x2073, 0x9961, 0x4863, 0xF1D3, 0x6A74, 0xF281, 0x7ABD, 0x3C05, 0xCAAD,
0x1BCB, 0x52BD, 0x0C29, 0x30F1, 0x8F3C, 0x19C6, 0x4791, 0xED38, 0x3E7F, 0xE4A9, 0x3C95, 0xCE1C, 0x3D25, 0xC07C, 0x911F, 0xE9A6,
0xEAE1, 0x2534, 0xE77D, 0xB2EF, 0xC4AB, 0x070B, 0x8D36, 0xAB94, 0x56B2, 0x400D, 0xFD5A, 0xD4A6, 0x3688, 0xEA5F, 0x18EE, 0xBDD1,
0xF40A, 0xB2B6, 0x2A36, 0x15F1, 0x6861, 0xCA4D, 0x295E, 0x6430, 0xEC73, 0xED17, 0xDE51, 0x258C, 0x4101, 0x010B, 0x9AF0, 0xF646,
0xEAC7, 0x7811, 0x6C9A, 0x7D3C, 0xCCC5, 0x0B82, 0x33E4, 0x6F9D, 0xC650, 0x64E6, 0x8A26, 0x3B67, 0xD683, 0xCC40, 0x3DEE, 0x5A8C,
0x2781, 0xDC79, 0xA33E, 0xC7FD, 0x61DF, 0x2889, 0xC2CE, 0x1814, 0x2D04, 0xE6F8, 0xC1B1, 0x25AA, 0x1C24, 0x8AEC, 0x5523, 0xFE28,
0xE64E, 0xC6C3, 0xA893, 0xEDDE, 0xE82E, 0x7CFE, 0xDC25, 0x8F96, 0xE04F, 0x41E6, 0x6D7B, 0xE8EC, 0xB84C, 0x4548, 0xEFE2, 0x5332,
0xC545, 0x37E9, 0xDF1A, 0x068A, 0x6A30, 0x3769, 0xC2E8, 0x4531, 0xA6E3, 0x292B, 0xC9DF, 0x2923, 0xA2F6, 0x4EE5, 0xC5C1, 0xDAC3,
0x9132, 0x2902, 0x4898, 0xCBC1, 0xCD2E, 0x9BA3, 0x0FAE, 0xE159, 0x6947, 0x93EA, 0x64C5, 0x0A28, 0x53DC, 0x396C, 0x2E95, 0x58DD,
0xDAA5, 0x37CF, 0x823F, 0x8D6D, 0xA5E3, 0x3F07, 0xCE61, 0xFBE3, 0x62EA, 0xB9C9, 0xED34, 0x5E5F, 0x4D37, 0xAEEE, 0xE3DE, 0xFFC3,
0x766F, 0xFA89, 0x2657, 0x42C9, 0x1F22, 0x921D, 0xED6A, 0x0AC9, 0x1563, 0x529D, 0x6F2A, 0x15C8, 0x53FA, 0x6449, 0xA572, 0x970E,
0xD2CB, 0x3B46, 0x3CED, 0x4964, 0x3501, 0x1BEC, 0xB91D, 0x1422, 0x82E1, 0x9FD6, 0xC834, 0xB902, 0x9EBC, 0xC021, 0x6AD6, 0x2DCF,
0x7FD1, 0x184D, 0xCDC7, 0x3EED, 0xDE55, 0x99F2, 0xF28A, 0x0AEF, 0x4846, 0xD97A, 0xA0F9, 0x1DA6, 0x5F73, 0xDA9B, 0x617B, 0x07EC,
0xF620, 0x4C3A, 0xD32C, 0xA96F, 0x131E, 0x3EEC, 0x5E40, 0xC7A9, 0xEC2E, 0x16DE, 0x1A38, 0xB0BC, 0x7C78, 0x2BB1, 0x16F2, 0xECB8,
0x743E, 0x07AD, 0xCDE1, 0x63C8, 0x55B2, 0x5621, 0xFAE4, 0x0666, 0xF694, 0x1D73, 0x301B, 0x394D, 0x280F, 0x355A, 0x8170, 0x21F3,
0xD320, 0xAB67, 0x00A7, 0xC7A0, 0x9A16, 0xECE0, 0x57FE, 0x256D, 0x07BE, 0x6AFA, 0xDB4F, 0xBB53, 0x6398, 0x2B97, 0x4BD7, 0x675F,
0xBBED, 0x0FC3, 0xC168, 0xDD1A, 0x91BB, 0xC6C3, 0xDE0F, 0x711A, 0x1955, 0xFD78, 0x1604, 0x1C4D, 0xCF52, 0xE6D1, 0xEFBF, 0xA8FB,
0x012C, 0xA2D9, 0xE263, 0x2C30, 0xE632, 0x2D97, 0x5C11, 0x3A8D, 0x0798, 0x37DF, 0x50A8, 0x7480, 0x6BF6, 0x271E, 0xF505, 0xA356,
0x2B0F, 0x2B28, 0xB614, 0x32DB, 0x71B0, 0xE0DC, 0xFB0F, 0x9647, 0xCADE, 0x93B7, 0x9F0C, 0xCE41, 0xC6EC, 0x0415, 0x042F, 0xDADF
};
void ny_dec(uint16_t *data, uint16_t cnt){
uint16_t i, t[1024+16];
uint8_t a, b;
for(i=0; i<cnt; i++) t[1023+16-i] = data[i] ^ nop_bin[i];
for(i=0; i<cnt; i++){
a = t[i];
b = t[i]>>8;
if(i>=0x208){
b = (b >> 2) | (b << (8-2));
a = (a >> 6) | (a << (8-6));
}
else{
a = (a >> 3) | (a << (8-3));
b = (b >> 5) | (b << (8-5));
}
data[i] = a<<8 | b;
data[i] &= 0x3FFF;
}
}
(https://files.catbox.moe/ua6x4g.png)Attachment NY8AO51H Timings
Thank You.
Now I have working write and read :)
I made BIN decoder.
Start decoding from configuration words (0x76 in BIN; "xdat", 4B len, 32B configuration words, 2048B data....)
Output: 1024W data, 16W config.
"ny_dec(buffer, 16+1024);"Code: [Select]uint16_t nop_bin[16+1024] = {
0xF8E5, 0x269D, 0xE258, 0xBC49, 0x7987, 0xA2DE, 0x4B2F, 0x74E7, 0x5035, 0x3ACD, 0x75A6, 0x55F9, 0xB4DF, 0xA969, 0x74FA, 0x98F6,
0xB372, 0x3850, 0x28FF, 0xFAE5, 0x114A, 0x067A, 0x8AE0, 0x6E5D, 0x5B98, 0x10EE, 0xFC57, 0x018E, 0xAA34, 0x3EEB, 0xB9B1, 0x3FE8,
0x1FB8, 0xF516, 0x8C97, 0x3541, 0xAB8B, 0xAB60, 0xA9EB, 0x9F77, 0x2C11, 0xFBBA, 0x7E49, 0x4A19, 0xB4F9, 0xF44C, 0xFF1D, 0x5725,
0xBB1C, 0x34D9, 0x962D, 0x3EEC, 0x81A8, 0x2291, 0xFD9C, 0x819C, 0xBB93, 0x36F1, 0xD957, 0xE6D3, 0x79BF, 0x5024, 0x30B9, 0xEDE4,
0x1606, 0x17D2, 0x6707, 0x4965, 0x6AFC, 0xA08F, 0xB60B, 0x9F51, 0x7134, 0x705D, 0xB19A, 0x4277, 0xB870, 0x4A9E, 0x3B14, 0xC7C7,
0x9FF7, 0x43A5, 0x79EC, 0xDEE7, 0xA7B7, 0x0791, 0x1AC1, 0x5217, 0xD55C, 0xBFF9, 0x0B5B, 0xEF6D, 0x9B7B, 0xBBB4, 0x4C9D, 0x2C93,
0x1DE9, 0x0832, 0x6721, 0x1440, 0xE11B, 0x6F5C, 0xBE65, 0x93D8, 0xCFE6, 0xB454, 0x2178, 0x669C, 0xCF0C, 0xA55F, 0xDB1F, 0xE1D8,
0xBAF7, 0xA4F8, 0xAA67, 0xB028, 0x2EBF, 0xD59D, 0x137F, 0xB0D3, 0x3ECC, 0xC3DD, 0xCA2C, 0xE482, 0x849B, 0xBB92, 0x11B8, 0xA774,
0xD23A, 0x005C, 0x6BA8, 0xAA92, 0x2512, 0xFFBE, 0x9A8E, 0xE4A4, 0x2027, 0x545F, 0x0767, 0x439C, 0x2851, 0x76D4, 0xB5D0, 0x68D0,
0x68FB, 0xAD46, 0x48A3, 0x5BB8, 0x529B, 0x14EA, 0x1890, 0xAF33, 0x3EEA, 0x9EF8, 0x41CB, 0x2B51, 0x8CF5, 0xB71B, 0xAF6A, 0x637D,
0x42D8, 0x24B7, 0x1CD4, 0x4553, 0xC519, 0xD9A1, 0xBF8E, 0x03F9, 0xF3AC, 0x3A90, 0x8E6F, 0x9190, 0x21EF, 0x9410, 0x5E40, 0x14F4,
0xA98C, 0xA6A9, 0x5743, 0x5B9E, 0x0FBE, 0x9F0D, 0xD743, 0xA75D, 0x3263, 0x202A, 0x85C2, 0xBBB3, 0xA81E, 0xC067, 0x40AB, 0x8376,
0x64C7, 0x01B7, 0xFB89, 0x96D8, 0xABD6, 0x50A9, 0x6D82, 0x0A47, 0x1168, 0xD100, 0xF24B, 0x50E7, 0x2A00, 0x8BF0, 0x5E66, 0x49D1,
0x226B, 0x697A, 0x5F2D, 0x5717, 0xB16C, 0x5B04, 0x47A1, 0x83B6, 0x451F, 0xCFEB, 0x65C9, 0x9DAC, 0x8D1E, 0x273A, 0x9320, 0xEDB9,
0xEDCF, 0xD3BB, 0xF237, 0x741C, 0x4046, 0x2C8D, 0xACF5, 0x01A8, 0x0E88, 0xD126, 0xAF6E, 0xDB00, 0xE5D3, 0x839E, 0x52EF, 0xF703,
0xE662, 0xF998, 0x7BC6, 0x206B, 0x5EAD, 0xBB0F, 0x61BE, 0xA6B6, 0xA242, 0x1C60, 0x0B06, 0x14A4, 0x5F12, 0x2E84, 0x71E4, 0x0629,
0x91EB, 0x12CC, 0xF9D8, 0x6BFC, 0x4060, 0x71A8, 0x2712, 0xCE7B, 0x06E6, 0xDDAF, 0x11BC, 0x1F09, 0x7531, 0xA775, 0x2593, 0x18C2,
0x0669, 0xDF87, 0x5EC6, 0xC736, 0x8D26, 0xD5C0, 0xE8B6, 0x74BA, 0xABFC, 0xFEA4, 0xE096, 0x6880, 0x9E65, 0x256B, 0x6E04, 0x060F,
0xCCCE, 0x992B, 0x360B, 0x6392, 0x4CE9, 0xCF7A, 0xE31B, 0x5E99, 0x220D, 0xAAD3, 0xFE7D, 0xFF02, 0x532E, 0x8275, 0xC2CE, 0xCB49,
0x68A6, 0x568F, 0x8CCA, 0xCE88, 0x6FE2, 0x3E50, 0x9492, 0xB5CD, 0xA013, 0xE144, 0xE0B0, 0x35A5, 0x1582, 0xEAB8, 0x666A, 0x0A86,
0x721C, 0x5D22, 0xA6E9, 0x4779, 0x3B95, 0x20BB, 0x0310, 0x7886, 0x070D, 0x4D8E, 0x2DF6, 0x91CD, 0xDA26, 0x5079, 0xCB70, 0x298D,
0x8336, 0x2AAB, 0x4DBD, 0xC567, 0x7002, 0x3E76, 0xC9B7, 0x3E2A, 0x6FC0, 0xE92A, 0xEC39, 0x8B77, 0xD18B, 0x7A5A, 0x4281, 0x7DFA,
0x9DDD, 0xBD29, 0x80F6, 0x6279, 0xDCC8, 0xF330, 0x6DDF, 0xF18E, 0xD501, 0x4430, 0xCF32, 0x7A5D, 0xA602, 0x910E, 0xC09F, 0x366D,
0x8310, 0x778E, 0xC65A, 0x0AB4, 0x786C, 0x32FF, 0x7765, 0xFA23, 0xFF22, 0xCDC1, 0x9B45, 0x64B6, 0x3180, 0x5C45, 0x6781, 0x9AA7,
0x4E56, 0xD3E6, 0x09FE, 0xB075, 0xD576, 0x11F4, 0x864F, 0x8DAA, 0x1476, 0x4FDF, 0xD0D2, 0x7A7B, 0xFB27, 0x1AE9, 0x0F4C, 0x3E03,
0x8F99, 0xC95C, 0x0253, 0x9A56, 0x5C87, 0x4583, 0x98A4, 0x1A28, 0xD93D, 0xE8C1, 0x7C18, 0xB73D, 0x5F4F, 0xD54D, 0xB58D, 0x9319,
0xAC92, 0x3876, 0x75DA, 0x7102, 0xDE99, 0x0E14, 0x8669, 0xD08F, 0x9F91, 0x800C, 0xD8BC, 0x76F2, 0x45F5, 0xDEE0, 0x9FAE, 0x1AE8,
0xF8E5, 0x269D, 0xE258, 0xBC49, 0x7987, 0xA2DE, 0x4B2F, 0x74E7, 0x5035, 0x3ACD, 0x75A6, 0x55F9, 0xB4DF, 0xA969, 0x74FA, 0x98F6,
0xB372, 0x3850, 0x28FF, 0xFAE5, 0x114A, 0x067A, 0x8AE0, 0x6E5D, 0x5B98, 0x10EE, 0xFC57, 0x018E, 0xAA34, 0x3EEB, 0xB9B1, 0x3FE8,
0x1FB8, 0xF516, 0x8C97, 0x3541, 0xAB8B, 0xAB60, 0xA9EB, 0x9F77, 0x2C11, 0xFBBA, 0x7E49, 0x4A19, 0xB4F9, 0xF44C, 0xFF1D, 0x5725,
0xBB1C, 0x34D9, 0x962D, 0x3EEC, 0x81A8, 0x2291, 0xFD9C, 0x819C, 0xBB93, 0x36F1, 0xD957, 0xE6D3, 0x79BF, 0x5024, 0x30B9, 0xEDE4,
0x1606, 0x17D2, 0x6707, 0x4965, 0x6AFC, 0xA08F, 0xB60B, 0x9F51, 0x7134, 0x705D, 0xB19A, 0x4277, 0xB870, 0x4A9E, 0x3B14, 0xC7C7,
0x9FF7, 0x43A5, 0x79EC, 0xDEE7, 0xA7B7, 0x0791, 0x1AC1, 0x5217, 0xEC2E, 0x16DE, 0x1A38, 0xB0BC, 0x7C78, 0x2BB1, 0x16F2, 0xECB8,
0x743E, 0x07AD, 0xCDE1, 0x63C8, 0x55B2, 0x5621, 0xFAE4, 0x0666, 0xF694, 0x1D73, 0x301B, 0x394D, 0x280F, 0x355A, 0x8170, 0x21F3,
0xD320, 0xAB67, 0x00A7, 0xC7A0, 0x9A16, 0xECE0, 0x57FE, 0x256D, 0x07BE, 0x6AFA, 0xDB4F, 0xBB53, 0x6398, 0x2B97, 0x4BD7, 0x675F,
0xBBED, 0x0FC3, 0xC168, 0xDD1A, 0x91BB, 0xC6C3, 0xDE0F, 0x711A, 0x1955, 0xFD78, 0x1604, 0x1C4D, 0xCF52, 0xE6D1, 0xEFBF, 0xA8FB,
0x012C, 0xA2D9, 0xE263, 0x2C30, 0xE632, 0x2D97, 0x5C11, 0x3A8D, 0x0798, 0x37DF, 0x50A8, 0x7480, 0x6BF6, 0x271E, 0xF505, 0xA356,
0x2B0F, 0x2B28, 0xB614, 0x32DB, 0x71B0, 0xE0DC, 0xFB0F, 0x9647, 0xCADE, 0x93B7, 0x9F0C, 0xCE41, 0xC6EC, 0x0415, 0x042F, 0xD4DF,
0xC05B, 0xA936, 0xFD83, 0x2C16, 0xBB17, 0xA670, 0x93C2, 0x32E3, 0x0B11, 0x890D, 0x94A1, 0xE462, 0x4F1D, 0x5062, 0x1AC4, 0x435D,
0x0D10, 0x0E28, 0x5149, 0xE150, 0x1F7F, 0x69D4, 0x2903, 0x9FF9, 0x281A, 0x7827, 0xE328, 0x0F36, 0xCD03, 0x1BF5, 0x0409, 0x89FA,
0x4BBC, 0x66E5, 0xF5ED, 0x209F, 0x05C5, 0x6279, 0x0320, 0x1608, 0x7C6D, 0x66CC, 0x74AA, 0xC27D, 0x6A1D, 0xB73F, 0xC94F, 0x2D92,
0x8418, 0xDC24, 0x58F7, 0x0394, 0xF4EF, 0x15F0, 0xE874, 0x9416, 0x37FA, 0x7801, 0xBE0D, 0x84D1, 0x02D0, 0x139B, 0x0880, 0x3728,
0x8FB5, 0xF607, 0xD106, 0x57E3, 0xEA04, 0x8272, 0x253F, 0x3308, 0x9B30, 0xB547, 0x1A65, 0x4B75, 0xB811, 0xBE81, 0x2B8B, 0xC602,
0xF83C, 0x1D53, 0x5318, 0x1C74, 0xF4C9, 0x48D5, 0x6393, 0x5BC5, 0x3F94, 0x7488, 0x00DF, 0x40D8, 0x9232, 0x3770, 0x7FFC, 0xD8E9,
0x6FBE, 0xD018, 0xF406, 0xB0BE, 0x398F, 0xECBD, 0xAC37, 0xE104, 0x928E, 0x5783, 0xF1F5, 0x3751, 0x7966, 0xB56E, 0x346B, 0xC624,
0xA519, 0x96B4, 0x9CCB, 0x141A, 0xF840, 0xF607, 0xA79A, 0xCB27, 0x1B7F, 0x03F4, 0xEF1E, 0xA0D3, 0xB42D, 0x1270, 0x98A1, 0x0B62,
0x0171, 0x5910, 0x260A, 0xB900, 0xDB4B, 0x072D, 0xD013, 0x2073, 0x9961, 0x4863, 0xF1D3, 0x6A74, 0xF281, 0x7ABD, 0x3C05, 0xCAAD,
0x1BCB, 0x52BD, 0x0C29, 0x30F1, 0x8F3C, 0x19C6, 0x4791, 0xED38, 0x3E7F, 0xE4A9, 0x3C95, 0xCE1C, 0x3D25, 0xC07C, 0x911F, 0xE9A6,
0xEAE1, 0x2534, 0xE77D, 0xB2EF, 0xC4AB, 0x070B, 0x8D36, 0xAB94, 0x56B2, 0x400D, 0xFD5A, 0xD4A6, 0x3688, 0xEA5F, 0x18EE, 0xBDD1,
0xF40A, 0xB2B6, 0x2A36, 0x15F1, 0x6861, 0xCA4D, 0x295E, 0x6430, 0xEC73, 0xED17, 0xDE51, 0x258C, 0x4101, 0x010B, 0x9AF0, 0xF646,
0xEAC7, 0x7811, 0x6C9A, 0x7D3C, 0xCCC5, 0x0B82, 0x33E4, 0x6F9D, 0xC650, 0x64E6, 0x8A26, 0x3B67, 0xD683, 0xCC40, 0x3DEE, 0x5A8C,
0x2781, 0xDC79, 0xA33E, 0xC7FD, 0x61DF, 0x2889, 0xC2CE, 0x1814, 0x2D04, 0xE6F8, 0xC1B1, 0x25AA, 0x1C24, 0x8AEC, 0x5523, 0xFE28,
0xE64E, 0xC6C3, 0xA893, 0xEDDE, 0xE82E, 0x7CFE, 0xDC25, 0x8F96, 0xE04F, 0x41E6, 0x6D7B, 0xE8EC, 0xB84C, 0x4548, 0xEFE2, 0x5332,
0xC545, 0x37E9, 0xDF1A, 0x068A, 0x6A30, 0x3769, 0xC2E8, 0x4531, 0xA6E3, 0x292B, 0xC9DF, 0x2923, 0xA2F6, 0x4EE5, 0xC5C1, 0xDAC3,
0x9132, 0x2902, 0x4898, 0xCBC1, 0xCD2E, 0x9BA3, 0x0FAE, 0xE159, 0x6947, 0x93EA, 0x64C5, 0x0A28, 0x53DC, 0x396C, 0x2E95, 0x58DD,
0xDAA5, 0x37CF, 0x823F, 0x8D6D, 0xA5E3, 0x3F07, 0xCE61, 0xFBE3, 0x62EA, 0xB9C9, 0xED34, 0x5E5F, 0x4D37, 0xAEEE, 0xE3DE, 0xFFC3,
0x766F, 0xFA89, 0x2657, 0x42C9, 0x1F22, 0x921D, 0xED6A, 0x0AC9, 0x1563, 0x529D, 0x6F2A, 0x15C8, 0x53FA, 0x6449, 0xA572, 0x970E,
0xD2CB, 0x3B46, 0x3CED, 0x4964, 0x3501, 0x1BEC, 0xB91D, 0x1422, 0x82E1, 0x9FD6, 0xC834, 0xB902, 0x9EBC, 0xC021, 0x6AD6, 0x2DCF,
0x7FD1, 0x184D, 0xCDC7, 0x3EED, 0xDE55, 0x99F2, 0xF28A, 0x0AEF, 0x4846, 0xD97A, 0xA0F9, 0x1DA6, 0x5F73, 0xDA9B, 0x617B, 0x07EC,
0xF620, 0x4C3A, 0xD32C, 0xA96F, 0x131E, 0x3EEC, 0x5E40, 0xC7A9, 0xEC2E, 0x16DE, 0x1A38, 0xB0BC, 0x7C78, 0x2BB1, 0x16F2, 0xECB8,
0x743E, 0x07AD, 0xCDE1, 0x63C8, 0x55B2, 0x5621, 0xFAE4, 0x0666, 0xF694, 0x1D73, 0x301B, 0x394D, 0x280F, 0x355A, 0x8170, 0x21F3,
0xD320, 0xAB67, 0x00A7, 0xC7A0, 0x9A16, 0xECE0, 0x57FE, 0x256D, 0x07BE, 0x6AFA, 0xDB4F, 0xBB53, 0x6398, 0x2B97, 0x4BD7, 0x675F,
0xBBED, 0x0FC3, 0xC168, 0xDD1A, 0x91BB, 0xC6C3, 0xDE0F, 0x711A, 0x1955, 0xFD78, 0x1604, 0x1C4D, 0xCF52, 0xE6D1, 0xEFBF, 0xA8FB,
0x012C, 0xA2D9, 0xE263, 0x2C30, 0xE632, 0x2D97, 0x5C11, 0x3A8D, 0x0798, 0x37DF, 0x50A8, 0x7480, 0x6BF6, 0x271E, 0xF505, 0xA356,
0x2B0F, 0x2B28, 0xB614, 0x32DB, 0x71B0, 0xE0DC, 0xFB0F, 0x9647, 0xCADE, 0x93B7, 0x9F0C, 0xCE41, 0xC6EC, 0x0415, 0x042F, 0xDADF
};
void ny_dec(uint16_t *data, uint16_t cnt){
uint16_t i, t[1024+16];
uint8_t a, b;
for(i=0; i<cnt; i++) t[1023+16-i] = data[i] ^ nop_bin[i];
for(i=0; i<cnt; i++){
a = t[i];
b = t[i]>>8;
if(i>=0x208){
b = (b >> 2) | (b << (8-2));
a = (a >> 6) | (a << (8-6));
}
else{
a = (a >> 3) | (a << (8-3));
b = (b >> 5) | (b << (8-5));
}
data[i] = a<<8 | b;
data[i] &= 0x3FFF;
}
}
https://youtube.com/watch?v=HRjVPssgL48 (https://youtube.com/watch?v=HRjVPssgL48)
Hello together
I wanted to ask if the PFC161 is supported by SDCC and the free pdk programmer at the time.
Where is the activity regarding Nyquest suddenly coming from? I noticed you can now buy plenty of their devices very cheaply on LCSC. It looks like they are basically PIC clones? They are supported by SDCC?Correct, they are PIC clones. Their NY8 C compiler uses a modified SDCC without following the GPL open source license by opening the source code of the modified tool chain.
something worth mentioning in the newer padauk IDE. They are using a key and response system for the customer service to unlock clients that can not connect to the internet. Might be a fun investigation if someone is interested. The way to access the unlock dialog is to run a fresh IDE without internet connection and click Help > News
Where is the activity regarding Nyquest suddenly coming from? I noticed you can now buy plenty of their devices very cheaply on LCSC. It looks like they are basically PIC clones? They are supported by SDCC?Correct, they are PIC clones. Their NY8 C compiler uses a modified SDCC without following the GPL open source license by opening the source code of the modified tool chain.
Not really, it's just an alternative way of network activation. If there's a working internet connection the activation process is automatic and transparent to the user.something worth mentioning in the newer padauk IDE. They are using a key and response system for the customer service to unlock clients that can not connect to the internet. Might be a fun investigation if someone is interested. The way to access the unlock dialog is to run a fresh IDE without internet connection and click Help > News
So the new IDE is locked down? It really seems that Padauk is not appreciating the open market...
I am having a good time with the CH32V003. It's a minimal RISC-V (RV32EC) microcontroller that is only $0.10 and comes with an excellent free toolchain. Not to speak of an overabundance of periphery including DMA...
also, seems like they just released some MCU with EEPROM or lithium charger.
They are also planning to release some hall effect switches next year.
I want to program PFC161 using freePDK hardware. For this I need to use the development branch. Using the firmware of master branch does not support in development branch. But there is no
EASYPDKPROG.dfu file in this branch. Where can I get it?
Reply to self :(Hi,
The problem is understood but not solved. The chip has no issue and identifies correctly
Our motherboard has 'just' a 10k pullup to the Padauk supply on the programming pins, but that already causes the programming interface to get wrong bits apparently and fail. I assume its some critical timing in the programmer firmware, a 10k pullup should actually not have any influence on a digital signal like that programming data pin.
We use easypdk 'lite' with 100 ohm series resistors in the programming lines, removing those does not change anything.
Johannes
uint32_t FPDK_ProbeIC(FPDKICTYPE* type, uint32_t* vpp_cmd, uint32_t* vdd_cmd)
{
//try to get IC with low voltages
*vpp_cmd = 4500; *vdd_cmd = 2000;
...
You can try to increase those values slightly to compensate for pull ups / downs in your circuit. E.g. try to set vpp_cmd to 5500 and vdd_cmd to 2500 or 3000 and check if probing is working with your circuit. Note: This is just for the probe command. { .name = "PFC154",
.otpid = 0x2AA5,
.id12bit = 0x34A,
.type = FPDK_IC_FLASH,
.addressbits = 13,
...
.vdd_cmd_read = 2.5,
.vpp_cmd_read = 5.5,
.vdd_read_hv = 2.5,
.vpp_read_hv = 5.5,
...
.vdd_cmd_write = 2.5,
.vpp_cmd_write = 5.5,
.vdd_write_hv = 5.5,
.vpp_write_hv = 0.0,
...
Hi JS,
i can send you PFS122 via DHL quickly (within europe), we bought a good quantity of -S16 and -U08
I have quite some parts stocked now in Portugal - i believe in using those padauks for several projects, so we bought stock to have them.
Plus - i want to use them commercially so happy to send you a bounty to get this moving.
Johannes
I did some more investigation about the programming problem with the pullup on the padauk PFC154 ('in circuit programming').
My suspicion proves correct, it is the pullup on the data line (PA6). The other pins used for programming are not affected.
It is super easy to reproduce, if you just add a 10kOhm pullup between PA6 and VDD on a sip test socket with a PFC154 and plug that to easyprog lite. it cannot identify the chip properly.
The error seems to be just in the last bit of the ID, and with the scope i verified that the levels of the bits seem correct.
So my assumption is that this can be fixed in software on easyprog, it is probably an issue of sampling timing of the answer, and it is not an issue of the padauk pin (not being able to drive against 10k or the like).
attached
- picture of setup (with easyprog and pfc154 and the pullup)
- picture of signals on scope without pullup
- picture of signals on scope with pullup.
I dont know the exact serial programming protocol of the padauk, but i can investigate into the firmware of the programmer and probably figure this out, however, i assume some of you are much faster on this.
Johannes
OK, so i have a full feature I2C implementation, interrupt based, working.
It simulates the usual PCF8574 but it also 'makes' a second device with 16 generic registers plus some readonly info for identification.
All works 100% in interrupt context, so the 'main' program is free for other functions.
There is a 'notification callback' when the PCF8574 is written so the main program can take action.
I will test the code a bit and clean it up. I will eventually publish it as open source, if someone is interested i can share it now.
One problem i stumbled upon which i would like to 'warn' about ;)
The bit set/reset instructions on the IO ports (PA and PB) do not affect a single bit. the implementation in the padauk is made in a way that they read back all 8 bits, modify the specific bit, and then put them back into the output register. So if a specific bit (in my case i2c data) is set to 0, but 'input', the set bit instruction on any other IO bit in that port will result .. in the 0 being changed to 1 (by readback of the input with '1 value and write out). It is logical but caught me ..
last comment (actually this is a question): i would like to use the "SWAPC" instruction, but did not get that to compile (well .. assemble). Is that maybe missing or is there a specific syntax i am missing ?
I tried SWAPC and also SWAPC.io, neither worked.
Cheers
Johannes
Checking OTP_ID we learn:
PFS121, PFS122, PFS172, PFS172B are all the SAME IC.
PFS123, PFS173, PFS173B are all the SAME IC
So looks like PFS122 support was there all the time :-DD
JS
OK, so i have a full feature I2C implementation, interrupt based, working.
It simulates the usual PCF8574 but it also 'makes' a second device with 16 generic registers plus some readonly info for identification.
All works 100% in interrupt context, so the 'main' program is free for other functions.
There is a 'notification callback' when the PCF8574 is written so the main program can take action.
I will test the code a bit and clean it up. I will eventually publish it as open source, if someone is interested i can share it now.
One problem i stumbled upon which i would like to 'warn' about ;)
The bit set/reset instructions on the IO ports (PA and PB) do not affect a single bit. the implementation in the padauk is made in a way that they read back all 8 bits, modify the specific bit, and then put them back into the output register. So if a specific bit (in my case i2c data) is set to 0, but 'input', the set bit instruction on any other IO bit in that port will result .. in the 0 being changed to 1 (by readback of the input with '1 value and write out). It is logical but caught me ..
last comment (actually this is a question): i would like to use the "SWAPC" instruction, but did not get that to compile (well .. assemble). Is that maybe missing or is there a specific syntax i am missing ?
I tried SWAPC and also SWAPC.io, neither worked.
Cheers
Johannes
Could you check if you can flash the PFS122 with the easy-pdk-prog with the PFS172 flag.
If that works we can add PFS122 to easy-pdk-prog and have official support!
edit: forget to say flag
You can try the previous version of SDCC to get SWAPC to compile, but they I believe you will have to also revert all the .IO syntax. There is an outstanding bug report about the issue here: https://sourceforge.net/p/sdcc/bugs/3376/. Hopefully it is resolved for the next release.
One problem i stumbled upon which i would like to 'warn' about ;)
The bit set/reset instructions on the IO ports (PA and PB) do not affect a single bit. the implementation in the padauk is made in a way that they read back all 8 bits, modify the specific bit, and then put them back into the output register.
One problem i stumbled upon which i would like to 'warn' about ;)
The bit set/reset instructions on the IO ports (PA and PB) do not affect a single bit. the implementation in the padauk is made in a way that they read back all 8 bits, modify the specific bit, and then put them back into the output register.
Could you explain your observation a bit more in detail? I'm working on a cycle accurate emulator which also includes peripherals (parts of it been used in the noiseplug showcase project: https://github.com/free-pdk/easy-pdk-showcase-projects/tree/master/noiseplug/emulation (https://github.com/free-pdk/easy-pdk-showcase-projects/tree/master/noiseplug/emulation))
sorry for the delay.
compiler: it will definitely not do the read/modify/write as 3 opcodes, that you would see in the assembly listing and the set0.io instruction is actually assembly already.
i agree you would wish that only one bit would be changed, but this not what i observe.
There is a simple test to do:
add a pull-up (or program a pull-up) on one bit on PA or PB (lets take the example here, PB0).
i want to use PB0 as 'open collector' output (actually for i2c ..)
So i do a set0.io PB,#0 - to set the bit to 0
after that, using PBC i can make the pin either '1' (due to the pullup) if i configure it as input, or '0' if i configure it as output in PBC.
then, while the bit is 'input', set ANY other bit in PB, one or zero does not matter.
the data bit '0' stored in the holding register for PB0 will be changed to a one, although no-one does a set1.io PB,#0
So it seems setting ANY bit in PB will 'read back' ALL values as seen from the port, change the one bit in question, and write them all to the port's holding register.
In normal situations (where inputs are inputs always) this would not harm as the value in the holding register is not important. however, in my usecase i depend on the 0 to be there, and as it is magically 'changed' now i need to set it to 0 everytime before i enable the output .. doable but annoying and i think its worth a warning.
Johannes
One problem i stumbled upon which i would like to 'warn' about ;)
The bit set/reset instructions on the IO ports (PA and PB) do not affect a single bit. the implementation in the padauk is made in a way that they read back all 8 bits, modify the specific bit, and then put them back into the output register.
Could you explain your observation a bit more in detail? I'm working on a cycle accurate emulator which also includes peripherals (parts of it been used in the noiseplug showcase project: https://github.com/free-pdk/easy-pdk-showcase-projects/tree/master/noiseplug/emulation (https://github.com/free-pdk/easy-pdk-showcase-projects/tree/master/noiseplug/emulation))
Would it make sense to merge this work into the uCsim simulators that SDCC uses?
Not so. When setting 8 MHz, calibration is normal.
If I install any other it is not calibrated. In this case, the file from the example, I did not change it.
well, pretty much quiet here .. seems padauks are not in favor any more ;)
I have put out a 500$ bounty for the PFS132 support ..
https://app.bountysource.com/issues/123829632-pfs132-support (https://app.bountysource.com/issues/123829632-pfs132-support)
Cheers
Johannes
Looks really neat! 0'1" less wide and you would not need the riser. :) But then, no place for silk screen...
Btw, which PCB layout program did you use?
static uint16_t t16_reset_val = 0;
/* Wherever I need to reset T16 counter: */
__asm__("stt16 _t16_reset_val\n");
__sfr16 timercnt;
void f(void)
{
timercnt = 0;
}
If you want to set the timer to 0, why not just do so?
(some stuff, in particular setting the counter to a small value, works)