Author Topic: EEVblog #1216 - PCB Layout + FPGA Deep Dive  (Read 1224 times)

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Offline EEVblog

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EEVblog #1216 - PCB Layout + FPGA Deep Dive
« on: May 28, 2019, 11:38:28 pm »
Only Dave can turn a simple question into a 1hr deep dive monologue into PCB layout and FPGA implementation.

FPGA power supplies, DC margins, dynamic power requirements, power budgets, high power designs, multi layer PCB design, placement, system considerations, power planes, copper weighting, stackups, routing, split planes, star grounding, blind and buried vias, and a whole lot more.

 
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Offline free_electron

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #1 on: May 29, 2019, 01:57:36 am »
The problem is that for such large currents you need wide traces. There simply is no room on that board to place such wide traces. so they opted for two wires instead to bring the current from the connector to the dc/dc.

There is multiple problems :
- You do not want big fat copper planes on one outside layers as the thermal differences will warp the board when it goes through reflow. copper needs to be balanced in vertical space.
- large current on inside layers is a thermal problem. you need double the width on an internal layer as opposed to an outer layer.

if they had routed the current on an internal plane they would have lost the usage of that plane for ground or low voltage feeding the FPGA's. they could only have overcome this by adding two additional layers. for such a large board this becomes costly. two wires was cheaper.
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Offline LapTop006

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #2 on: May 29, 2019, 01:44:48 pm »
- large current on inside layers is a thermal problem. you need double the width on an internal layer as opposed to an outer layer.

I've wondered why the convention that internal layers are half-ounce copper, is it purely a convention or is there anything more to it?
 

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #3 on: May 29, 2019, 01:56:07 pm »
- large current on inside layers is a thermal problem. you need double the width on an internal layer as opposed to an outer layer.

I've wondered why the convention that internal layers are half-ounce copper, is it purely a convention or is there anything more to it?

afaiu the blank pcb is 1/2oz, outer layers are plated thicker with the vias 
 

Offline free_electron

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #4 on: May 29, 2019, 04:46:38 pm »
It all depends. Standard prepreg is 17 micron ( 1/2 ounce ). After plating that becomes 1 ounce ( not always true ... depends on aspect ratios. for very small hole boards it becomes 2/3 oz because they can't fill the holes anyway. fluid doesn't go through.)

So internal layers stay at 1/2 oz , outer layers grow up.

It is also a misconception that 1oz copper can handle double current than 1/2 oz. The 'grown' copper has weaker current handling as it is less dense than rolled copper.
The current limit on internal layers has to do with internal heating. the outer layers can radiate off their heat to ambient while internal layers have to bank on conductive heat removal. Fr4 is a VERY bad thermal conductor and that poor copper is sandwiched between layers of FR4.

'parallelling' layers is also not very effective. visually think about it this way : you have a double sided board. On top layer you solder a wire on the left and on the right. you send current through the top layer. Now drill two vias between top and bottom layer and connect top and bottom layer. Why would electrons go from top layer , through the via , through bottom , through another via back to top if they can simply flow in the top layer. path of least resistance. via's add impedance. This is all the more true for pulsed currents. ( ac or superimposed ac on dc ). The faster the rise times and the higher frequencies in the spectrum the more it is affected by via impedance.

There is also displacement effects ( skin effect )

You can have thicker copper on inner layers. i've done 8 layer boards with 4 oz copper on inner layers and 1 oz on outer. Then again , there's 300 ampere running through those things. You drop directly form outer layer onto mid layers and make sure there is no pathway on the outer layers between begin and endpoint for the current. That way you force current to flow on inner alone. The reason for sticking with 1oz on outer layers is that the routing on outer layers needs 4 mil track and gap. you can't do that on 2 oz copper. on 4 oz copper narrowest trace is 12 mils. on 2 oz copper 8 mils. For such thick copper you end up with trapezoidal cross sections due to etching. having a skinny trace next to a heavy slab is a recipy for overetching the skinny traces.

Once you are dealing with large currents ( over 10 ampere ) things start becoming tricky. 
another problem is that , with planes, you need to take care not to end up with 'swiss cheese'. every via you shoot creates a hole in the plane... an obstacle for electrons to flow around.
For fast signals ( even differential ones ) : shoot ground via's to couple them and force the pathways. don't leave it up to chance.

You need to visualize the current paths in 3d. For really complex boards : use a PDN analyser ( Power Distribution Network : PDN ) and find the weak spots in your layout.



another problem today is ever decreasing operating voltages. many high performance cpu's run at 1.8 or 1.2 volts with margins as low as 10 millivolt... if voltage goes down , current goes up ... and it becomes a geometry problem. Modern designs move away from centralized power regulation to a POL approach ( Point Of Load ). multiple dc/dc converters all feeding their local islands from a high voltage bus. the high voltage bus carries much lower currents and thus requires less copper real estate. Convert down , where you need it , and keep the distance between generation ( the dc/dc ) and the load , short .

You can do experiments with current tracker probes. i believe mikeselectricstuff has a video on that where he traces the actual current through a plane using a current tracker (iprober)
« Last Edit: May 29, 2019, 04:53:32 pm by free_electron »
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Offline johnlsenchak

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #5 on: May 29, 2019, 04:52:44 pm »


I  had  to watch  this video  twice because you real  went down  that  "rabbit hole"  all the  way to China  :)


I'm  not a  circuit  board  designer , I won't  claim ever to be one, however  wouldn't  common  sense  tell you  just put the power  connector
close to the  two  power  DC-DC converters  from the start?  Then you would just  run a  power and ground  plane  between the layer of the
PC  Board  directly  to the two FPGA's
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Offline free_electron

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #6 on: May 29, 2019, 04:55:49 pm »


I  had  to watch  this video  twice because you real  went down  that  "rabbit hole"  all the  way to China  :)


I'm  not a  circuit  board  designer , I won't  claim ever to be one, however  wouldn't  common  sense  tell you  just put the power  connector
close to the  two  power  DC-DC converters  from the start?  Then you would just  run a  power and ground  plane  between the layer of the
PC  Board  directly  to the two FPGA's

yes, but that is not always possible. in an ideal world the dc/dc on that fpgd bord would sit symmetrically between the thw fpga's with the power connector right next to it. But the monitor case designers may have something to say about that .... it won't look nice if the connector comes out in the middle of the screen .... users may complain :)

That is the difference between an 'arduino board' where they just put things where they like , and a real product that is driven by form fit and function. There are many many aspects and tradeoffs , and it is sometimes very hard to do the board layout to fit counterproductive needs.
« Last Edit: May 29, 2019, 04:57:41 pm by free_electron »
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Offline free_electron

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #7 on: May 29, 2019, 05:25:55 pm »
found the video



watch last 5 minutes. he shows how current flows in plane and around 'obstacles' and does not go in 'dead space'
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Offline German_EE

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #8 on: May 29, 2019, 05:31:23 pm »
Surprised that nobody has mentioned running solder over the traces to increase the current handling capability. I remember an elevator control PCB that had to switch about 60A per phase and that had copper wire soldered to the PCB on five or six traces. The board wouldn't have bent from the stress though, it was about 3mm thick!
Should you find yourself in a chronically leaking boat, energy devoted to changing vessels is likely to be more productive than energy devoted to patching leaks.

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Offline free_electron

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #9 on: May 29, 2019, 07:27:59 pm »
Surprised that nobody has mentioned running solder over the traces to increase the current handling capability. I remember an elevator control PCB that had to switch about 60A per phase and that had copper wire soldered to the PCB on five or six traces. The board wouldn't have bent from the stress though, it was about 3mm thick!

well there is something to be said for adding surface mounted busbars. There are special copper preforms that look like a 2206 package ( width of a 1206 but long like a 2225 ) they are solid copper if 0.8mm by 0.8mm and used for smt placement. you place them in a staggered herringbone pattern. It does add 60 to 70% current handling capacity of a 1oz trace.

Another technique for high current is embedded copper slugs or 'coins' ( also used for thermal dissipation ) , or simply go with embedded copper wires.

wirelaid technology : https://www.we-online.com/web/en/index.php/show/media/04_leiterplatte/2013_1/wirelaid_1/design_rules/Designguide_WIRELAID_0713_EN_Screen.pdf

embedded copper coins for current handling


[imghttps://www.ttmtech.com/products/images/press_fit_coin.jpg[/img]http://embedded copper coins for trans-board cooling purposes



i know a thing or two about handling large current through boards .... -grin-
« Last Edit: May 29, 2019, 07:30:44 pm by free_electron »
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Offline schratterulrich

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #10 on: May 29, 2019, 07:50:40 pm »
We have once tried to use "copper slugs" to transfere the heat from a SMD transistor to a heatsink on the backside of the board.
It was very difficult to get the planarity on both sides of the board surface needed for reliable SMD soldering and a good connection to the heatsink on bottom. We finally gave it up for cost reasons as well.
We have redesigned it and optimized it for thermal vias.
Capped thermal vias can be placed very densily under the SMD pad and give a quite low thermal impedance, too.
 

Offline free_electron

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #11 on: May 29, 2019, 08:01:48 pm »
We have once tried to use "copper slugs" to transfere the heat from a SMD transistor to a heatsink on the backside of the board.
It was very difficult to get the planarity on both sides of the board surface needed for reliable SMD soldering and a good connection to the heatsink on bottom. We finally gave it up for cost reasons as well.
We have redesigned it and optimized it for thermal vias.
Capped thermal vias can be placed very densily under the SMD pad and give a quite low thermal impedance, too.

you do NOT solder to the slug ! you need to treat it as a heatsink with thermal compound and pressure mount.
another solution is to just mill cavities and stick the heatsink through , but if you also need electrical connection then the copper slug is a better idea.
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Offline LapTop006

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #12 on: May 29, 2019, 11:42:44 pm »
... Modern designs move away from centralized power regulation to a POL approach ( Point Of Load ). multiple dc/dc converters all feeding their local islands from a high voltage bus. the high voltage bus carries much lower currents and thus requires less copper real estate. Convert down , where you need it , and keep the distance between generation ( the dc/dc ) and the load , short .

This I'm familiar with, the magic term for the datacenter stuff is "48v POL".

Some random PDFs on it:
https://www.apec-conf.org/Portals/0/APEC%202017%20Files/Plenary/APEC%20Plenary%20Google.pdf?ver=2017-04-24-091315-930&timestamp=1495563027516
https://www.st.com/content/ccc/resource/corporate/company/divisional_presentation/group0/28/f9/07/50/fd/dd/48/fa/APEC_2017_48V_Direct_Conversion/files/APEC_2017_48V_Direct_Conversion.pdf/_jcr_content/translations/en.APEC_2017_48V_Direct_Conversion.pdf
http://www.wiwynn.com/usr_files/48V_An_Improved_Power_Delivery_System_for_Data_Centers_20170626_final.pdf
https://www.maximintegrated.com/content/dam/files/products/power/switching-regulators/48V-rack-power-architecture-for-hyperscale-data-centers.pdf
 

Offline radar_macgyver

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #13 on: May 30, 2019, 05:18:44 am »
A Virtex 6 (Vcore of 1.0 volts), on a board from a commercial vendor once gave me trouble due to core voltage fluctuations. I was pushing the V6 somewhat hard (clocks at 400 MHz) and noticed that a DDS core would spit out glitchy values, but only on one channel of a multi-channel design. I spent nearly two months adjusting constraints and adding pipelining to no avail. Strangely, the same bitstreams worked fine on a second copy of the board which had a newer assembly revision. A senior Xilinx engineer on their forums asked me to measure the core rail with a decent scope, and that's when I saw that when the FPGA drew a large amount of current (a bunch of logic all started to operate at once) the core voltage sagged by ~50 mV, which dropped the voltage just to the edge of the allowed range. This, according to the Xilinx engineer, was enough to slow down the logic to violate timing and result in glitches. After reporting this to the board vendor, they let me know the assembly revision change was... drumroll... bumping the core voltage from 0.95 to 1.0 volts.
 

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #14 on: May 30, 2019, 09:08:36 am »
That's why I always design for the upper range of the allowed Vcore values. If it's 0.95 - 1.05V I'll aim for 1.00V <= V <= 1.05V.
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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #15 on: May 31, 2019, 05:38:59 pm »
Dave mentioned something about Finite Element Analysis for the ground plane. How much is it (FEM) used in electrical/electronics engineering ?
 

Offline schratterulrich

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #16 on: June 01, 2019, 12:25:31 am »
Wie use FEM for simulating the impedance of PWR-GND plane in combination with decoupling caps. Our CAD tool from ZUKEN supports this simulation. The benefit is, that wie don't use 100nF caps at each pin. Instead we place capacitor groups optimized with the simulation to get a low impedance up to 1GHz. We habe good experiance with this approach also for EMC.
Our products are used in industrie with about 1000 units per product and year.
 

Offline thm_w

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #17 on: June 03, 2019, 07:38:19 pm »
The current limit on internal layers has to do with internal heating. the outer layers can radiate off their heat to ambient while internal layers have to bank on conductive heat removal. Fr4 is a VERY bad thermal conductor and that poor copper is sandwiched between layers of FR4.

Learned recently this is not the case. Recommended trace width for internal layers is the same as external layers. That would change if you are using different copper thickness, 1oz external 0.5oz internal, for example, which is normal to do. So internal layer in general would be about 2x width of external due to additional plating (as you've explained).

FR4 thermal conductivity is 0.29 W/(m·K). Thermal conductivity of air is 0.026 W/(m·K), 10 times worse. The heat will get through the FR4 much easier than it will get from board to air. If you have a plane it can conduct to that as well (as Dave showed a bit in the video, with the saturn calculator). The FR4 is also usually very thin on an impedance controlled board.
Of course there may be special situations, if you have a hot trace on the outside then one just under it, would make things more complicated. But a lot of the calculators are based off of old calculations that are misleading or flat out wrong.

Quote
For comparison, we also provided the numbers based on legacy IPC2221. You can see that the old PCB design standard overstated current carrying capacity of external tracks. Therefore it seems that for small boards without planes the designs that relied on the historical charts might have resulted in underrated external traces. That document also arbitrarily assumed that internal conductors could carry only half of the current of the outer ones. In reality, as mentioned in the new standard, inner layers may actually run cooler because the dielectric has 10 times better thermal conductivity than air.

https://www.smps.us/pcb-calculator.html
https://en.wikipedia.org/wiki/FR-4#cite_note-IEEE-1
 

Offline free_electron

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Re: EEVblog #1216 - PCB Layout + FPGA Deep Dive
« Reply #18 on: June 04, 2019, 03:01:43 pm »
Dave mentioned something about Finite Element Analysis for the ground plane. How much is it (FEM) used in electrical/electronics engineering ?

Quite a bit.

CST studio
Flomerics
Comsol
Ansoft
Keysights ADS

Thermal modeling,  Magnetic Modeling, Power modeling, RF Modeling ...

You try to figure out the impact of mechanical warpage of the board on a microstrip pin filter used in a 76GHz radar....
The board warps due to mechanical impact ( mounting screws ) and thermal expansion when in use.  What are the best positions for the screws and dams to alleviate this problem ?
Comsol can do it.


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