EEVblog #1228 - Do Digital Scopes Have REAL Verniers?

[ogden]

After reading the HMCAD1511 data sheet I'm quite sure it doesn't have 13 ADC bits internally, although it does have 8 ADCs.

It does not have 8 ADCs but 4. Datasheet states it clearly that it is not just 8 bit ADC internally, on DS page 23: "There will be no missing codes for gain settings lower than 32x (30dB), due to higher
than 8 bit resolution internally. ". BTW I was wrong about ADC gain step, it is actually 1dB. Will fix original post.

[alpher]

Looks like we don't want Siglents on the channel in the future. The hardware isn't terrible but the crowd is a nuisance.

  They certainly are, rabid fanboyism is what swayed me finally toward buying a Keysight instead they beloved Siglent. So it worked against their (at least some of them) interests.
They're like that ubiquitous used car salesman, when he start pushing that certain car on the lot , you know you have to run. 

[ogden]

They're like that ubiquitous used car salesman, when he start pushing that certain car on the lot , you know you have to run. 

That's problem of salesmen, not car. In case of your example probably both are inferior. What I am trying to say - don't spoil your buyers decisions by analyzing salesman "performance" instead of product. Disclaimer: I am far from "fanboy" of Siglent.

[StillTrying]

It does not have 8 ADCs but 4.

Perhaps it's the way they're describing the differential inputs.
P26:
HMCAD1511 is a multi Mode high-speed, CMOS ADC, consisting of 8 ADC branches, configured in different channel modes, using interleaving to achieve high speed sampling. For all practical purposes, the device can be considered to contain 4 ADCs.
P13:
Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves 4 ADC branches, while single channel mode interleave all 8 ADC branches.

Edit: By my calculation you need 8 ADCs to do 1Gsa/s from a 1GHz clock, although I'm confused by the timing diagrams.

Datasheet states it clearly that it is not just 8 bit ADC internally, on DS page 23: "There will be no missing codes for gain settings lower than 32x (30dB), due to higher than 8 bit resolution internally.

Analog resolution might be 13 bit but the ADCs are 8.

[Mr. Scram]

They certainly are, rabid fanboyism is what swayed me finally toward buying a Keysight instead they beloved Siglent. So it worked against their (at least some of them) interests.
They're like that ubiquitous used car salesman, when he start pushing that certain car on the lot , you know you have to run. 

It's the same here. Initially I thought Siglent was doing okay but considering anything that could look like criticism causes the Church of Siglentology to jump down your throat, it seems impossible to get a good idea of the drawbacks and issues with the products. The useful information is drowned out. If you can't inform yourself you can't make a good assessment and a sale is lost. The forum unfortunately also loses some of its value. I started looking elsewhere and it looks like it might be a Keysight too.

[ogden]

HMCAD1511 is a multi Mode high-speed, CMOS ADC, consisting of 8 ADC branches, configured in different channel modes, using interleaving to achieve high speed sampling. For all practical purposes, the device can be considered to contain 4 ADCs.

Thank you for pointing out about 8 ADC branches, yet it still does not add-up. To get 8x gain at ENOB of 8-bit ADC (7.6 bits), one need much more than eight 8-bit ADC's. Conclusion still is - internal resolution of ADC's is more than 8 bits. After all manufacturer states that and as already mentioned - I am sure they do not lie. Thou, it's interesting that in the datasheet ADC SNR/ENOB figures for 10x gain are specified for single channel only.

Edit: By my calculation you need 8 ADCs to do 1Gsa/s from a 1GHz clock

No you don't. I do not know internals of particular chip, but for example flash ADC will give one output per each clock pulse.

[StillTrying]

yet it still does not add-up.

Yes, I can't find a description of the 1511 or similar internal workings.

I still think the ADCs are 8 bit, and the part that is adjustable at the fine 2^13 resolution is each ADC's Ref. voltage or something, and all the other larger gain changes are done in analogue rather than ignoring the top or bottom 5 bits of a 13 bit conversion.

Conclusion still is - internal resolution of ADC's is more than 8 bits. After all manufacturer states that and as already mentioned - I am sure they do not lie. Thou, it's interesting that in the datasheet ADC SNR/ENOB figures for 10x gain are specified for single channel only.

I forgot they could be flash, but I doubt there's 4(or8) 13 bit flash converters in there.

[David Hess]

Thanks for the video Dave.  The demonstrated non-decimal vernier step size gives some idea of what is going on.  My cursory examination of the VGA datasheet seems consistent with the displayed vernier step sizes.

My guess is that the fine gain control of the HMCAD1511 and similar ADCs is only being used for gain calibration between the ADCs when operating in interleaved mode as the datasheet discusses.  Their range is just too small because they are meant for only this purpose.  This explains why the external VGA is necessary for vernier operation.  If there is another vernier adjustment, then I suspect it is being done by trimming the ADC's reference voltage but that does not appear to be happening here.

Modern pipelined ADCs produce more bits per stage than strictly needed and then these bits are combined through digital error correction to produce the final monotonic output.

The VGA here only has 7 bits of "vernier" gain control.  The 8th bit selects between low and high gain mode.

The Siglent's calibrated vernier settings seem to follow the vernier gain settings that are actually available in hardware rather than an arbitrary scale like decimal.

[rf-loop]

Do digital oscilloscopes have REAL vertical vernier controls?
Let's probe a scope up the clacker to find out!

Thank you about this video update/edit. Now it looks much better if the viewer also carefully takes note of all the added texts.
(there is some hidden details still what it do not explain but it can not do without hard work for fully "reverse engineer" also ADC control bus data and imho it is not needed in this context )

[EEVblog]

Where Dave adds this note:
NOTE: The Rigol DS1054Z does have the ability to do vernier control. It uses the same HAD1511 ADC as the Siglent, and that ADC has two methods of vernier control. One is the digital gain after the ADC (available because the ADC is actually up to 13 bits internally). And second, the ADC reference voltage has an internal DAC that can be changed.
So either or both of those techniques can be used, technically no need for a Variable Gain Amplifier on the front end.

So why then is it used ? 

It's NOT used on the Rigol. The Rigol does not have a VGA.
As for Siglent, maybe they wanted different performance, or couldn't do it with the ADC alone. No idea, how about you ask them?

[rf-loop]

Video link on YouTube:

https://youtu.be/7v-P75MOZ5o

Where Dave adds this note:
NOTE: The Rigol DS1054Z does have the ability to do vernier control. It uses the same HAD1511 ADC as the Siglent, and that ADC has two methods of vernier control. One is the digital gain after the ADC (available because the ADC is actually up to 13 bits internally). And second, the ADC reference voltage has an internal DAC that can be changed.
So either or both of those techniques can be used, technically no need for a Variable Gain Amplifier on the front end.

So why then is it used ? 

It is not only vernier between main steps what need handle. Vernier steps and main steps are not different Exept in software)
Example whole voltage band I from 500uV/div to 118mv/div there is over 350 steps in Siglent SDS1000X-E and all these need solve using VGA and HMCAD1511 internals together.
Voltage bands II and III are bit more easy due to less steps.
Just alone from main step 500uV to 1mV/div it use 10uV increments.

[Kleinstein]

From die DS the ADCs inside are pipelined type ADCs with digital error correction. So the internal resolution needs to be higher, though possibly with missing codes that are only corrected later. So it is hard to even give a number for the resolution and it may very well be be not an integer number of bits. If the first pipeline stages are always one way with a small signal, the later stages may well give good resolution, like a 13 Bit ADC - though chances are it would not work that well (more DNL and possibly missing codes) if the initial stages are changing. With some 49.x   dB SNR the ADC is pretty close to an ideal 8 Bit ADC at low gain.

The gain adjust in the ADC is only really coarse steps (x2 , x 1.25 etc.) or very fine for a very small range. So it is not sufficient for a true vernier mode. It is still a little better than the normal 1:2:5 steps used on a scope.

[tautech]

As for Siglent, maybe they wanted different performance, or couldn't do it with the ADC alone. No idea, how about you ask them?

Don't need to.

The answer to why Siglent used VGA and ADC variable gain control is already in this thread:
https://www.eevblog.com/forum/blog/eevblog-1226-how-to-get-better-accuracy-on-your-oscilloscope/

And yes, the reasons have been further expanded on here.
Sometimes things are not as straightforward as they first appear and require deeper investigation for full understanding as rf-loop has shown. Neither VGA or ADC on their own are sufficient to get the full range of Fine adjustment so both must be used in tandem so a HW and SW solution is the solution.

[SilverSolder]

Very interesting video and forum thread.  To me, it made it clear that there are many ways to skin this particular cat - and clearly, there will be good and less good ways of implementing vernier gain, even with the same chips! 

Hard to think of a way to test oscilloscope vernier performance consistently, so different manufacturers/models can be compared...

[thm_w]

So makes me think, if all these gain ranges are available in a $7 chip (AD8370), why do we still have the poor software multiplied ranges in the keysight/rigol.
Even if the front end noise is too high, I think you'd still get a bit of benefit by having the extra gain ranges. Especially in the case of Rigol, adding an extra gain range to the ASIC should be minimal in terms of cost no? Maybe AD can get those performance levels but others can't.

[Kleinstein]

How difficult it is to add an VGA to the ASIC depends on the process used for the chip. It may not be that simple, especially hat high speed.  Anyway it will add power dissipation, making the chip run even hotter. An extra chip between the input stage and ADC is not such a bad solution.

Besides the VGA chip, it also needs calibration for the gain stages if it is supposed to be accurate.
For some cases (especially lowest gain) the VGA chip may also add some errors, linearity is limited and there can be a gain dependent delay. With a good (e.g. 10 Bit) ADC using just digital multiplication may not be such a bad decision.

[Mr. Scram]

So makes me think, if all these gain ranges are available in a $7 chip (AD8370), why do we still have the poor software multiplied ranges in the keysight/rigol.
Even if the front end noise is too high, I think you'd still get a bit of benefit by having the extra gain ranges. Especially in the case of Rigol, adding an extra gain range to the ASIC should be minimal in terms of cost no? Maybe AD can get those performance levels but others can't.

Possibly because people don't know and care. A video like this may create more awareness. Of course most customers may simply not care if it gets the job done.

[SilverSolder]

Maybe it's just me, but I would expect any scope to be implemented in a way that makes the best use of its hardware capabilities.  If the vertical amp vernier control doesn't actually control amplification, it should be relabeled "vertical zoom" or something like that?

[StillTrying]

I beginning to think the HMCAD1511 might not have any coarse analogue gain stages afterall.

Instead, 8 X 13 bit 125MHz ADCs. 2V input from the top 8 bits gives the X1 gain, 62.5mV input from the bottom 8 bits gives the X32 gain.
If the X50 gain is a digital multiplication of the X32 gain the top 92 values from the ADCs can't be used, because their values would be covered by the digital multiplication.