Author Topic: EEVblog #1323 PCB Layout Review & Analysis  (Read 1039 times)

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Offline EEVblog

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EEVblog #1323 PCB Layout Review & Analysis
« on: July 24, 2020, 11:51:06 pm »
Dave analyses a PCB layout from the EEVblog forum and covers all sorts of tips for SMD layout, component placement, routing, layer stackup, controlled impedance traces, supply planes and power bypassing.
Subscribe on Library: https://lbry.tv/@eevblog:7

 
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Offline highlanderIII

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Re: EEVblog #1323 PCB Layout Review & Analysis
« Reply #1 on: July 25, 2020, 09:27:19 am »
Dave - for floating head type videos, maybe mirror your floating head so that you appear to look (in the final video) towards the part of the board you are drawing on. Just a thought - I have no idea if this is easy to do in the edit.

Thanks for the great content!  :-+
Back from haitus
 

Offline Unixon

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Re: EEVblog #1323 PCB Layout Review & Analysis
« Reply #2 on: July 25, 2020, 10:12:18 pm »
That was fun! So much crazy shit in one layout :)

Long long time ago when I was just starting with switch mode DC-DC converters producing a somewhat crazy layout was OK until ST1S10 came along and that thing ... if you step away from recommendations even for a tiniest amount it just blew up and released magic smoke from everything that was powered from its low side.

A fylfot made of bypass caps and taces ... I guess this is the first time I witness it.
 

Offline Unixon

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Re: EEVblog #1323 PCB Layout Review & Analysis
« Reply #3 on: July 25, 2020, 10:35:17 pm »
One can loose sleep over these random width traces! Why not widen them to like a standard outer layer signal trace width on this board as soon as they're out of that tiny BGA? Having less places to fail with manufacturing the board is better, isn't it?
 

Offline HwAoRrDk

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Re: EEVblog #1323 PCB Layout Review & Analysis
« Reply #4 on: July 26, 2020, 11:23:43 am »
Great video.

One thing about that board design that sticks out to me, apart from the mentioned issues, is the USB-UART IC. It appears to be powered solely from the 2.8V rail. Don't those things need a minimum of 3V? Due to the D+/D- signalling levels being 3V. I suppose 2.8V is technically within tolerance, but it's marginal and I wouldn't rely on it. Also, if it's one of the USB chips that has it's own LDO integrated to create the signalling voltage, then minimum VCC will be more like 3.3V.
 

Offline coppercone2

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Re: EEVblog #1323 PCB Layout Review & Analysis
« Reply #5 on: July 27, 2020, 06:31:44 am »
i think the analysis is very through but it keeps reminding me of microsoft clippy

i don't know if its good or bad. i think i prefer just a window box with someone talking, its a little creepy. did you join the robot singularity? head floating around with a gag in the simpsons with virtual homer
« Last Edit: July 27, 2020, 06:33:54 am by coppercone2 »
 

Offline Clear as mud

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Online splin

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Re: EEVblog #1323 PCB Layout Review & Analysis
« Reply #7 on: July 30, 2020, 10:13:55 pm »
To minimse EMC/EMI problems wouldn't it be better to route all the signals on internal layers? E.g top (component side) and bottom ground planes, 2nd power plane 3rd layer signals. Obviously a lot more vias would be required - do PCB makers have limits on number of vias (or extra charges)?

It would also reduce ground loop area for decoupling by eliminating the vias to an internal ground plane and by bringing the power plane closer. It would also make it a bit more difficult to reverse engineer your product.

Signals sensitive to capacitive loading might need special treatment of course.

Perhaps you wouldn't want this for development but only for production versions.
 

Offline thm_w

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Re: EEVblog #1323 PCB Layout Review & Analysis
« Reply #8 on: July 30, 2020, 10:54:31 pm »
To minimse EMC/EMI problems wouldn't it be better to route all the signals on internal layers? E.g top (component side) and bottom ground planes, 2nd power plane 3rd layer signals. Obviously a lot more vias would be required - do PCB makers have limits on number of vias (or extra charges)?

It would also reduce ground loop area for decoupling by eliminating the vias to an internal ground plane and by bringing the power plane closer. It would also make it a bit more difficult to reverse engineer your product.

Signals sensitive to capacitive loading might need special treatment of course.

Perhaps you wouldn't want this for development but only for production versions.

Yes but as you said, makes development harder.
If you are completely changing the layout for production, then.. more chance for bugs to appear. So its not worth the risk for the average project.
http://www.hottconsultants.com/techtips/pcb-stack-up-1.html

There can be additional costs from the fab for via's if you go crazy with them, but just adding one for each IC pin in this example project is nothing.
https://www.eevblog.com/forum/eda/when-can-you-have-too-many-vias/
« Last Edit: July 30, 2020, 10:59:09 pm by thm_w »
 
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