How easy is it to take the open source Trezor Model T crypto hardware wallet files and manufacture your own? Or to modify or improve the design?
The Trezor is open source hardware, so Dave checks out the Github and looks at the hardware files available and imports into Eagle and KiCAD. Where to from here?
OSHW Logo generator:
https://maciek134.github.io/oshw-logo-gen/
Why not ask Chris Gammell about importing Eagle into KiCad, he has just done a video about it.
Nice. Shameless plug: I work on BitBox2, a successor BitBox01, now with a screen and touch/scroller sensors.
Schematics and BOM are here but they are in just PDF files:
https://github.com/digitalbitbox/bitbox02-firmware/tree/master/doc. I'm currently converting our Altium sources into KiCad with a plan to then publish everything including gerbers.
Curious what you think.
Alex.
Why not ask Chris Gammell about importing Eagle into KiCad, he has just done a video about it.
Well I just tried it with a fairly recent compile of KiCAD 5.99. It's still far from usable. Issues are mainly the silk screen (locations and size of labels) and the footprint conversion. In converted footprints, sometimes the silk layer is imported into the soldermask layer. So you have exposed copper where the silk screen should have been and no openings for pads. Effectively unusable unless you spend the time fixing those issues manually.
Dave, you can have multilayer board in free version of Eagle and even generate your Gerbers!
Eagle's CAM Processor complains about layer configuration but produces correct output files.
The policy about 3rd party files is something along the lines of that a loaded file is not a subjest for editing restrictions.
Fun fact: one can add additional layers to a standard 2-layer board and use them with little effort for power planes even in restricted freeware mode.
1) Open XML board file in text editor and declare new layers by copying and editing layer definition lines;
2) Open edited board file in Eagle, add a top/bottom polygon and then change layer that this polygon belongs to (you can do this multiple times back and forth);
Editing these layers is still prohibited, so it is not possible to put regular traces there, but one can have complex polygons correctly connected to vias and TH pads
p.s. These dotted polygons are unrouted polygons, you can run Ratsnest on them to fix this.
CAM Processor presets for 4 and 8 layer board are attached.
Example: 4-layer board (piece of .brd file header)
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
<layer number="2" name="Layer2" color="5" fill="1" visible="no" active="yes"/>
<layer number="3" name="Layer3" color="3" fill="1" visible="no" active="yes"/>
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
Example: 8-layer board (piece of .brd file header)
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
<layer number="2" name="Layer2" color="5" fill="1" visible="yes" active="yes"/>
<layer number="3" name="Layer3" color="3" fill="1" visible="yes" active="yes"/>
<layer number="4" name="Layer4" color="6" fill="1" visible="yes" active="yes"/>
<layer number="5" name="Layer5" color="7" fill="1" visible="yes" active="yes"/>
<layer number="6" name="Layer6" color="15" fill="1" visible="yes" active="yes"/>
<layer number="7" name="Layer7" color="9" fill="1" visible="yes" active="yes"/>
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
Well, you get the idea... XML is your friend.
Watch out for drill files! This board uses both TH vias (.0116 file extension) and blind vias (.0102 file extension).
This is how the PCB looks like after spending about 1 hour worth of fixing the footprints and adding some 3D goodness.
PS: after another hour or so, you're down to 20 DRC violations that you need to look into and about 1000 warnings about silkscreen overlaps that you can ignore for a while. The original PCB doesn't seem to have any reference designators on the silkscreen, so you'd do the same and disable them. Also, KiCAD by default warns about silkscreen overlapping pads, which Eagle (or the PCB designer who did the Trezor) seems to be OK with.
Watch out for drill files! This board uses both TH vias (.0116 file extension) and blind vias (.0102 file extension).
WTF, why would blind vias be needed on this?
I managed to load the files in too eagle cad (seem to now be part of fusion 360) and I keep looking at silk screen and wondering why it goes off the board? Also the reference designation seem to show up but they are all the wrong size some overlapping and some straight going over pads. I was able to generate some sort of parts lists but it still makes almost no sense with C_0603$REFLOW and some of the other thing dave mentioned,I have attached it bellow. I have also had a go at generating the Gerber files but I have almost no I idea what I am doing (2nd year electronics student), however I would more than happy to upload them if people want them.
Watch out for drill files! This board uses both TH vias (.0116 file extension) and blind vias (.0102 file extension).
WTF, why would blind vias be needed on this?
I don't know, but you can see ' extent="1-2" ' parameter in .brd file for some vias which determines a blind via while all other have ' extent="1-16" ' which determines through hole via.
This board is weird, it has 16 layers declared, but 3 of them used, 2nd internal layer is empty, there's not even a power polygon in there.
Top and bottom layers are signal+power, 2nd layer is signal, 3rd is empty.
Blind vias on this, why god why?
I tried importing it into kicad 5.99, the edge cuts are fine, after refilling nothing is not connected, the problem is those micro vias, which I honestly dones't understand the need for. I think it might be easier to relay out at least the traces.
I will be doing that now.
OK, I fixed blind vias, had to replace extent for all blind vias and move 3 of them slightly to fix overlapping with bottom signal traces.
Now it's semi-standard 3of4-layer board and it looks like it passes DRC.
Attached fixed Eagle files.
You have done a great job,
Importing into kicad gives me a huge amount of errors, the vias aren't connected on other layers it is complaining.
I really want to start this project all over. It might be worth it to reroute it. Also I hate their layout it sucks
Indeed, the designer allowed himself a pretty expensive luxury for convenience sake. Blind vias with 0.2mm drills, that puts you outside of cheap manufacturing. Pretty sure the whole board could have been done with 0.3/0.6 vias, it's not that densely populated. They could have reduced the track width in exchange for board area, they're doing 8/8, going down to 6/6 would have saved some space and still be what e.g. JLCPCB can manufacture. There's just two areas where routing will get a little fiddly, one is the USB-C receptacle where things are quite tight, the other place is the display connector on the bottom right of the top side.
Importing into kicad gives me a huge amount of errors, the vias aren't connected on other layers it is complaining.
I really want to start this project all over. It might be worth it to reroute it. Also I hate their layout it sucks
I'll put my KiCAD project on my github in a while. I'm down to about 4 DRC violations and a ton of silkscreen warnings that I excluded. Didn't fix the blind via thing yet. You're welcome to start from that.
Oh wow that display connector is killing me, that isn't within JLCPCBs capabilities. And yes the USB C, there is a trace that I am 100% confident cannot fit with JLC's capabilities, I would certainly change a few components to make them more easily manufacturable, the board isn't that small and there isn't that many components.
Considering the display connector ... it's almost OK, but pads must be little bit thinner to allow 0.2mm clearance.
USB C is OK, nothing special, 0.3mm pads with 0.2mm clearance.
Being a mechanical engineer I feel like mentioning that the data 3D for the case also seems to be only given as STEP format - not the actual CAD data.
It is more like having only a PDF file vs the actual native data that you can edit.
Another one to take off of their OSHW logo
I don't know these dimensions aren't manufactured easily with something like JLCPCB. We could go with cheaper and better suited components, especially that we only need USB 2.0
That is my favorite connector for that.
https://lcsc.com/product-detail/USB-Connectors_XKB-Enterprise-U262-161N-4BVC11_C319148.htmlAlso the clearances on that display connector is very small and not manufacturable with the usual scumbags.
The components are places way too close together and their orientations suck in my opinion, they could have spaced them out and made their locations more appropriate, they have the space why not use it.
Also the clearances on that display connector is very small and not manufacturable with the usual scumbags.
Here's your good clearance connector
p.s. It's easy to extract components from an Eagle project into a library. Just create an empty library and copy over (in text editor) corresponding library sections from .sch and .brd files. I believe once there was even a script to do this in one click.