What confuses me, is about the C extension, is just that, an extension to a base ISA like the I base, so to improve code density. But itself the extension is that, an extension it cannot even address all 16 registers for some of the instruction, only the higher 8 (of 16).
Yes, specifically r8-r15, the same as when applied to RV32I or RV64I. They happen to be the hi 8 registers in RV32E, yes, but not in the others.
This is no different to ARM Thumb/Thumb2, in which it is the low 8 registers that can be used by all 2-byte instructions, with several of the high 8 registers performing implicit jobs (PC, LR, SP). In RISC-V it is similar, but it is the low registers with implicit uses: Zero, RA (LR), SP.
In Thumb the 2-byte instructions that can use all 16 registers are MV, ADD, CMP, BX, PUSH, POP.
In RV32I/RV32E, the 2-byte instructions that can use all 32 (or 16) registers (with some individual exceptions for combinations that don't make sense) are: C.LI, C.LUI, C.ADDI, C.SLLI, C.MV, C.ADD, C.LWSP, C.SWSP.
So here is the question is, what is the actual base ISA for this chip? I guess is the RV32I.
No, the base ISA is RV32E.
RV32E is not an extension of RV32I, it is its own base ISA defined by "Copy RV32I, hard coding the MSB of all register fields to '0'. Instructions with a '1' in those positions are undefined reserved instructions."
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