EEVblog 1545 - World's Fastest Oscilloscope, MXO4 TEARDOWN

[David Hess]

Dual buffering is the generic approach to do acquisitions in every DSO. If you look close to the specs of a DSO you can see some have more memory in single shot and/or sequence mode.

None of my DSOs double buffer simply because it would have required two completely separate memory banks with duplicate hardware.  A single memory bank could not sustain access from the digitizer and the processor simultaneously.  On older DSOs double buffering might not yield any improvement if the analog trigger took too long to read and rearm.

[nctnico]

Then your DSOs must be really old  Even the Keysight Megazoom Asic does double buffering.

[Mechatrommer]

Then your DSOs must be really old  Even the Keysight Megazoom Asic does double buffering.

how much percentage of blind time do you know?

[egonotto]

Hello,

the MXO 4 has at least 4 GB for temporary information storage for operating system and instrument firmware and >= 7 GB for waveform data and measurement data.
Such information can be found in the "R&S®MXO 4 Series Oscilloscope Instrument Security Procedures"

Best regards
egonotto

[David Hess]

Then your DSOs must be really old  Even the Keysight Megazoom Asic does double buffering.

With an ASIC it makes a lot of sense because the extra multiplexing hardware can be integrated.  I am curious about their fast RAM implementation.

With older DSOs it was a struggle just to make the acquisition RAM fast enough without wider word widths, and this shows up with multiple channels not only halving the record length but the sampling rate also, so double buffering would have come at considerable cost.

All of the designs I came up with a couple years ago were either limited by the RAM which could fit on the acquisition FPGA, or the processor's cache size.  The cost of external memory was too high for what I was considering.

[nctnico]

Depends a bit on what you want to do where it comes to samplerate. Over 15 years ago I already managed to get to 1.6GB/s with DDR2 memory on an FPGA using a soft DDR2 controller. With a hard IP DDR controller on a more modern FPGA, you can easely get way more bandwidth. And typically these hard IP blocks support simulating dual/multi port access to make life easy. Pretty neat stuff! See the many oscilloscopes that are build around the Xilinx Zync FPGA for example.

[David Hess]

Over 15 years ago I already managed to get to 1.6GB/s with DDR2 memory on an FPGA using a soft DDR2 controller. With a hard IP DDR controller on a more modern FPGA, you can easely get way more bandwidth. And typically these hard IP blocks support simulating dual/multi port access to make life easy. Pretty neat stuff! See the many oscilloscopes that are build around the Xilinx Zync FPGA for example.

I was looking at DPO style designs so the data is not streamed to memory but instead used to update a 2D histogram which requires a read, modify, and write cycle, so standard DRAM would run at only a fraction of its rated speed.  That is why the alternative of using processor cache was so interesting.  An FPGA can do it because the operation can be split up at the cost of multiplying the required RAM, and then combining the acquisition histograms later.

The segmented memory method has the advantage of preserving the original acquisition record, but at the cost of extra complexity.

[Wolfgang]

Nice! A bit surprising that the MXO4 uses off-the-shelve ADCs. Didn't expect that but if they do the job for the right price then why not.

I made some tests about how many bits of the 12Bit Texas Instruments ADC are really usable. The answer is a bit above 10 at best, at 10MHz signal frequency and in high resolution mode.
Details here:

https://electronicprojectsforfun.wordpress.com/to-enob-or-not-to-enob/

[switchabl]

First of all, thank you for posting this, this looks like a formidable effort!

I will have to look at it again in more detail later but you seem to be using something like SFDR in your ENOB definition except you are counting noise bins as "peaks", is this correct? I see two problems with this:
1) The power of a noise bin is dependent on the (arbitrarily chosen) FFT length. In case the largest "peak" is a noise bin, the ratio is essentially meaningless. A normal SFDR measurement would use a sufficiently long signal to ensure that the largest spur/harmonic is clearly above the noise floor and the ratio is always taken between two tones.
2) This would actually be a strictly less stringent measure than "conventional" SINAD. You are comparing the signal power to that of the largest non-signal bin. SINAD (the way I would define it) involves the sum of all the other bins.

[Wolfgang]

First of all, thank you for posting this, this looks like a formidable effort!

I will have to look at it again in more detail later but you seem to be using something like SFDR in your ENOB definition except you are counting noise bins as "peaks", is this correct? I see two problems with this:
1) The power of a noise bin is dependent on the (arbitrarily chosen) FFT length. In case the largest "peak" is a noise bin, the ratio is essentially meaningless. A normal SFDR measurement would use a sufficiently long signal to ensure that the largest spur/harmonic is clearly above the noise floor and the ratio is always taken between two tones.
2) This would actually be a strictly less stringent measure than "conventional" SINAD. You are comparing the signal power to that of the largest non-signal bin. SINAD (the way I would define it) involves the sum of all the other bins.

Comment is correct, but that is why I used standard values for frequency, memory depth and sample rate. The point is when you see a "spur" or glitch or whatever, its normally not possible to determine what exactly caused it. In case of strong spurs, its clear, if noise is the main reason its getting fuzzy. You can also see this from the standard deviation values on my plots. Strictly speaking the total power of ALL spurs (plus noise) would go into the SINAD figure, but the practice I used is common for ENOB measurements AFAIK. The hard limit, at least as larger amplitudes, is always the 3rd or 5th harmonic of the signal frequency. In fact, the "largest peak" method overestimates the ENOB value by a small amount. For the TI ADC in the MXO4, the values found are very plausible. If what you want to measure are spectra, the SFDR approach is more practical than integrating over all non-signal components.

[ballsystemlord]

@EEVblog / Dave,
I think you were very pressed for time when you did this video, there's so much stuff in this scope that's not in other scopes, so I'd like to ask if you could do a follow up video on this scope so that you could go more in depth about the various components and stuff. What is believed to be Coilcraft inductors are just the tip of the iceberg in cool stuff this oscilloscope has inside of it.

Thanks!