Author Topic: EEVBlog #155 Itead Board Fail  (Read 12797 times)

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Offline frank26080115

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Re: EEVBlog #155 Itead Board Fail
« Reply #25 on: March 18, 2011, 02:52:47 pm »
question, when a design is finished, is it a good idea to disable the flood-fill and then run an auto-route and then re-enable the flood-fill? is there a better technique for this?
 

Offline FreeThinker

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Re: EEVBlog #155 Itead Board Fail
« Reply #26 on: March 21, 2011, 11:34:48 am »
Machines were mice and Men were lions once upon a time, but now that it's the opposite it's twice upon a time.
MOONDOG
 

Offline steaky1212

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Re: EEVBlog #155 Itead Board Fail
« Reply #27 on: March 21, 2011, 06:01:23 pm »
what I dont understand is how they managed to fit the a trace between two vias (TWICE!), but cant do the same with a flood fill.
Still, I am glad it didnt happen to me  ;)
 

Offline dimlow

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Re: EEVBlog #155 Itead Board Fail
« Reply #28 on: March 21, 2011, 08:38:31 pm »
So Dave, What is a uRGB MatrixDuino anything to do with a RGB LED Matrix ? seems Itead Published your board design and the name of your project on the link above. I dont think that was very good. I guess its like their Colorduino v1.3
« Last Edit: March 21, 2011, 08:40:43 pm by dimlow »
 

Offline RayJones

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Re: EEVBlog #155 Itead Board Fail
« Reply #29 on: March 22, 2011, 08:00:09 pm »
With hindsight, I can see two ways of avoiding the problem in future.

1/ do your polygon pour at 8 thou clearance and check the DRC. If OK, re-pour at 6thou and submit.
2/ add a deliberate track under the polygon pour to ensure connectivity.

It is amusing (in a way) to get this sort of result from the ultra precise Altium package.
I have been known to have similar issues with polygon pours when panelising many identical boards onto one large panel for another PCB service.
My problem was the copies were pasted without netlist connectivity (avoids the ratsnet appearing between boards).
The problem was allowing a polygon re-pour after the no netlist paste.
Result - instant isolation of all ground pins from the polygon pour.
Arrgggghhhh - wasn't funny at the time, but once the pain wore off ;D

BTW despite the issues, the boards look great, must give them a go myself.
Reasonable turnaround?
 

Alex

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Re: EEVBlog #155 Itead Board Fail
« Reply #30 on: April 03, 2011, 12:00:43 pm »
It seems this is not so uncommon after all and it is something to look out for when evaluating EMC performance.

Have a look at the highlighted text in the attached pdf.
 

Offline aXit

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Re: EEVBlog #155 Itead Board Fail
« Reply #31 on: April 22, 2011, 05:57:35 am »
Just got an order from Itead. Seems good enough, few holes slightly out of allignment with the pads, but nothing too serious. No issues like dave's, but this design was easily made with 10/10.

A very strange thing though... is that I got 11 boards, and only 4 were e-tested. I'm not sure what this really means. Maybe one failed the e-test, and they threw in 2 extra? Seem strange that they're making extra boards just in case they fail e-test.
 

Offline FreeThinker

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Re: EEVBlog #155 Itead Board Fail
« Reply #32 on: April 22, 2011, 01:03:43 pm »
Just got an order from Itead. Seems good enough, few holes slightly out of allignment with the pads, but nothing too serious. No issues like dave's, but this design was easily made with 10/10.

A very strange thing though... is that I got 11 boards, and only 4 were e-tested. I'm not sure what this really means. Maybe one failed the e-test, and they threw in 2 extra? Seem strange that they're making extra boards just in case they fail e-test.
Perhaps not. As I understand it they 'tag' the boards on to there production boards spare space, just as easy to make enough to fill the spare space as waste it and helps guarantee yield.
Machines were mice and Men were lions once upon a time, but now that it's the opposite it's twice upon a time.
MOONDOG
 


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