Author Topic: EEVblog #389 - Casio Calculator Investigation  (Read 10298 times)

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Offline FJV

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #25 on: November 24, 2012, 10:59:39 am »
Some form of alternative pcb may be in the future for use with 3d printers.

http://www.plosone.org/article/info%3Adoi%2F10.1371%2Fjournal.pone.0049365

Should be fun, I guess.


 

Offline mikeselectricstuff

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #26 on: November 24, 2012, 11:59:06 am »
I like this Olympia space-age looking thing :


Magnets & reed switches for the keys, plug-in PCBs.
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Offline free_electron

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #27 on: November 24, 2012, 12:41:48 pm »
Number of layers in a chip is hard to determine. There are a bunch of sacrifical layers that are created , removed , created again , removed again.
In terms of metallic interconnect the earliest chips had only 1 layer. modern chips have up to 6 layer metal the top 2 of which can be copper if needed but mostly are aluminum.
Then there is all the intermediate layers : nitride layers , polysilicon layers , the implanted structures.
Some masksets contain up to 100 masks each of which creates a 'layer' in the chip. Not all those layers remain behind. some are stripped as they serve as a temporary shield for a process step. Other layers are combined into 1 . they contain multiple structures that are made a different way but in the crosssection occupy only '1 layer' but they are made independently.

Masksets are horrendously expensive. They are essentially a quartz plate with a chrome film vacuum deposited onto it. this is then coated with a photoresist and exposed using an electron beam. after development the mask is plasma etched to removed the exposed chrome. the structures on the plate are much larger than they need to be on the chip.
the mask is covered with a reticle ( a thin film of celluloid offset about 1cm ) if any speck of dust were to fall on the reticle the distance is far enough we can focus straight through this. A 'stepper' uses a deep UV lightsource ( typically a quartz sphere containing some noble gases , which are excited using an X-ray source ) to send the light through the mask and the optical array. the wafer is then 'stepped' with this image. the mask holds, depending on size, the patterns for 1 to 20 chips.

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Offline IanB

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #28 on: November 24, 2012, 02:49:06 pm »
Number of layers in a chip is hard to determine. There are a bunch of sacrifical layers that are created , removed , created again , removed again.
In terms of metallic interconnect the earliest chips had only 1 layer. modern chips have up to 6 layer metal the top 2 of which can be copper if needed but mostly are aluminum.

Thanks for the answer. I was basically interested in the interconnect layers, where one conductor has to "cross over" another without making contact like the traces on a multi-layer PCB. It sounds like the answer is up to about 6.
I'm not an EE--what am I doing here?
 

alm

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #29 on: November 25, 2012, 01:08:32 am »
But probably less than six in an eighties-vintage IC.
 

Offline free_electron

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #30 on: November 25, 2012, 02:12:25 am »
Eighties vintage. One or two maximum. Three metal was end nineties...

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Offline jeroen74

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #31 on: November 25, 2012, 02:23:01 am »
I guess that also depends on the complexity of the chip. A calculator chip isn't particularly high tech or demanding. And just as with PCBs, component placement is a very big factor in how easily a PCB can be routed. From what I read, the complexity in FPGA/chip tools is in the placement algorithms, not the routing.
 

Offline tom66

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #32 on: November 25, 2012, 02:33:53 am »
The Casio VPAM ones clearly use a micro of some kind, the diag mode mentions "ROM" and "Read OK". But I wonder about the more basic ones. Do they use ASICs or some 8/4-bit micro core?
 

Offline jeroen74

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #33 on: November 25, 2012, 02:46:10 am »
I've been wondering this myself for ages too :) I guess the basic ones just have a simple ASIC with a 4 bit core that's highly optimized for calculator operations. Certainly nothing general like a PIC or AVR, maybe something highly obscure like from NEC.

For fun, a while ago I designed my own four bit core to make a simple four function calculator and wrote the code for it. An interesting trade off is whether to include a special instruction to get something done or use multiple, more simple instructions but use more ROM. I don't know what's cheaper in silicon, logic or ROM.

Currently it's only running on a simulator on a PC, but I still plan to create an actual hardware version, with an AVR emulating this P-Code (actually, the first calculator using the 4004 used P-Code ;) ), the challenge to keep everything within 2K of Flash.

edit:
One even more totally outrageous thing I did a couple of years ago, was reimplementing the original HP-35 with a FPGA, from the descriptions and code from the original patents which are very detailed. Unfortunately, I never got round to actually finishing it  ::)
« Last Edit: November 25, 2012, 02:53:57 am by jeroen74 »
 

Offline PaulS

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Re: EEVblog #389 - Casio Calculator Investigation
« Reply #34 on: November 25, 2012, 05:15:19 pm »
Very weird watching this, I have the exact same calculator (fx-260 solar) sitting on my desk. I can tell how bright your lab is, when I do 69! the screen blanks for a few seconds, then it displays the result.
 


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