Author Topic: EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED!  (Read 3704 times)

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Offline NANDBlog

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Re: EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED!
« Reply #25 on: February 03, 2019, 10:35:35 pm »
Since then, 4 layer boards have been pretty much mandatory on all new products.
Pretty much. I havent designed a 2 layer PCB in this decade, unless I could keep the entire bottom side as ground. Most of the stuff I design nowadays require some impedance control, and making a 50 ohm trace on a 1.5mm thick board is just ... inconvenient.
 

Offline mrpackethead

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Re: EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED!
« Reply #26 on: February 04, 2019, 12:19:29 am »
Pretty much. I havent designed a 2 layer PCB in this decade, unless I could keep the entire bottom side as ground. Most of the stuff I design nowadays require some impedance control, and making a 50 ohm trace on a 1.5mm thick board is just ... inconvenient.

yeah, 2.5mm wide tracks are possibly going to make it hard!
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Offline EEVblog

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Re: EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED!
« Reply #27 on: February 04, 2019, 02:05:45 am »
I did watch through the video, and  find it astounding that you can get any work done while simultaneously & continuously talking & reading & responding to that text thing on the left.
If you had 5% of the experience with KiCad compared to Altium this would have been 2 minutes of work.

It was not meant to be a work video, it was just me playing around with KiCAD whilst doing some live chat whilst I just happened to do what I want. It is what it is, and no, you can't effectively get work done whilst doing such a thing, that's why it wasn't about me getting work done in any kind of effective way. You don't have to like that style of video, and that's fine. And there is no point telling me the issues with that, trust me, I know.
BTW, I did make some very valid usability points in the video and someone on the KiCAD team actually thanked me for that.
« Last Edit: February 04, 2019, 02:09:10 am by EEVblog »
 

Offline Neilm

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Re: EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED!
« Reply #28 on: February 04, 2019, 07:55:55 pm »
I can think of only one advantage of two layer boards over four, removing devices during repair is a lot easier.

It is also cheaper. If I can make a board that passes EMC requirements on 2 layers then why would I want to make it 4 layer?  I will admit the only boards I have ever done 2 layer were electrically very simple but I have done them.
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Offline boffin

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Re: EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED!
« Reply #29 on: February 05, 2019, 03:22:00 am »
Would be interesting to see emission differences between same designed boards in which one is smt the other dip.

Wouldn't be any different if the layout remains otherwise identical.
Would anyone be interested in a 6 layer version with grounds on the outside layers?

I'd actually be curious to know if it's any better if you place the power/ground  on the outside layers, and run the data tracks on the buried layers.
 

Offline T3sl4co1l

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Re: EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED!
« Reply #30 on: February 05, 2019, 03:36:54 am »
It would be, though a design like this is still dominated by the size and thru-hole shape of the DIPs used.

An SMT build isn't much better, because you still have via rings on the back side.

In both cases, VCC will be chopped up by inevitable too-good-to-miss-out-on routes, between adjacent and nearby pins.

For DIP, pour around all pins is quite feasible, but hard to maintain for SOIC (plus a via per pin, on average, more or less), and impossible for TSSOP or smaller.  So the rows of pads in the latter case will cause a void in the VCC pour.

Consequently, you'll want to space things out somewhat more than you would even for a 2-layer build (with no particular attention to EMC, that is), which means you aren't saving any size going to four layers here.  So, your motivation is now, just to say you could, more than anything.

The best you could do, is to opt for blind vias ($$).  Then you could build top side components and VCC on top layer, drop vias to Mid1 for priority routes, then route intersections and low priority routes on Mid2+.  Ground vias are regular thru vias or pads.  This would give you 100% solid bottom ground (except for vias), which is excellent shielding for frequencies well above the skin depth of that copper thickness (so, for 2oz, some MHz).

One possible advantage of this kind of construction: the majority of traces/routes are fully encapsulated, making corrosion a somewhat lower risk.  Vias, pads and connecting traces are still vulnerable; vias can be plugged/capped (for another dollarsign more; we're already not caring about fab cost, so what the hey ;) ), and we can do double layer of soldermask, or fill silk everywhere*.  Or both, why not.  And obviously, there's always the boring answer, conformal coating. :P

*Oh that's something I should try some day, do an inverted silk board.  Text can be drawn with inverted labels, and the negative space inbetween can be filled without too much futzing (possibly a polygon can fill it, but I kind of doubt that Altium at least calculates poly clearances that way, on non-copper layers that is, hmm).

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Offline srce

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Re: EEVblog #1176 - 2 Layer vs 4 Layer PCB EMC TESTED!
« Reply #31 on: February 15, 2019, 03:34:37 pm »
A while ago, I was playing around with COMSOL to get a feel for how a 4-layer PCB reduces crosstalk. You can model any combination of materials you want:



Then calculate the electric potential. Here for 2-layer PCB then 4-layer, both with the same thickness (1.6mm):





The closer ground plane on the 4-layer PCB considerably reduces the potential on the parallel wire (from about 0.15V to 0.01V). You can get better results for the 2-layer board by making it thinner.

Going back to the subject of this thread, if we look at the field in the air above too, we can see how that is also reduced:





Obviously, it's better still if you have 6 layers and can sandwich it between two planes:














« Last Edit: February 15, 2019, 04:13:45 pm by srce »
 
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