Author Topic: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown  (Read 29173 times)

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Offline mike1305

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #50 on: May 30, 2013, 10:41:59 pm »
Why don't you two get a room?  :blah: :blah: :blah: :blah:
 

Offline MysteryBunny

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #51 on: May 31, 2013, 05:16:11 am »
exact, this seems to be your problem, and examples below confirms it:

Quote from: MysteryBunny
IMAGINE ORM NOM NOM num num... NO EAT JITTER... NO EAT!!!!!!!!! NO! ONLY EAT GOOD APPLE... Signal is good! YUMMY!
...
HAHAHAHAH!
...
I need a small kitten to hop across my screen now with a fluffy pen to point at the right thing so you can see!!!

so really, you need to got to doctor and/or try to learn how to express oneself.

honestly i don't have issues with english.

The fact you can't understand or answer simple question makes me realize that the only problem here is you,
jumping from topic to topic, posting wired jokes (haha), using (without any reason) bold/italic/caps, etc.
is the best confirmation.


I thought we were having a fun discussion, now you think my jokes are WIRED?! Well ALRIGHT I need to go the doctor to learn how to express oneself! Thank you for the advice <333 I shall go to the doctor right away and not talk about ADCs any more!!!

Also right above us a kitten named mike1305 just posted with his fluffy pen. THAT IS THE BEST CONFIRMATION.

EDIT: i'm nice guy, so i will explain what is your (and not my) problem:

1.) The general quastion was - are these ADCs overclocked and if they are is it bad?
Most of your answer however are generic and have nothing to do with the question, this spefic ADC or what so ever topic related

Quote from: MysteryBunny
In the end the design was rushed with the cheap MAX II

2.) pointless, any CPLD would do the job as well. I would not say "design was rushed", others with similar hardware combination
did they same (Instek/Rigol/Atten/Siglent/UN-T , and that since years, no rush here)

Quote from: MysteryBunny
Look at the graph on FG 19. (Page 20) FG. 29 (Page 22)... You'll see that it's great at 500mhz,
pretty bad accuracy at 1GHZ (even 800mhz sucks), and horrible at 2GHZ... [/i]

3.) pointless, the same DSO with real ADC08D1000 would have still the same bandwidth.

Quote from: MysteryBunny
In fact it even says for DES mode 900mhz is "typical" @ PG. 9
They say a "typical" for non-DES is 1.7ghz @ PG. 8
2GHZ @ +/- 7 DB loss... @ page FG 29. Page 22 of the A/D manual
So You can easily push this to 1GHZ with +/- 3 DB loss... WHILE in DES mode I am guessing?

4.) pointless and mix of things, you can't push anything was already given by the hardware, FPBW have nothing
to do with overclocking, etc.

Quote from: MysteryBunny
This is also 8-bit sampler, it isn't a 14-16 bit precision one either... I can't imagine how terrible it would
be at 2GHZ. It's funny to imagine though...

5.) you don't need to imagine anything here as it is pointless for give topic/questions.

Quote from: MysteryBunny
SnR/attenuation changes with the clock frequency, which people were asking what happens when you overclock it...

so far ok, but then  ...

Quote from: MysteryBunny
Obviously it overclocks to 1GHZ, it can even do 2GHZ ( with problems )...

7.) as answer to my comment to what you "saw" on SNR/Input frequency figure and not from SNR/Sample clock
(which as shown in below didn't exists for you).

Quote from: MysteryBunny
I was making a joke about 14-bit precision non-sampling A/D converters

a joke, the only joke i see is you, but hey, let's continue.

Quote from: MysteryBunny
But how many sample points do you think you'll have in X amount of time with each step before it's digitized?
How accurate is that going to be to your standards? Good enough for you?
But is it good enough for me? I prefer high bandwidth, high sample rate

8.) as comment/answer to given question complettly pointless

Quote from: MysteryBunny
ENOB doesn't change when you overclock
...
The noise is going to be very high from overclocking

9.) You can easy convert ENOB to SINAD and calculate the SNR/THD values. So think back, when SNR is chaning while overclocking
the SINAD and ENOB will change as well. This is pure math (no, you don't need english to get that).

Therefore is your ENOB statement above wrong, but you even not recognized it as you posted about SNR, do you?

Quote from: MysteryBunny
If you know how the A/D steps through in a delta-sigma converter, you will know that noise creates poor samples, but that's really just a filtering/attenuation issue... I had to post that even in the manual it says a 3db loss which isn't a big deal but ...

10.) the question was not about "a sigma-delta converter" but this specific flash converter, but anyway, what you said agin?
Ahh, i see

(1.) Most of my answers are about performance issues with overclocking... (2.) A CPLD is slow and small. You do not know the differences between them and FPGAs... A PLD has a speed grade. This is not debatable...  (3.) This is a different device, you have not read either datasheet

(4.) The bandwidth is "where" the sample is taken. SnR, sample speed, all tie into it... If the bandwidth is bigger, you need to sample more to capture it correctly... A/D converters will step through each part of the waveform to capture it... (5.) There is a difference between a delta-sigma converter and a flash one, please refer to my table I created for this thread

(7.) In an A/D converter, the frequency will affect the entire device... Increasing clock frequency will make the A/D converter sample at more points, and more noise will appear... I wonder why I am even telling you this...

I have linked you the basics of an A/D converter. I can tell you cannot design with them yet... You also don't understand basic RC circuits and waveforms... I can tell you would also struggle with PLLs, as I mentioned the DDR output and it confused you...

(8.) This is most important question in choosing an ADC...

(9.) I was referring to the size of the buffer, which is 8-bits... ENOB RATIO is a NOISE RATIO for digital systems... SIGNAL-TO-NOISE-RATIO is a NOISE RATIO for analog systems... An digital waveform is electrically still analog... They are both noise ratios... So we call it a NOISE RATIO... ENOB in it's short term means PERFECT ENOB which is 7.5 or 8-bits. Perfect ENOB doesn't change... the SnR changes... Both are NOISE RATIOS, so we can settle them as DIFFERENCES BETWEEN THE NOISE AND THE SIGNAL... Please study basic RF design guidelines...

(10.) If you look at the chart, which I created myself, detailing A/D types.... You will see the delta-sigma is the HIGHEST PRECISION one. It has the most complicated decimator stage... In english we call this an "example"...  I created this table so others can follow. FLASH is the opposite. When you see two different examples in english which are opposite, you call them contrasting examples...

I am done educating you for today... I think I have settled every question you could possibly ask ( english questions too ) <333 :)

Also do you like german music?!?!? I own a lot of german music... I see you are german... I like this particular song:
« Last Edit: May 31, 2013, 08:27:38 am by MysteryBunny »
 

Offline Hydrawerk

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #52 on: May 31, 2013, 02:43:55 pm »
Well, how do they produce the demo signals in GDS-2000A?
Amazing machines. https://www.youtube.com/user/denha (It is not me...)
 

Offline amyk

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #53 on: June 02, 2013, 09:13:10 am »
I think the g13 #119 is? a LM119 High Speed Dual Comparator. But thats only a guess.

giving the fact that on the other side of the cable MC10H125 has been used (with diff ECL signals) and no channel offset circuit available
in LA module (but in the POD) i would say they are ECL comparators like ADCMP580 (which have G12 branding btw.), however dual channel version.
At first I thought it was the CLC2500 but given that everything else on the board is AD (there's an AD5339 DAC next to the opamp), maybe not... either way, not cheap parts at all.

Someone in China is selling an ADCMP583 which is only mentioned otherwise here: http://www.alfa-chip.com/files/presentation/Amps.pdf
 

Offline tinhead

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #54 on: June 02, 2013, 10:07:45 am »
it is ADCMP563, datasheet menas G01 but there exists a list on chinese AD site with G13 marking:

http://ezchina.analog.com/servlet/JiveServlet/download/1659-1205/ADI???.pdf

EDIT: seems to not work due chinese characters? anyway, EDN is having as well G13 listed

http://static.ednchina.com/Analog/2009/11/4/ee5ef4a9-e1ad-48fa-aec9-6334aedec844.pdf

« Last Edit: June 02, 2013, 10:10:43 am by tinhead »
I don't want to be human! I want to see gamma rays, I want to hear X-rays, and I want to smell dark matter ...
I want to reach out with something other than these prehensile paws and feel the solar wind of a supernova flowing over me.
 

Offline tinhead

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #55 on: June 02, 2013, 10:11:30 am »
I've emailed the InstekUSA folks to see if they can get an answer.  If/when I get a reply I'll post it.

grego,

did you got anything back?
I don't want to be human! I want to see gamma rays, I want to hear X-rays, and I want to smell dark matter ...
I want to reach out with something other than these prehensile paws and feel the solar wind of a supernova flowing over me.
 

Offline marmad

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #56 on: June 02, 2013, 10:50:19 am »
grego,

did you got anything back?

I'm not sure that we can expect them to say much more than what they've already told Dave. I doubt they're going to say directly that they overclock ADCs or that they use the processor to handle part of the display updating (or, conversely,  that the single FPGA can be slightly overloaded handling both acquisition and updating)
 

Offline grego

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #57 on: June 02, 2013, 01:35:01 pm »
grego,

did you got anything back?

I'm not sure that we can expect them to say much more than what they've already told Dave. I doubt they're going to say directly that they overclock ADCs or that they use the processor to handle part of the display updating (or, conversely,  that the single FPGA can be slightly overloaded handling both acquisition and updating)

This.

I am going to ask for clarification on short/auto memory though.
 

Offline marmad

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #58 on: June 02, 2013, 04:45:22 pm »
I am going to ask for clarification on short/auto memory though.
I suppose... although given that:
a) mike1305 already posted that the Short setting plus 500 ns/div time base gives a sample rate of 200 MSa/s.
b) Segments use 1k record lengths.
c) Short makes much more sense referring to 1k than to 1M.
...I think it's safe to assume it's just a 'misprint' in the manual, and that short = 1k / auto = 1M (or shorter, depending on other channels used, etc).

But you could see very easily yourself by just selecting Short and cycling through the time bases while watching the sample rate indicator. A 1k record length would produce the following rates:
1 - 50ns = 2GSa/s
100ns = 1GSa/s
200ns = 500MSa/s
500ns = 200MSa/s
1us = 100MSa/s
... and so on.


Actually, the Short record length = 1k samples;  it's confirmed in Dave's original video (#474) between 53:20 - 53:40.

And we had assumed that the Instek was doing 80k wfrm/s (and all of it's other fast rates) with a 1M record length. Instead, it appears that it's high speeds are with 1k, which means it's achieving the fastest rate (and some of the other fast rates) with reduced sample rates, thereby lowering it's effective bandwidth at those settings. I'd be curious to see NEW waveform update measurements made with an AUTO record length.

So yes, the GDS-2000A series is a 80k wfrm/s DSO when sampling at 200MSa/s. At the full 2GSa/s, it's not appreciably any faster than the Rigol or Agilent when using it's small 1k record length - and possibly much slower when using equivalent memory sizes.

I don't know... IMO, this verges perilously close to false advertising - especially given the 'misprint' in the manual.
« Last Edit: June 02, 2013, 07:40:08 pm by marmad »
 

Offline Hydrawerk

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #59 on: June 02, 2013, 05:07:26 pm »
Well, this GDS-2000A somehow resembles GDS-806C... This 2004's scope was not cheap, had crap 100MSa/s ADC, was not easy to use, had quite unergonomic front panel and I didn't like it at all.
https://plus.google.com/photos/106264218831814439783/albums/5852286961657081569
Much more I like the even older HP 54600 series, but OK, it has even worse 20MSa/s ADCs...
Amazing machines. https://www.youtube.com/user/denha (It is not me...)
 

Offline marmad

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #60 on: June 02, 2013, 05:32:37 pm »
Well, this GDS-2000A somehow resembles GDS-806C...

I don't really see the comparison.
 

Offline Azhar

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #61 on: June 15, 2013, 09:38:06 am »
Thanks Dave! I enjoyed the tear down as always! thanks for the awesome EEVBlog!  :-+ :-+
 

Offline mamalala

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #62 on: June 23, 2013, 10:22:33 pm »
Maybe i am missing something, but for the life of me, i can't understand the fuzz about the grading/fading stuff for the display. I mean, what does real phosphor do on an analogue scope? The beam hits a spot, which in turn lights up. It the gradually fades out, unless the beam retraces that exact same spot again. Doing that digitally just means to set a pixel to a given value, and then decrease that value on each new capture, unless the captured value would "hit" that pixel again, in which case it gets set to the start value again.

I mean, just look at old computer demos, the "blob" effect basically does just that (yes, i know, not directly comparable, but the outcome is the same). Assuming a 640x480 display (just as an example), we have 640x480x3 = 921.600 bytes, x50 fp/s = 46.080.000 bytes per sec, so a 50MHz clock would be enough if the FPGA would "brute force" the grading for each display pixel in a linear fashion and only does 1 byte at once. Using 3 bytes at once improves that, limiting the color-space improves it even more. After all, it would just need a pixel=old_pixel-1 to do the fading, or in case of a "retrace" it would be a simple old_pixel=max_value.

The FPGA can readily prepare 8, 9 or 10 bits per pixel, as far as intensity is concerned. That would result (assuming a 50Hz display rate) in roundabout 15k, 30k or 60k waveforms per second. All it has to do is to sample the waveform 256, 512 or 1024 times and increase the values for the pixels that are "lit". That way the main controller already gets a shaded bitmap of the waveform. This is the used to be combined with whatever the main controller already has in its image memory with a way mentioned above. Heck, i can think of several ways to implement that stuff rather efficiently, especially if you have direct control of the address lines and stuff from the memory...

What am i missing?

Greetings,

Chris

Edit: Sorry, i meant the "shade-bob" effect.
« Last Edit: June 24, 2013, 08:08:17 am by mamalala »
 

Offline amyk

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #63 on: June 24, 2013, 11:49:25 am »
What am i missing?
The fact that scope firmware programmers aren't from the demoscene?
 

Offline marmad

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #64 on: June 24, 2013, 12:01:44 pm »
What am i missing?

A lot of other stuff that happens. Forget for the moment the amount of data which just has be to shifted - from the ADC to sample memory (which stores a copy of the last waveform captured) and from sample memory to display memory - but apart from the intensity grading, there is decimation, other acquire modes (peak detect, high-res, etc), possible anti-aliasing, measurements, etc.

I'm not saying it's the most complicated thing in the world - but with current technology, it appears to require more than a single FPGA (or else special silicon like Agilent's ASIC) - in order to do it seamlessly.
 

Offline mamalala

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #65 on: June 24, 2013, 12:03:58 pm »
What am i missing?
The fact that scope firmware programmers aren't from the demoscene?

Uh, i know that already. My point was that fading/phosphor emulation shouldn't be that hard to implement since similar effects have been implemented decades ago on rather slow machines. Considering that FPGA's are quite fast and can do stuff in parallel rather nicely, it should be a rather simple thing to implement nowdays.

Greetings,

Chris
 

Offline mamalala

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #66 on: June 24, 2013, 12:12:04 pm »
What am i missing?

A lot of other stuff that happens. Forget for the moment the amount of data which just has be to shifted - from the ADC to sample memory (which stores a copy of the last waveform captured) and from sample memory to display memory - but apart from the intensity grading, there is decimation, other acquire modes (peak detect, high-res, etc), possible anti-aliasing, measurements, etc.

Sure, but wouldn't all that be done before the "displayable" waveform? My thinking is that the signal would be processed and then stored in memory. Without any grading, that would be the end of it and out to the display it goes. With grading, those results would "simply" be added to the existing data (either with or without first doing a "fade out" on the existing pixel), and after N repeats of all that goes to the display.

But then, what do i know ;) At least something like that would be the way i would first try to implement it.

Greetings,

Chris
 

Offline marmad

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #67 on: June 24, 2013, 12:18:45 pm »
Sure, but wouldn't all that be done before the "displayable" waveform?
Hi Chris,

Some of it happens before - but some of it is often combined with the grading (like decimation for the display).

Here's a nice link showing some different methods DSOs manufacturers have come up with for implementing it. It's educational  ;)

Best,

Mark
 

Offline marshallh

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #68 on: June 24, 2013, 08:30:40 pm »
What am i missing?
The fact that scope firmware programmers aren't from the demoscene?

Truth. If they gave a damn and were halfway competent they could do it proper.
Shadebobs on a pentium I...
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BGA soldering intro

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Offline ResR

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #69 on: June 25, 2013, 03:16:56 pm »
Not a big news but from the video at 08:52? the lower two pins are shorted to the pins at the other side with "stiching", mate, that is how it is detected of being connected.
 

Offline andersm

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Re: EEVblog #475 - GW Instek GDS-2000A Oscilloscope Teardown
« Reply #70 on: June 25, 2013, 05:46:34 pm »
The Chinese sure love their DSPs, but I wonder who will be the first to try using a tablet CPU and crunch the graphics using OpenGL and shaders.


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