Author Topic: EEVblog #496 - What Is An FPGA?  (Read 58701 times)

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Offline poorchava

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Re: EEVblog #496 - What Is An FPGA?
« Reply #100 on: July 23, 2013, 05:53:15 am »
FPGAs have some serious limitations. Consider the following task: there is a 48-bit counter incrementing by one every clock cycle and compared against a set value. Simple, right? Design has to have zero latency, (meaning: pipelining is not allowed.)

Code: [Select]
always@(posedge clk)
begin
counter<=counter+48'b1;
if (counter==set_value) out_compare<=1;
else out_compare<=0;

NO.

for one: most recent stuff (Virtex 7, Spartan 6 etc) have 6 input LUTs which means that comparison of two 48-bit values will be synthesized as 16 LUTs, each performing comparison of 3 bits from one value and 3 from the other, then results of those 16 LUTS are ANDed by another 3 LUTs and then this one is ANDed by another LUT. So you have 3 levels of logic which pretty much limits you to below 150 MHz. Now you add a binary counter. Synthesize that in FPGA fabric and you go like 'w00t, 40MHz'. That's because due to carry logic setup time of all your DFFs (48 of them) adds up. Ok, but there is a DSP48A1 on a Spartan6, why not use that? You can, it needs about 2 clock cycles to reload to certain value, start counting down and spit out first valid result.


When you can pipeline stuff at will, you can get your 300Mhz or whatever, but when this is not and option, things start to get hard.



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Offline iva

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Re: EEVblog #496 - What Is An FPGA?
« Reply #101 on: July 23, 2013, 05:05:06 pm »
coincidentally, SparkFun just released an FPGA dev board for $75 US:
https://www.sparkfun.com/products/11953

These are not "development boards", these are just breakout boards for Spartan or Cyclone, they may have clock source, JTAG connector, perhaps something else, but calling that a complete dev board will be little bit of stretch IMHO.

Dev board is opposite - it meant to be used separately and extensions are added to dev board itself.
I respectfully disagree but I think we're getting philosophical here.
Can you start and do development using the board linked above?
Well, yes you can and you don't really need much more if you don't want to.

I consider a breakout board something really bare-bone which, for example, gives you easier access to high density components and doesn't need anything else.
Something like this, to be clear (one of the first google image hits):
 

Offline c4757p

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Re: EEVblog #496 - What Is An FPGA?
« Reply #102 on: July 23, 2013, 05:10:21 pm »
I agree. IMHO, if it has more stuff on it than just decoupling capacitors (and that's only because they must be in a certain location), it's not a breakout board. That looks very much like a development board to me. It even has a programmer built in. I've got a little eBay FPGA board that has just a Cyclone IV, regulators, an oscillator, and an EEPROM, and I'd even call that a dev board. Hell, I still think it's one even after I've disabled the crappy oscillator and unhappy, hot regulators, because it has an EEPROM and JTAG header.
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Offline JoeyP

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Re: EEVblog #496 - What Is An FPGA?
« Reply #103 on: July 23, 2013, 06:00:51 pm »

2. Internal constraints - Low-cost fpgas ($<200-300) have Fmax limitations usually around 130-150mhz. It gets very hard to clock logic faster than that. If you have a small functional unit you could spend time pipelining and optimizing by hand (and in the case of xilnx ISE, manually placing elements sometimes) and approach 200mhz. For something more complex like a 5stage pipelined MIPS core you would be lucky to break 60-70mhz. The process of hand tuning the code/constraints/routing until you achieve your desired clock speed in that unit is called "closing timing". You will either have gap/slack in propagation delay.


Not sure which brand of FPGAs you refer to, but this sounds like very dated info. For years I've been doing 200-250MHz synchronous designs in Altera Cyclone and Lattice ECP family FPGAs in the sub $30 range. The silicon in these parts typically has per/element Fmax specs in the 300-400MHz+ range. Hand placement is not necessary to get desired Fmax, but I'll occasionally use it to assure off-chip timing.

Regarding the difference between FPGAs and CPLDs, it's becoming a moot point. Modern "CPLDs" (e.g. Altera Max parts) are essentially tiny FPGAs with on-board configuration memory. It took a while for Altera to admit this, but even their sales reps now freely concede this point.
 

Offline Rasz

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Re: EEVblog #496 - What Is An FPGA?
« Reply #104 on: July 23, 2013, 06:21:04 pm »
Regarding the difference between FPGAs and CPLDs, it's becoming a moot point. Modern "CPLDs" (e.g. Altera Max parts) are essentially tiny FPGAs with on-board configuration memory. It took a while for Altera to admit this, but even their sales reps now freely concede this point.

Are you sure about that? If they were same die FPGAs with on board flash it would be logical to give them option of loading config with jtag without flashing, afaik this is not possible (and resulted in many cplds dying while being used to learn VHDL)
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Offline AndyC_772

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Re: EEVblog #496 - What Is An FPGA?
« Reply #105 on: July 23, 2013, 07:04:32 pm »
How did you manage that? I don't think I've ever managed to damage a CPLD during debugging.

Offline JoeyP

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Re: EEVblog #496 - What Is An FPGA?
« Reply #106 on: July 23, 2013, 07:16:12 pm »
Regarding the difference between FPGAs and CPLDs, it's becoming a moot point. Modern "CPLDs" (e.g. Altera Max parts) are essentially tiny FPGAs with on-board configuration memory. It took a while for Altera to admit this, but even their sales reps now freely concede this point.

Are you sure about that? If they were same die FPGAs with on board flash it would be logical to give them option of loading config with jtag without flashing, afaik this is not possible (and resulted in many cplds dying while being used to learn VHDL)

Yes. The sales reps will even tell you so if you challenge them on it. In the old days, CPLDs had slightly different architectures from FPGAs, so there were applications where one might make sense over the other (from a pure logic point of view - excluding volatility considerations). These days, if you look at say Altera MaxV, the logic cells are virtually identical to a same-generation FPGA. They're even starting to include the other features previously limited to FPGAs such as PLLs etc. The main benefit to a CPLD these days is the non-volatility. For some applications the faster internal configuration time for these types of CPLDs vs an FPGA with external configuration (which tend to be serial, and much slower) may also be a benefit. Yes, they could certainly have chosen to include external (volatile) reconfiguration for CPLDs, but that would have blurred the line between CPLD/FPGA still further, and for the moment they seem to want to keep it distinct (probably for marketing purposes).
 

Offline MasterOfNone

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Re: EEVblog #496 - What Is An FPGA?
« Reply #107 on: July 23, 2013, 07:54:45 pm »
Last time I looked Xilinx's ISE integrated ABEL into its design flow, although they no longer actively promote it, its still perfectly usable - particularly for Hardware designers who I suspect are still the main users. Metastability is still an issue out there today with VHDL. IMO ABEL's main problem was that VHDL came along as a standardized open language while most of the HDL's back in the 80's and 90's were somewhat proprietary. By version 5 Abel was doing some pretty good stuff. Today we really only have Xilinx, Lattice and Altera who swallowed most of the smaller players long ago including DataIO. The ones they didnt swallow died.. along with their languages.

I should have said PSHDL reminded  me of early versions of ABEL, since I didn’t really follow it after the Nineties. I'm not saying that early versions of ABEL were crap, it’s just that it took a lot of effort to develop designs that used multiple state machines that operated on different clocks. Using it for address decoding and generating chip selects was fine. So after briefly looking at PSHDL I was just enquiring how they have solved those problems, since it reminded me of early versions of ABEL where everything operated in parallel and you had to use state machines for sequential processing. 
In Verilog or VHDL you can usually do timing simulations to help identify potential problems, these tools took a lot of time and effort to develop and are tied to the FPGA device being used. I’m not sure how they were going to do this with PSHDL.
Also I don’t think ABEL is still supported by Xilinx (it isn’t in 13.2) and when it was supported (v10 or v11), I’m not sure if  it could be use it for anything apart from CPLD’s, but I might be wrong. 
Anyway I’m not claiming to be some HDL expert in any language, I was just wandering how engineers are going to develop large complex FPGA designs with PSHDL.
 

Offline Alexei.Polkhanov

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Re: EEVblog #496 - What Is An FPGA?
« Reply #108 on: July 23, 2013, 09:25:19 pm »
I consider a breakout board something really bare-bone which, for example, gives you easier access to high density components and doesn't need anything else.
Something like this, to be clear (one of the first google image hits):

I think that is simply called an SMT adapter. Problem with adapters is that they violate certain design rules such as proximity of decoupling capacitors to respecting pins. At least first set of caps should be close, larger caps that added to compensate for self-resonance can be moved further but it is very beneficial if you can add bypass caps on opposite side of board as close as possible to via that goes straight from the power pin. Other signal integrity issues can be introduced by SMT adapters as well. I tried to use through hole caps with one pin almost completely cut off and soldered right to the pin on opposite side of prototyping board. I had moderate success with that. I have few good photos - will post later when I will get home.
« Last Edit: July 24, 2013, 12:28:21 am by Alexei.Polkhanov »
 

Offline marshallh

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Re: EEVblog #496 - What Is An FPGA?
« Reply #109 on: July 23, 2013, 09:31:23 pm »
He's right, MAX II and MAX V cplds are sram based, config data is loaded from an EEPROM on powerup.
They are only rated for about 100 program cycles.
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Offline c4757p

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Re: EEVblog #496 - What Is An FPGA?
« Reply #110 on: July 23, 2013, 09:32:34 pm »
They are only rated for about 100 program cycles.

I've noticed this. Is that just a really, really conservative rating, or do they actually tend to fail after that many? :o
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Offline Alexei.Polkhanov

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Re: EEVblog #496 - What Is An FPGA?
« Reply #111 on: July 23, 2013, 09:33:20 pm »
Regarding the difference between FPGAs and CPLDs, it's becoming a moot point. Modern "CPLDs" (e.g. Altera Max parts) are essentially tiny FPGAs with on-board configuration memory. It took a while for Altera to admit this, but even their sales reps now freely concede this point.

Are you sure about that? If they were same die FPGAs with on board flash it would be logical to give them option of loading config with jtag without flashing, afaik this is not possible (and resulted in many cplds dying while being used to learn VHDL)
Altera MAX V CPLD datasheet states that you can reprogram it only 100 times.

 

Offline Alexei.Polkhanov

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Re: EEVblog #496 - What Is An FPGA?
« Reply #112 on: July 23, 2013, 09:37:17 pm »
They are only rated for about 100 program cycles.

I've noticed this. Is that just a really, really conservative rating, or do they actually tend to fail after that many? :o
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Offline Rasz

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Re: EEVblog #496 - What Is An FPGA?
« Reply #113 on: July 23, 2013, 10:42:38 pm »
cplds also tend to be cheaper, maybe its a market segmentation and there is a programming counter like in inkjet printers :)
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Offline JoeyP

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Re: EEVblog #496 - What Is An FPGA?
« Reply #114 on: July 24, 2013, 12:06:13 am »
cplds also tend to be cheaper, maybe its a market segmentation and there is a programming counter like in inkjet printers :)

I think it is definitely market segmentation. I believe that's why they continue to push the CPLD terminology, instead of calling them what they are - FPGAs with onboard configuration memory.

I don't think they simply pop in one of their FPGA dice though, because to keep cost down they probably need to use much smaller silicon real-estate. The largest "CPLDs" are still quite a bit smaller than the smallest FPGAs (at least from Altera).

As far as a programming counter, it's not consistent. Doesn't die at exactly 100 cycles, or at same count for every part. My bet is that they use a process for the EEPROM that is compatible with the logic die, so that it can all be done on a single piece of silicon - but just guessing there. It was not unusual for EEPROMs to have such limits to programming cycles in the old days, so maybe just using old (but coincidentally compatible) technology.

I did some tests a while back on some modern EEPROMs rated at 1M cycles. Found they would begin to fail at anywhere from 2M to 10M cycles, and found it to be very vendor-dependent. Faster programming parts predictably fail with fewer cycles because they use higher programming voltages internally.
 

Offline romovs

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Re: EEVblog #496 - What Is An FPGA?
« Reply #115 on: July 24, 2013, 01:46:08 am »
I have few good photos - will post later when I will get home.

Where did you get those tiny sticky labels?
 

Offline Alexei.Polkhanov

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Re: EEVblog #496 - What Is An FPGA?
« Reply #116 on: July 24, 2013, 02:21:29 am »
I have few good photos - will post later when I will get home.

Where did you get those tiny sticky labels?
I printed them on printer on self adhesive paper.



 

Offline bitwelder

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Re: EEVblog #496 - What Is An FPGA?
« Reply #117 on: July 24, 2013, 05:48:55 am »
Anyway I’m not claiming to be some HDL expert in any language, I was just wandering how engineers are going to develop large complex FPGA designs with PSHDL.
About PSHDL, just yesterday on YouTube CCCen channel they published the lecture on "Programming FPGAs with PSHDL" from SIGINT13 conference:
I haven't had time to watch it yet, but usually CCC does good stuff.
 

Offline MasterOfNone

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Re: EEVblog #496 - What Is An FPGA?
« Reply #118 on: July 24, 2013, 09:03:57 pm »
Anyway I’m not claiming to be some HDL expert in any language, I was just wandering how engineers are going to develop large complex FPGA designs with PSHDL.
About PSHDL, just yesterday on YouTube CCCen channel they published the lecture on "Programming FPGAs with PSHDL" from SIGINT13 conference:
I haven't had time to watch it yet, but usually CCC does good stuff.


Just watched it and all my questions have been answered. Basically PSHDL isn’t aimed at asynchronous designs with multiple clocks, it's aimed at synchronous designs with a single clock.
PSHDL is aimed at the educational/hobbyist market and it isn’t trying to replace VHDL or Verilog, its aim is to become the Arduino for FPGA’s. 
 

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Re: EEVblog #496 - What Is An FPGA?
« Reply #119 on: July 25, 2013, 07:07:25 am »
Hi everyone:)

In the last FF video i criticized Dave for the boring FPGA tutorial (And yes, i still think it was boring). He answered "why don't  you make own  tutorial video, and show how it is done"
Well, the challenge was indeed accepted. Here is the result:



I am not claiming to do any competition  with Dave, but is think if the video will get some positive feedback, i will do more tutorials.
I am not professional and  on the learning curve by myself, but is think i can teach  peple a lot of basics, since i have good experience with being a tutor in real life.



 

Offline EEgalitarian512

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Re: EEVblog #496 - What Is An FPGA?
« Reply #120 on: July 25, 2013, 09:19:37 am »
Hi Dave. Thank you so much for this video on FPGAs. If it feels right, I would heartily encourage more videos on this topic - especially from a logic design viewpoint. I am more interested in the 'schematic capture' aspect - and not so much from the programming / VHDL / Verilog side of things. I am equally interested in CPLDs - again from the schematic side.
 

Offline Rasz

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Re: EEVblog #496 - What Is An FPGA?
« Reply #121 on: July 25, 2013, 02:06:34 pm »
Hi everyone:)

In the last FF video i criticized Dave for the boring FPGA tutorial (And yes, i still think it was boring). He answered "why don't  you make own  tutorial video, and show how it is done"
Well, the challenge was indeed accepted. Here is the result:


I am not claiming to do any competition  with Dave, but is think if the video will get some positive feedback, i will do more tutorials.
I am not professional and  on the learning curve by myself, but is think i can teach  peple a lot of basics, since i have good experience with being a tutor in real life.

There was a problem when rendering that video, you put elevator music instead of voice track = definition of boring.
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Offline Alexei.Polkhanov

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Re: EEVblog #496 - What Is An FPGA?
« Reply #122 on: July 25, 2013, 05:41:20 pm »
There was a problem when rendering that video, you put elevator music instead of voice track = definition of boring.
Totally agree with that!!!
 

Citizen

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Re: EEVblog #496 - What Is An FPGA?
« Reply #123 on: July 25, 2013, 06:19:43 pm »
Quote
There was a problem when rendering that video, you put elevator music instead of voice track = definition of boring.

Your definition of boring is pretty local;)
 For me smooth/electro jazz (you call it elevator music)   is just a not annoying background music, which keeps your brain active while not dragging any attention to itself  (like in case with classical music).

In my opinion, the subtitle like explanation has many advantags , especially while explaining  a programming  language.

1. The viewer can  pouse video at any time, read what i "said" and compare it with code..
2. You can put additional annotations in it,text highlighting, syntax  or small code examples.
3. If the viewers  native language is not English(which happens pretty often on youtube), it is much easier to understand such tutorials.
 

Offline MacAttak

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Re: EEVblog #496 - What Is An FPGA?
« Reply #124 on: July 26, 2013, 12:28:06 am »
Hi everyone:)

In the last FF video i criticized Dave for the boring FPGA tutorial (And yes, i still think it was boring). He answered "why don't  you make own  tutorial video, and show how it is done"
Well, the challenge was indeed accepted. Here is the result:
....

I started to watch it, but it was REALLY hard to follow. Reading the captions at the bottom of the video makes it impossible to see what you are actually doing in the UI above. In order to grasp it, I need to watch and read the text, then rewind and watch the same clip again while paying attention to the video itself.

This really needs voiceover.

BTW, one of our core services is online training videos. Not a single one uses text captioning in lieu of voiceover. There is a reason for that - when someone is watching you do something with a code editor they can't also be reading text at the same time.
 


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