Author Topic: EEVblog #532 - Silicon Chip Wafer Fab Mailbag  (Read 51832 times)

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Offline poorchava

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #25 on: October 08, 2013, 06:09:46 am »
As for attaching die to the leadframe: quite often the die is being soldered to the leadframe. And that solder is almost pure lead (like 89% or something IIRC). And those are RoHS parts. It's just that there's an exemption in RoHS for die attach :).
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Offline SArepairman

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #26 on: October 08, 2013, 06:32:14 am »
Favourite part


with only the hood on he looks like Lawrence of Arabia
 

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #27 on: October 08, 2013, 08:03:35 am »
Wafers are cut whit a mechanical saw? is that real?
 

Offline vk2hmc

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #28 on: October 08, 2013, 08:19:17 am »
Vincent - Thanks for sending the m o s t  a w e s o m e s t  mailbag yet!
Dave - now that is something we don't see every day!
I am off to watch it for the 4th time now ;)

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Offline nack

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #29 on: October 08, 2013, 09:23:52 am »
Awesome episode!
 

Offline Razor512

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #30 on: October 08, 2013, 10:37:41 am »
When can we expect the cost and size to come down to a point where we can do a low volume fab at home?

@free_electron, even with those cost, don't you find it insane how high the cost is for flash memory?
for example, a company will make a 64GB SDXC card and then charge an arm and a leg price of $42


(you could just imagine CEO's laughing all the way to the bank when due to a lack of competition, they can charge prices like this for a product that likely has an extremely high yield and a low overall manufacturing cost).
 

Offline pe4mwt

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #31 on: October 08, 2013, 10:39:50 am »
Nice video, I wear those suits to work everyday, only mine is blue, and in our factory the socks are just that: socks. We wear normal ESD shoes over them. No zipper and no pink stuff either ;). But hey, we don't produce chips, we only produce the 30 to 130 million euros costing lithography machines the chip manufacturers are using to expose the chips.

If you think those 300 mm wafers are big just wait until the 450 mm technology is ready. They are working on that now all around the world. I don't think I am going to carry those wafers, 25 in a row, in one foup. Curious how they are going to solve that. The automatic fabs will probably need even better tracks along the roof for carrying those heavy foups.

Vincent is actually a dutch guy living and working in the US. And yes he wrote some interesting books. I have one of those over here, really nice. If you'd seen all his equipment in his garage then you know even Dave would be jealous. At least I am...

Thanks for the video Dave and Vincent thanks for sending Dave all that nice stuff!
« Last Edit: October 08, 2013, 10:41:37 am by pe4mwt »
 

Offline nack

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #32 on: October 08, 2013, 10:41:06 am »
@Razor512
Expensive? Just because it's tiny doesn't mean it should be cheap! Have you really watched the videos of Dave and lithography in general?

« Last Edit: October 08, 2013, 10:53:19 am by nack »
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #33 on: October 08, 2013, 10:42:46 am »
Wafers are cut whit a mechanical saw? is that real?
Yes. They use a carbide blade coated with diamond dust.

http://americas.micross.com/products-services/die-wafer-services/wafer-sawing.stml

The wafer is not very hard to saw. So the carbide is not really needed. Its just that carbide is very hard so they can make a very thin blade that will not wobble. You want the cut to be a sfine as possible as it means you can put dies closer and thus more per wafer which brings the cost per chip down.
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Offline Razor512

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #34 on: October 08, 2013, 10:46:00 am »
Why are the wafers round instead of square?  wouldn't it be more efficient to have then in a square shape so that more complete dies can be placed in the same area, thus better utilizing the same surface area? (couldn't they somehow use a square compartment when making the silicon ingots? )

and @nack I have watched a few videos, and can see where some of the fixed cost come from, but it is hard to figure out where the rest of the cost comes from.
« Last Edit: October 08, 2013, 10:53:45 am by Razor512 »
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #35 on: October 08, 2013, 11:04:57 am »
When can we expect the cost and size to come down to a point where we can do a low volume fab at home?

@free_electron, even with those cost, don't you find it insane how high the cost is for flash memory?
for example, a company will make a 64GB SDXC card and then charge an arm and a leg price of $42


(you could just imagine CEO's laughing all the way to the bank when due to a lack of competition, they can charge prices like this for a product that likely has an extremely high yield and a low overall manufacturing cost).
Not really. Remeber that you 64 gig card has 4 to 8 chips in it... The waferfab has to amortized on it. The development cost of the flash chip is practicaly zilch as it is a repetitive structure and those are created by specialised software. We have special software where you tell i want an array this wide, that tall and split in sectors of that large and this software goes off and creates the entire layout. So thats not the problem. It's the cost of the 45nM waferfab , and all the process equipment
Lithography is hell at such small structures. The mask image is being pre-distorted. A straight line on the wafer is not a straight line. Here is why:

Lets say you want two lines , each 45nanometer wide, running parallel at a distance of 45nanaometer from each other (remeber we run at 18 nanometer these days !)
You will expose the photolayer with ultraviolet light . Ultraviolet light has a wavelength of 400nanometer downto 10 nanometer... Making uv at 10nanometer is very very difficult. You need to excite some special gas mixes using a magnetron to get that stuff. Besides, the photomask material is sensitive in only a narrow band. For printed circuit boards this is 320 nanometer.
For chips we have resists that are sensitive to deep-uv. Around 150 to 100 nanometer.
So how do you create such small structures if the wavelength of the light is larger ? Its like cutting a line with a knife that is wider than the cut ! Solution : you cut sideways (under an angle)
This is accomplished by pre distorting the mask at an interval of the wavelength used. I'm trying to find a picture of such a mask... Ive seen em on the internet but i can't find it right now. They have a special name for this technique.
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Offline 6thimage

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #36 on: October 08, 2013, 11:06:55 am »
Why are the wafers round instead of square?  wouldn't it be more efficient to have then in a square shape so that more complete dies can be placed in the same area, thus better utilizing the same surface area? (couldn't they somehow use a square compartment when making the silicon ingots? )

Silicon wafers need to have the same crystal orientation, referred to as things like 100 and 110, so a 'batch' of silicon wafers is created by heating up a pot of silicon, then a single crystal is placed into the pot and slowly pulled away. As it is pulled away it is rotated so that it increases in size, to produce a cylinder, this cylinder is then cut to produce the individual wafers - hence why you can't get square wafers. Wikipedia has quite a good page on it http://en.wikipedia.org/wiki/Wafer_(electronic).
 

Offline nack

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #37 on: October 08, 2013, 11:07:31 am »
Why are the wafers round instead of square?  wouldn't it be more efficient to have then in a square shape so that more complete dies can be placed in the same area, thus better utilizing the same surface area? (couldn't they somehow use a square compartment when making the silicon ingots? )

and @nack I have watched a few videos, and can see where some of the fixed cost come from, but it is hard to figure out where the rest of the cost comes from.

Wafers are round due to their production process:
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #38 on: October 08, 2013, 11:14:05 am »
Why are the wafers round instead of square?  wouldn't it be more efficient to have then in a square shape so that more complete dies can be placed in the same area, thus better utilizing the same surface area? (couldn't they somehow use a square compartment when making the silicon ingots? )

and @nack I have watched a few videos, and can see where some of the fixed cost come from, but it is hard to figure out where the rest of the cost comes from.
There is multiple reasons for that.
First is the pulling of the ingot.
They start with a seed crystal, no larger than a pea, of which the exact crystal orientation is known.
This is mounted on a rod and spun around slowly in a vat containing pure liquid silicon.
As they pull this upward , silicon atoms will stick to the seed crystal and they will orient themselves in the same cristalline structure.

Remeber that this whole silicon i got is 1 massive crystal without a single defect !

So the ingot is round by itself due to the growth process.
Trimming the edges of the circle doesnt make sense. You spent a lot of money to create a slice of hyper pure crystal and you are going to cut off 1/3 and throw that away. Let's use it.

Two: square wafers would have sharp corners. Bump a corner and shatter the wafer. Eveen cracking a stine fragment off the tip of a corner would create silicon dust everywhere ... Dust is your enemy.
No problem with a round wafer. It wont snag...

Three
Many reactions aredone using plasma. To mix the chemicals in the plasma very evenly you need to stir it... How do you stir a cloud of ionized very reactive gas ? With a magnetic field. Plasma reacts to magnetic field. So we have multiphase coils around the reactor chamber creating a spinning as wel as a lateral moving magnetic field. That makes a uniform mixture of the reacting agents giving a uniform process across the wafer.

Spin something and ... It becomes circular... Square reactors would be very hard to get stuff in the corners.... Circular reactors dont have corners.

There is reason to all the madness going on in this industry. It is fascinating to look at all the trickery involved in getting this to work at all !
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Offline Winston

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #39 on: October 08, 2013, 02:39:22 pm »
I think I've posted this here somewhere before, but it's especially appropriate for this subject:

IC Die Photography

http://diephotos.blogspot.com/
 

Offline algorath

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #40 on: October 08, 2013, 03:52:11 pm »
awesome stuff. are there any factories/test facilities like this in china/taiwan/korea? or are they just on the manufacturing site of things?
can you give us a factory tour some time freeelectron or is that shit highly classified? ^^
 

Offline vsq

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #41 on: October 08, 2013, 03:58:17 pm »
I think I've posted this here somewhere before, but it's especially appropriate for this subject:

IC Die Photography

http://diephotos.blogspot.com/

Beautiful! Simply awesome! Thanks!
 

Offline walshms

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #42 on: October 08, 2013, 03:59:12 pm »
The mask image is being pre-distorted. A straight line on the wafer is not a straight line. Here is why:

Lets say you want two lines , each 45nanometer wide, running parallel at a distance of 45nanaometer from each other (remeber we run at 18 nanometer these days !)
You will expose the photolayer with ultraviolet light . Ultraviolet light has a wavelength of 400nanometer downto 10 nanometer... Making uv at 10nanometer is very very difficult. You need to excite some special gas mixes using a magnetron to get that stuff. Besides, the photomask material is sensitive in only a narrow band. For printed circuit boards this is 320 nanometer.
For chips we have resists that are sensitive to deep-uv. Around 150 to 100 nanometer.
So how do you create such small structures if the wavelength of the light is larger ? Its like cutting a line with a knife that is wider than the cut ! Solution : you cut sideways (under an angle)
This is accomplished by pre distorting the mask at an interval of the wavelength used. I'm trying to find a picture of such a mask... Ive seen em on the internet but i can't find it right now. They have a special name for this technique.

I think I can help you here, Vincent.  I remember learning about this a while ago.

You're operating beyond the diffraction limits, so the masks are made to take advantage of interference; using the wave-like character of light, the masks are designed such that the resulting image is the one you actually want.  There's simply no way that you could make 18nm structures with 320nm light unless you took advantage of interference.  If you examine the masks themselves, you'd find that the image on them doesn't really look like the image that gets laid down on the photoresist.

It's really pretty amazing that we (the species) have been able to figure all of this out.
 

Offline KerryW

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #43 on: October 08, 2013, 04:04:01 pm »
I worked in the industry back in the 90's making equipment to pull the dies from the completed wafers.  I worked for a company called Laurier, mostly on their DS3000 machines.

Some wafer testers marked bad die with ink dots, but most of them generated a map with a status for each die. 
The machine had an anvil with a plastic disc at the top with holes in it for 1 or more needles to poke through and holes for vacuum.  It had an arm with a collet with a vacuum hole in it.  An XY stage moved the wafer around and a video camera sat over the anvil.  Another XY stage and camera were on the output, which normally held a number of waffle packs or gel packs.
We would read the map, locate the test dies (the ones that were different), then move to the first pickable die.  Align to the camera, pull a vacuum to seat the die on the anvil, bring the collet to the die and lower it, bring the needle up to pull the die from the membrane, then raise the arm and move to the output and place the die in the next available pocket of the appropriate waffle pack.

Die sizes ranged from ~1" sq to 7 mils (178 microns).  For one project, we had to pick 10 mil (254 micron) dies, but we had to read a 4 digit serial number printed on the die before picking it.

The machines cost $150K to $250K, and could pick and place up to 2000 die per hour.
One accurate measurement is worth a thousand expert opinions
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Offline TiN

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #44 on: October 08, 2013, 04:35:15 pm »
Great stuff, thanks Dave and Vincent! It's always amazing to see how the magic happens.
Also those nanometer probes, I guess, you cannot even breathe on it, or it will bend  :-DD :scared:

I had a question tho, is there any widely available solvent or chemical which can be used to remove/dissolve package epoxy of usual chip packages? I like taking photos of electronic gear, and tried couple ways to get die shots, but either shatter die or it gets badly damaged when trying remove epoxy mechanically. I have some dead modern CPUs and GPUs, which might be interesting to look at (lots actually, even some latest multi-billion transistor count chips) :)

Best one so far is nvidia geforce4 Ti4200 GPU die shot, which i got off it's BGA package by heating it and cracking open.
Pity it's covered with metal mask in front, so cannot see inner layers beauty.



« Last Edit: October 08, 2013, 04:37:19 pm by TiN »
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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #45 on: October 08, 2013, 04:35:32 pm »
awesome stuff. are there any factories/test facilities like this in china/taiwan/korea? or are they just on the manufacturing site of things?
can you give us a factory tour some time freeelectron or is that shit highly classified? ^^
Plenty. TSMC is Taiwan. UMC too. Korea has massive fabs from Samsung, Hynix , and others.

But you are not going to get in. It's not so much that stuff is classified ( some of it is. forget taking pictures , let alone taking a smartphone or cellphone inside ) but the problem is that us sack of bones and meat bags are walking dust generators...
If they could, wafer fabs would be completely void of human presence.

@walshms. that's : interference lithography. that is the term that eluded me. It's been so long since i've been on that side of the entire semiconductor world... i've forgotten half of it..

it is like i described. even thought the knife blade itself is too wide, by putting it under 45 degrees you can make a cut smaller than the width of the knife. in the lithography process they use two light bundles , 90 degrees apart and 45 degrees offset from the plane. so if the plane is horizontal , one is shining left to right under a 145 degree angle, the other shines right to left under a 45 degree angle. Where the wavelength interferes with each other you get a standing wave ( i think. it's like the famous double slit experiment. http://en.wikipedia.org/wiki/Double-slit_experiment )
in the peaks you have light , so you are exposing the photoresist. In the valley there is absence of light so no exposure.

Instead of slits they use complex patterns the make the light beams coming from opposite directions interfere with each other and create the correct shadowed areas in the form of the wanted structure. Totally batshit crazy stuff.
ASML is the big name there.

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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #46 on: October 08, 2013, 04:41:27 pm »
I had a question tho, is there any widely available solvent

Fuming nitric acid. But that is VERY dangerous stuff. And you need to heat it... which makes it even more dangerous.
That is how it is done in the industry. solvents don't work. The chip casing material is not soluble.

https://www.sumibe.co.jp/english/product/it-materials/epoxy/sumikon-eme/index.html

That is what is used for chip bodies. Sumitomo is by far the largest manufacturer of that stuff.
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Offline TheWelly888

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #47 on: October 08, 2013, 04:42:20 pm »
Most Awesome Mailbag - Thanks Vincent!

You can do anything with the right attitude and a hammer.
 

Offline synapsis

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #48 on: October 08, 2013, 04:59:24 pm »
Back in the 80's I grew up with a friend whose mom worked at Burr Brown. She brought home a bare wafer and some dies once. She kept the dies in a sugar bowl so they wouldn't get lost. ;) The wafer was tiny (size of my hand maybe), the wafers in the video look huge.

What happens to wafers that don't meet spec? Do they get recycled or are they used to level the breakroom table?
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #49 on: October 08, 2013, 05:11:51 pm »
Back in the 80's I grew up with a friend whose mom worked at Burr Brown. She brought home a bare wafer and some dies once. She kept the dies in a sugar bowl so they wouldn't get lost. ;) The wafer was tiny (size of my hand maybe), the wafers in the video look huge.

What happens to wafers that don't meet spec? Do they get recycled or are they used to level the breakroom table?
bare wafers are immediately thrown back in the puddle of liquid silicon...
proces wafers are checked at each and every step. if a step fails you simply 'undo the step' be removing it.
let's say there was an etching problem with the nitride.. simply strip the photoresist completely and etch all nitride off. then apply a new layer. That is why we have those teststructures. each and every step is carefully monitored. Each layer can be 'undone'. so then the wafer is simply ran 1 step backward and it gets a redo. they call those rework lots. ( a lot is a FOUP carrying 25 wafers are a traveller boxing holding 2 'boats' each holding 25 wafers. )

Scrapped (broken) wafers are sent back to the silicon wafer maker. They recycle them into new ones. Silicon is 100% recyclable.

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