How do they design the chip ? Do they use a CAD software ? Like equivalent Altium or Zuken or similar to create PCBs ?
David.
very similar. we have Schematic capture software. Typically Cadence Virtuoso or Mentor Pyxis. There is also Silvaco.
You have simple parts liek resistors and diodes and transistors. the symbols are the same , but the attached data is of a toally different calibre. layout geometry, layer thicknesses, parasitics ... it's all attached to the symbol.
Simulation is typically Mentor's Eldo or Cadence Ultrasim. Don't compare these tools with Multisim or LTspice. This is a completely different world. These simulators DO work ! The reason is that we do have accurate models. we know exactly how our transistors and other elements on the chip behave. There is no approximation or the classical trick of slapping in voltage to current converters and other 4 terminal elements like in 'little spices'. Engines like ELDO and UltraSim can simulate an entire chip with millions of transistors at transistor level , including all the parasitics injected in the layout of the chip. These tools are customized for each chip maker. The Eldo version that we use is not the same as the Eldo used by Maxim or Linear ! The simulation libraries are tuned for our process chemistries. you need to tell the simulator i am using BicMos 9 from manufacturer xyz for this design, or i am doing cmos x nanometer form that guy there.
These simulators only run on huge compute farms. A typical simulation cluster can have hundreds of processors all tackling the same design. Top level simulations can run multiple days.
Just like you have PCB layout tools there are IC layout Tools. Cadence Opus for example. there are p-cell generators and libraries just like in normal pcb. we just have more layers ... 50 to 60 layers for an average chip.
you place parts from library and wire em up according to the schematic.
Digital cruft is fully automatic. Cell placers create row and column distributions and autoroute the interconnects. parasitics are extracted and buffers are injected in nodes with lots of load.
This software is so expensive it cannot be bought. It is licensed for 1 year. The schematic capture tools are essentially free. anything else is paid per second the software runs and per processor core it claims. A single runtime licence costs multiple millions of dollars per year.
Key software makers in this field are Cadence, Mentor, Silvaco , Magma , Ansys and some others. All this stuff runs on bug iron ( used to be Sun Solaris on workstations) but is now mainly done on standard windows PC's using VNC connecting to the compute farm. The farm is a mix cluster of Sun and RHEL (Red hat enterprise linux) The tools are only supported on very carefully selected installations. you can't just take any linux and plonk that stuff on there. If you run into trouble the tool makers will tell you to go to hell. They use a particular build of the OS and do their testing on that install. If you want to use any other install they give no warranty it will work as designed...
There is a windows based IC design tool from a company called Tanner-EDA