Author Topic: EEVblog #532 - Silicon Chip Wafer Fab Mailbag  (Read 51826 times)

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Offline maros

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #50 on: October 08, 2013, 05:25:48 pm »
If someone's courious about how pure silicon rods are made should take a look at Czochralski process invented by Polish scientist Jan Czochralski.
 


Offline DavidDLC

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #52 on: October 08, 2013, 08:34:55 pm »
 

Offline DavidDLC

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #53 on: October 08, 2013, 08:40:41 pm »
How do they design the chip ? Do they use a CAD software ? Like equivalent Altium or Zuken or similar to create PCBs ?

David.
 

Offline zoomtronic

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #54 on: October 08, 2013, 08:56:11 pm »
Excellent video, I watch some of Your videos, because some are more interesting than others to me. I do electronics as a hobby, more programming lately. Also link to "Indistinguishable From Magic: Manufacturing Modern Computer Chips" are excellent way to figure out how production of modern day chips are going on.
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Offline tized

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #55 on: October 08, 2013, 09:01:04 pm »
That video brings back memories...
My first steps in the industry were as a test development engineer, writing the test programs for the testers.
The company I worked for back then had several testers for engineering. The "cheap" ones, that only did digital, cost $500k. The more expensive ones, with mixed-signal capabilities, cost $4M (Teradyne Tigers). Each tester had a handler, which is the robot that gets trays of units to test and runs them on the test.
For each product there is a TIU (Tester Interface Unit), which are like the probecard (called SIU sometimes) Dave showed but bigger! A TIU would cost anything from $20k to $40k depending on the components you have on it and complexity. Of course you had to have several TIUs for each product; one for each tester and some spares to avoid downtime if one gets broken (and they often do). Each TIU has a test-socket, or several test-sockets for small components, like the ones in the video. The locker on the sockets (the top part) can come off and the handler will have a jig to match the socket, that can pick units up and place them on the TIU.
Now, the socket sits attached to the TIU with the pogo pins against the pads on one side, with the handler pushing hundreds to thousands of units with its manipulators, imagine the wear and tear on those boards and sockets.  At one time we had lots of weird problems with one of the testers. The technician from the vendor opens up the test head and blows pressurized air in it, out flies metal bits as if it were a CNC machine. On another occasion a handler lost its calibration in mid-run and tried to place unit through the TIU, I'll leave the damage assessment as an exercise.         

Hey, first post! *waves hand at everyone*

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Offline zoomtronic

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #56 on: October 08, 2013, 09:02:50 pm »
I also found video on veritasium channel on YT
simple but very clear explanation of transistor working process.
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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #57 on: October 08, 2013, 09:22:58 pm »
How do they design the chip ? Do they use a CAD software ? Like equivalent Altium or Zuken or similar to create PCBs ?

David.
very similar. we have Schematic capture software. Typically Cadence Virtuoso or Mentor Pyxis. There is also Silvaco.
You have simple parts liek resistors and diodes and transistors. the symbols are the same , but the attached data is of a toally different calibre. layout geometry, layer thicknesses, parasitics ... it's all attached to the symbol.

Simulation is typically Mentor's Eldo or Cadence Ultrasim. Don't compare these tools with Multisim or LTspice. This is a completely different world. These simulators DO work ! The reason is that we do have accurate models. we know exactly how our transistors and other elements on the chip behave. There is no approximation or the classical trick of slapping in voltage to current converters and other 4 terminal elements like in 'little spices'. Engines like ELDO and UltraSim can simulate an entire chip with millions of transistors at transistor level , including all the parasitics injected in the layout of the chip. These tools are customized for each chip maker. The Eldo version that we use is not the same as the Eldo used by Maxim or Linear ! The simulation libraries are tuned for our process chemistries. you need to tell the simulator i am using BicMos 9 from manufacturer xyz for this design, or i am doing cmos x nanometer form that guy there.

These simulators only run on huge compute farms. A typical simulation cluster can have hundreds of processors all tackling the same design. Top level simulations can run multiple days.

Just like you have PCB layout tools there are IC layout Tools. Cadence Opus for example. there are p-cell generators and libraries just like in normal pcb. we just have more layers ... 50 to 60 layers for an average chip.
you place parts from library and wire em up according to the schematic.

Digital cruft is fully automatic. Cell placers create row and column distributions and autoroute the interconnects. parasitics are extracted and buffers are injected in nodes with lots of load.

This software is so expensive it cannot be bought. It is licensed for 1 year. The schematic capture tools are essentially free. anything else is paid per second the software runs and per processor core it claims. A single runtime licence costs multiple millions of dollars per year.

Key software makers in this field are Cadence, Mentor, Silvaco , Magma , Ansys and some others. All this stuff runs on bug iron ( used to be Sun Solaris on workstations) but is now mainly done on standard windows PC's using VNC connecting to the compute farm. The farm is a mix cluster of Sun and RHEL (Red hat enterprise linux) The tools are only supported on very carefully selected installations. you can't just take any linux and plonk that stuff on there. If you run into trouble the tool makers will tell you to go to hell. They use a particular build of the OS and do their testing on that install. If you want to use any other install they give no warranty it will work as designed...

There is a windows based IC design tool from a company called Tanner-EDA
 
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Offline tized

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #58 on: October 08, 2013, 09:30:32 pm »
How do they design the chip ? Do they use a CAD software ? Like equivalent Altium or Zuken or similar to create PCBs ?

David.

EDA tools are used for the design of chips. Search for Cadence and Synopsis to have an over view of some of the major software vendors in that area.
Basically on one side you have the layout engineers who design the actual transistor level. They create a library of gates, latches and other basic components in a similar way to PCBs for a specific production process. On the other side there are the design engineers who functionally describe the chip logic in high level languages (Verilog and VHDL). In the middle you have the back-end engineers who take the design and "synthesize" using the process libraries in to gates and transistor, doing the blocks placement and routing. That's the over simplified version of the flow as there is much more to it: Architecture, Micro-Architecture, verification, static-timing analysis, DRC, emulation. And that's just the pre-silicon side...  :o
 

Offline open loop

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #59 on: October 08, 2013, 09:33:31 pm »
Really enjoyed this video, It reminded me of a few things.

The photo on page 851 in "the art of electronics" second edition... Looks like a couple of engineers looking at a massive (5m by 5m) printout of the wafer mask. Would be interesting to see if these are still done today.

The test head reminds me of the skill that was required to make the early core memory modules. Where tiny ferrite beads were woven into copper wire by hand. I am very lucky to have core memory module myself.

I did spend a few days of my childhood breaking into old ICs to see the "silicon chip" I used a bench vice and blunt chisels - well they were blunt after I broke into a few ICs. If you want to easily photograph a chip then an old 27 series EEPROM may be interesting but it would only be memory cells. I also seem to remember that the early microprocessor chips had an EEPROM version and was windowed, got a couple of these and they may be worth looking into.


Anyway great video
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #60 on: October 08, 2013, 09:39:26 pm »
Careful with moores law. That law is often misinterpreted !

Moores law says that every 12 to 14 months the number of transistors on a chip doubles.
nothing more...

it does not say 'that the chip needs to stay the same size !

There have been long periods where the transistors themselves would not shrink. we kept running 0.5 micron for 5 to 7 years ... the chips just became larger and larger. So moores law remained valid.
Then we switched to 250 nanometer. Did that violate moores law ? no the design still had x amount of transistors, you could simply put them on a smaller area.

Moores law essentially tells us one thing : desings are doubling in complexity every year and a half or so.
we are now at a few million transistors to turn blink an led...A typical remote control that reads a keypad and blink the Ir led used to be made with simple logic. a shiftregister and some timers. now we use 32 bit cpus with tons of code in flash eprom , adc to do the capsense  and some remotes even have color lcd's now... a far step from the first remote that used and LC tuned oscillator to transmit a few frequencies. the buttons on the remote changed the frequency. that's all...
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Offline M. András

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #61 on: October 08, 2013, 09:40:41 pm »
just out of curiosity. there was a mentioning of led manufacturers, how many of the led company's have their own fab?. (<-it was a debate question from a sparky when they installed new fixtures in our warehouse and again goddam neon lights..) and how many of the ic company's have?. other lesser intresting question how much do they use from the gold bond wires lets say for a tqfp 208 package for the whole wafer? what other materials do they use for bond wires? like for those insanly high current fets etc
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #62 on: October 08, 2013, 09:41:36 pm »

The photo on page 851 in "the art of electronics" second edition... Looks like a couple of engineers looking at a massive (5m by 5m) printout of the wafer mask. Would be interesting to see if these are still done today.

yes they are. the entire chip is plotted so you can scribble space allocation on there as the design goes. you can use a pen and draw what blocks you wan twhere. ideal for team meetings.
indivdual blocks may be plotted in detail to scribble remarks of how the layout needs tweaking
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Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #63 on: October 08, 2013, 09:42:13 pm »
What happened to your finger at 10:50?

Wasn't just the finger:


Oh wow.  What happened?
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Offline Kempy

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #64 on: October 08, 2013, 10:48:55 pm »
Great stuff, thanks Dave and Vincent! It's always amazing to see how the magic happens.
Also those nanometer probes, I guess, you cannot even breathe on it, or it will bend  :-DD :scared:

I had a question tho, is there any widely available solvent or chemical which can be used to remove/dissolve package epoxy of usual chip packages? I like taking photos of electronic gear, and tried couple ways to get die shots, but either shatter die or it gets badly damaged when trying remove epoxy mechanically. I have some dead modern CPUs and GPUs, which might be interesting to look at (lots actually, even some latest multi-billion transistor count chips) :)

Best one so far is nvidia geforce4 Ti4200 GPU die shot, which i got off it's BGA package by heating it and cracking open.
Pity it's covered with metal mask in front, so cannot see inner layers beauty.

Here is a video of how to de-cap chips at home (you do need a cnc mill however)
 

Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #65 on: October 09, 2013, 02:08:22 am »
Great stuff, thanks Dave and Vincent! It's always amazing to see how the magic happens.
Also those nanometer probes, I guess, you cannot even breathe on it, or it will bend  :-DD :scared:

I had a question tho, is there any widely available solvent or chemical which can be used to remove/dissolve package epoxy of usual chip packages? I like taking photos of electronic gear, and tried couple ways to get die shots, but either shatter die or it gets badly damaged when trying remove epoxy mechanically. I have some dead modern CPUs and GPUs, which might be interesting to look at (lots actually, even some latest multi-billion transistor count chips) :)

Best one so far is nvidia geforce4 Ti4200 GPU die shot, which i got off it's BGA package by heating it and cracking open.
Pity it's covered with metal mask in front, so cannot see inner layers beauty.

Here is a video of how to de-cap chips at home (you do need a cnc mill however)


Why would you de-cap a chip?
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Offline jp430bb

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #66 on: October 09, 2013, 02:18:43 am »
One guy decapped some microcontrollers to try and read out the mask-programmed firmware on them. 

Another reason would be to get the die size and pictures of the overall layout of the die, like how many cores and SRAM blocks are on a CPU. 
« Last Edit: October 09, 2013, 02:20:15 am by jp430bb »
 

Offline jp430bb

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #67 on: October 09, 2013, 02:26:22 am »
Back in the 80's I grew up with a friend whose mom worked at Burr Brown. She brought home a bare wafer and some dies once. She kept the dies in a sugar bowl so they wouldn't get lost. ;) The wafer was tiny (size of my hand maybe), the wafers in the video look huge.

What happens to wafers that don't meet spec? Do they get recycled or are they used to level the breakroom table?
bare wafers are immediately thrown back in the puddle of liquid silicon...
proces wafers are checked at each and every step. if a step fails you simply 'undo the step' be removing it.
let's say there was an etching problem with the nitride.. simply strip the photoresist completely and etch all nitride off. then apply a new layer. That is why we have those teststructures. each and every step is carefully monitored. Each layer can be 'undone'. so then the wafer is simply ran 1 step backward and it gets a redo. they call those rework lots. ( a lot is a FOUP carrying 25 wafers are a traveller boxing holding 2 'boats' each holding 25 wafers. )

Scrapped (broken) wafers are sent back to the silicon wafer maker. They recycle them into new ones. Silicon is 100% recyclable.

Once wafers have had metal layers deposited, silicon wafer makers won't want them back.  Copper, in particular, is poison for silicon wafers in the front-end (early) process steps. 
 

Offline elCap

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #68 on: October 09, 2013, 02:46:22 am »
@walshms. that's : interference lithography. that is the term that eluded me. It's been so long since i've been on that side of the entire semiconductor world... i've forgotten half of it..

it is like i described. even thought the knife blade itself is too wide, by putting it under 45 degrees you can make a cut smaller than the width of the knife. in the lithography process they use two light bundles , 90 degrees apart and 45 degrees offset from the plane. so if the plane is horizontal , one is shining left to right under a 145 degree angle, the other shines right to left under a 45 degree angle. Where the wavelength interferes with each other you get a standing wave ( i think. it's like the famous double slit experiment. http://en.wikipedia.org/wiki/Double-slit_experiment )
in the peaks you have light , so you are exposing the photoresist. In the valley there is absence of light so no exposure.

Instead of slits they use complex patterns the make the light beams coming from opposite directions interfere with each other and create the correct shadowed areas in the form of the wanted structure. Totally batshit crazy stuff.
ASML is the big name there.
As for photomasks, I think the Phase shift mask (PSM), which uses interference, is quite common these days. Then there are other mask types like half tone, gray tone and so on. For binary mask the optical proximity correction technique is probably mandatory for high performance mask. For anyone interested, Wikipedia is a good starting point http://en.wikipedia.org/wiki/Photomask

Other "fun facts" about photomask: Mask substrates are made of quartz for the optical and thermal properties. Photomasks for semiconductor are normally 4 times bigger than the intended chip size. But for displays (LCD, plasma, ...) the photomasks are 1:1, making the masks for the biggest TV huge, heavy and expensive.
For making the photomask there are two main techniques; laser and e-beam. Semiconductor masks use both, display masks only laser.

Someone mentioned invar as a material with low thermal expansion. Another material used in semiconductor industries is Zerodur, thermal expansion close to zero. Quite cool stuff. But even with quartz, invar and Zerodur the temperature control for exposing systems has to be very good, within a 1000 of a degree. (e.g. 23.000 +/-0.001 C)
 

Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #69 on: October 09, 2013, 02:51:04 am »
One guy decapped some microcontrollers to try and read out the mask-programmed firmware on them. 

Another reason would be to get the die size and pictures of the overall layout of the die, like how many cores and SRAM blocks are on a CPU.

Ok I just reread my question and realized I worded it very badly.  I meant to ask what de-lidding is (I'm new at this).
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Offline jp430bb

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #70 on: October 09, 2013, 03:13:32 am »
@walshms. that's : interference lithography. that is the term that eluded me. It's been so long since i've been on that side of the entire semiconductor world... i've forgotten half of it..

it is like i described. even thought the knife blade itself is too wide, by putting it under 45 degrees you can make a cut smaller than the width of the knife. in the lithography process they use two light bundles , 90 degrees apart and 45 degrees offset from the plane. so if the plane is horizontal , one is shining left to right under a 145 degree angle, the other shines right to left under a 45 degree angle. Where the wavelength interferes with each other you get a standing wave ( i think. it's like the famous double slit experiment. http://en.wikipedia.org/wiki/Double-slit_experiment )
in the peaks you have light , so you are exposing the photoresist. In the valley there is absence of light so no exposure.

Instead of slits they use complex patterns the make the light beams coming from opposite directions interfere with each other and create the correct shadowed areas in the form of the wanted structure. Totally batshit crazy stuff.
ASML is the big name there.
As for photomasks, I think the Phase shift mask (PSM), which uses interference, is quite common these days. Then there are other mask types like half tone, gray tone and so on. For binary mask the optical proximity correction technique is probably mandatory for high performance mask. For anyone interested, Wikipedia is a good starting point http://en.wikipedia.org/wiki/Photomask

Other "fun facts" about photomask: Mask substrates are made of quartz for the optical and thermal properties. Photomasks for semiconductor are normally 4 times bigger than the intended chip size. But for displays (LCD, plasma, ...) the photomasks are 1:1, making the masks for the biggest TV huge, heavy and expensive.
For making the photomask there are two main techniques; laser and e-beam. Semiconductor masks use both, display masks only laser.

Someone mentioned invar as a material with low thermal expansion. Another material used in semiconductor industries is Zerodur, thermal expansion close to zero. Quite cool stuff. But even with quartz, invar and Zerodur the temperature control for exposing systems has to be very good, within a 1000 of a degree. (e.g. 23.000 +/-0.001 C)

Fun fact about silicon and coefficient of thermal expansion: at liquid nitrogen temperature, silicon's CTE is close to zero.  That makes LN2-cooled silicon popular for mirrors for high-power x-ray beams. 

 

Offline Razor512

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #71 on: October 09, 2013, 11:11:56 am »
If a company is going to charge over a million dollars a year for software, won't companies designing these IC's just pirate the software, or weigh the cost of purchasing a license to the software, to the cost of just allocating a few of their programmers to try and crack the software?

At least until they charge a reasonable price, eg $100 for lifetime use of per version of the software, or if it needs frequent updating, then $30 a month or something?
 

Offline quarros

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #72 on: October 09, 2013, 11:23:15 am »
If a company is going to charge over a million dollars a year for software, won't companies designing these IC's just pirate the software, or weigh the cost of purchasing a license to the software, to the cost of just allocating a few of their programmers to try and crack the software?

At least until they charge a reasonable price, eg $100 for lifetime use of per version of the software, or if it needs frequent updating, then $30 a month or something?

You do realize what kind of a colossal lawsuit would ensue after a thing like that?  :palm:
If you have a market that has very few players, than practically no secret can be held for long.
 

Offline tized

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #73 on: October 09, 2013, 11:56:54 am »
If a company is going to charge over a million dollars a year for software, won't companies designing these IC's just pirate the software, or weigh the cost of purchasing a license to the software, to the cost of just allocating a few of their programmers to try and crack the software?

At least until they charge a reasonable price, eg $100 for lifetime use of per version of the software, or if it needs frequent updating, then $30 a month or something?

A. The software licenses are still small change relative to the cost of the FABs and engineers.
B. Those are all tape-out proven software suits, meaning several products have been successfully taped-out using that software. With each tape-out costing millions of dollars, no one will take a risk with cracked/hacked software.
B. Smaller business don't pay millions but tens to hundreds of thousands of dollars a year for just for a few licenses. The licensing schemes are gradual.
C.  When a company does get to the millions of dollars a year area, the licenses include training vouchers for the staff, every bug report gets seriously addressed and you might even get on site support people.

As the saying goes "You get what you paid for".
 

Offline quarros

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #74 on: October 09, 2013, 12:01:11 pm »
A. The software licenses are still small change relative to the cost of the FABs and engineers.
B. Those are all tape-out proven software suits, meaning several products have been successfully taped-out using that software. With each tape-out costing millions of dollars, no one will take a risk with cracked/hacked software.
B. Smaller business don't pay millions but tens to hundreds of thousands of dollars a year for just for a few licenses. The licensing schemes are gradual.
C.  When a company does get to the millions of dollars a year area, the licenses include training vouchers for the staff, every bug report gets seriously addressed and you might even get on site support people.

As the saying goes "You get what you paid for".

Additionally you can get the software specifically tailored to your own fab needs!
 


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