Author Topic: EEVblog #532 - Silicon Chip Wafer Fab Mailbag  (Read 51776 times)

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EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« on: October 08, 2013, 09:06:47 am »
A look at some equipment and wafers used in the manufacture of silicon chip wafers.
200mm and 300mm wafers, die, dice sawing, lead-frame manufacture, automated testing machine (ATE) probing, clean room bunnie suits, photo plots, BGA chip thermal test sockets, and the worlds smallest active FET probes at 100 nanometers for direct wafer probing!
Thanks to Vincent Himpe:
http://www.siliconvalleygarage.com/

 

Offline walshms

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #1 on: October 08, 2013, 09:36:02 am »
Okay, so how cool is it to get your hands on stuff like this?

Amazing... the die test rig alone is seriously impressive.  What do you guess... maybe a month to build one?

Vincent, thanks for sharing this!  :-+
 

Offline Jebnor

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #2 on: October 08, 2013, 09:47:19 am »
I found this Talk about Fabrication by a guy who works in a FAB.    Really interesting.

It's an hour long, and oh so worth it!
Before this, there was a typo.
 

Offline walshms

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« Last Edit: October 08, 2013, 10:05:04 am by walshms »
 

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #4 on: October 08, 2013, 09:58:53 am »
Vincent, thanks for sharing this!  :-+

 :-+

Offline walshms

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #5 on: October 08, 2013, 10:28:46 am »
This video is from 2008, but gives a bit more insight into the beginning and some of the process:

 

Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #6 on: October 08, 2013, 11:15:32 am »
What happened to your finger at 10:50?
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Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #7 on: October 08, 2013, 11:43:36 am »
What kind of phone is that?
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Offline pickle9000

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #8 on: October 08, 2013, 12:30:42 pm »
Dave what did it smell like?

Amazing mailbag, best ever for sure. Thank you Vincent
 

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #9 on: October 08, 2013, 12:35:32 pm »
What happened to your finger at 10:50?

Wasn't just the finger:
 

Offline nathanpc

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #10 on: October 08, 2013, 12:39:11 pm »
This is by far the most fascinating mailbag ever.
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #11 on: October 08, 2013, 12:46:53 pm »
Well done Mate !

Now, if you think that probecard is an amzing piece of gear. Think about the test machine behind that sucker.
We have certain products that we ship over a million parts a day of. there's only 3600 seconds in an hour, 24 hours a day that's 86000 seconds.

you better get a machine that can execute that test lightning fast... even if you can do 3 chips a second ( these machines have multiple heads, one is testing the second on is unloading, the third one is loading... ) That's only 260000 chips a day. you need 5 of these testers ( assuming no downtime for maintenance ) to just run 1 product !

The cost of these machines is mindboggling. The really high end machines are actually not sold. There is no way to recup the development cost, other than to charge you for the test-time. You buy the hardware ( which cost multiple arms and legs) while the test software and the know-how is paid for by paying a price per second. If every chip costs 2 cents to test... and you run a million a day .. the bill at the end of the day is 20K$ ... 356 days a year. just for one product.
That is why only the really large companies can afford their own fabs. Everything else subcontracts it to the megafabs like TSMC and UMC or charters.

Some other mind boggling numbers:
The actual waferfab , the building, power, consumables, air filtration , electricity , gases and chemicals including the personell and the depreciation of the equiment in it costs about 600 million $ a year. And you have not made a single chip. so even if you are loitering for a minute ... 365 days at roughly 1.6 million $ a day ... or 68000$ an hour. Just to run that thing idle...

you cannot shut down any of that equiment. The process are so critical that the reactors need to stay in operation or you get all kinds o side effect inside the machine and the end result is chips that dont work right. So when idle we actually cycle 'dummy' wafers. put metal on , etch it off, put metal back on , etch it off. after 1600 wafer the reactors go down for cleaning... that takes 4 hours... so running dummies is mandatory but also very expensive as it eats into the cycle counter before mandatory shutdown.

A key machine going down is a disaster. maintenance is planned in conjunction with fab operations so that the downtime of the machine has no impact on the flow. they make sure there are no wafers waiting for that process step. there is daily, two daily, 3 daily, weekley biweekley monthley, bimonthly maintenance. The manufacturer of the equioment has checklists and these maintenances need to be done.

If the biweekly says : change all the bearings you change all the bearings. The biggest mistake you can make is looking at the bearing and saying 'but they still look good, ' That can get you fired... Nobody is willing to take the risk of leaving the bearings in to find out that 2 days before scheduled mainteance the thing comes to a grinding halt because the bearings wore out... now there are wafers waiting... if a biweekly maintenance means 4 hours scheduled downtime (nothing waiting) it only cost you the personell cost. if you have 4 hours downtime with wafers waiting the bill becomes over 250.000 $ ... there is going to be some yelling involved in that one... all for 400$ in bearings.

Right. some expansion on the video and elaboration.

image of a tester : http://www.teradyne.com/pressRoom/images/UltraFLEX-HD.tif (warning ; 43 megabyte file ! )
that testhead holds 1 chip under test ! if you ook inbetween the operator's arms you see the large plumbing fixtures that pipe liquid nitrogen into the head.. the chip is actually cycled , cold ( -30 degrees , ambient , 25 and hot (125) )

Now image a tester that tests 16 Gbyte flash chips.. Erase them , program checkerboard, read, erase , alternate checkerboard, verify, wipe, do this at three temperatures, finally format it lod the wear leveling algorithm , write the dead cell msrkers and allocation tables and spit it out.. That chips sits in the tester for maybe 50 to 60 seconds ... Now you understand why they cant make a sub 1 dollar flashchip... the testtime alone cost 2$. and thats not counting the cost of the machine, operators or building the machine sits in...

Bondout chip:
basically they bring out the internal data and address bus and the core is made 'static' ( the clock can be stopped) so that's ewhat the extre a pins are. this allows for the tracer to look over the shoulder of the core and look at the inside registers.
JTAG effectively eliminated bond-out parts

Leadframe:
the cup holding the die is flashed with a few microns of silver. a silver-eopxy glue is used to glue the die in the cup. after bonding and molding a stamping machine bends the pins and snips the shorting bar inbetween the pins and trims the pins to length.

Testsockets. The crowns on the pogo pins are made such that they cause only minimal dmage ot the ball but the sharp prongs cut onto the ball to guarantee good contact. also the bottom of the pogopin has a tiny crown. that construction is made sideways. so whenever you apply pressure there is a sideways wiping action cleaning the contact area between pogo pin and pad on the pcb.

Probeneedles
All those needles are used for manual probing on a probestation. we decapsulate prototype chips, solder them on a testboard and stikc it under a microscope. the probestation is just a large anti-vibration table. basically an air suspended massive block of granite with a board holder and floating microscope. micromanipulators have a grabber at the end. stick in a needled and you can position the needle above the die and pick off a signal. the microscope has a laser mounted that is used to destroy the passivation , or metal. so we can actually drill down and expose internal contacts. drop the needle and you can measure internal signals.

Bare dies. These are normal bondpads. i thought those were pillared but they arent. the Sawn silicon germanium wafer IS pillared. instead of bondpads there are solid copper rods sticking up. so these chips are not bonded . they are flipped upsided downon a flex and then ultrasonically rubbed until the copper rods weld into the flex substrate.

Mask. that thing is technically called a reticle. a real mask is chip-scale and exposes the entire wafer in one shot. as structures gotten smaller dust becomes a problem. so we make upscaled masks that are optically shrunk during exposure. the wafer is stepped a few chips at a time the black ring on the mask is used to put a celluloid foil over the mask. the masks are washed, dried , and then a fresh foil is applied. the distance between foil and surface of the actual pattern means, if dust falls on the foil, we can focus straight through that. it doesn't bother. That plate is pure microscope quality quartz. it is sputtered with chrome. The mask is actually for an plasma tv panel column or row driver. that's why this is a long skinny chip. its essentially a shift register with lots of output drivers. its got a lot of memory on board to compensate for panel deficiencies

probecard : the needles are made of a material called invar  http://en.wikipedia.org/wiki/Invar.
as this testing is done hot and cold we cant have the needleds extend or contract !. that would shift their position on the bondpads...
the tails are spot welded on the invar needle. then that golden (its actually kapton) sleeve is trimmed to length , slid over and the end tacked down.

The 8051 is actually a uPSD5000. it is a 8051 with a cpld ram and flash. it is the last generation ( or was. its discontinued) of the Waferscale PSD devices.

The big boy (300mm) is an image processor for HD lcd tv's. it takes the HDMI signal ,decrypts it and spits it to the panel drivers. it does upscaling , deinterlacing as well as the backlight modulation ( this is for LED panels where each LED is a RGB triplet that can be midulated independently )
« Last Edit: October 08, 2013, 01:20:37 pm by free_electron »
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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #12 on: October 08, 2013, 12:58:52 pm »
The actual waferfab , the building, power, consumables, air filtration , electricity , gases and chemicals including the personell and the depreciation of the equiment in it costs about 600 million $ a year. And you have not made a single chip. so even if you are loitering for a minute ... 365 days at roughly 1.6 million $ a day ... or 68000$ an hour. Just to run that thing idle...

In our Seismic streamer manufacturing plant at my former company, we'd produce >$250K worth of product a day (more expensive than a new car these things).
So if a bit of my automated product gear broke down for an hour, you'd not only lose that money, but the customer has their survey boat sitting idle in dock costing then $2M/day in lost revenue.
So everyone had "standing orders" - no matter what you are working on, if production stopped, you dropped whatever it was and raced to production to fix it. I always had a pre-packed toolkit with all the right gear ready to go at a moments notice.
 

Offline kizzap

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #13 on: October 08, 2013, 01:20:11 pm »
An excellent video there Dave, thanks for sharing too Vincent.

There was one thing that piqued my interests, and it didn't seem to get mentioned. On the 200mm wafer, it looked like there were quite a number of dies that weren't the same as the rest of the batch. Is this normal, and what sort of purpose would it have?

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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #14 on: October 08, 2013, 01:25:42 pm »
those are parametric teststuctures.

there is a number of individual resistors, some loose diodes some loose transistors.
when we are depositing, for example, a resistive layer, that layer may not be the same thickness everywhere. having these teststructres allows a quick initial test. we simply measure the resistance teststructre and 'map' the thickness gradient across the wafer. if it is out of tolerance most likely very few parts will meet spec so we don't bother : simlply reject the entire wafer it's cheaper. so it is a kind of quick check to see if 1) nothing was missed (maybe a layer is missing) , 2) there are no crazy tolerances

Besides electrical structures there are also optical markers so the exposure units have calibration points for layer alignment.
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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #15 on: October 08, 2013, 01:31:18 pm »
Sorry bout the cleanroom overall size. that's all they had at weirdstuff warehouse. check the inside label. It'll say Agilent i believe. these came from the Lumileds fab ( Agilent -> avago ) here in san jose. So these were worn by some dude making your super bright led's in your overhead fixtures.
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Offline ChrisBoden

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #16 on: October 08, 2013, 01:40:15 pm »
I love the shirt. ;)
 

Offline grego

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #17 on: October 08, 2013, 02:05:03 pm »
Vincent, nice going.  Seriously.  Really interesting stuff.  Big +1.

 :-+
 

Offline JoeN

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #18 on: October 08, 2013, 02:40:53 pm »
I found this Talk about Fabrication by a guy who works in a FAB.    Really interesting.

It's an hour long, and oh so worth it!


The guy got xylene and phosgene mixed up 19:48.  Dave is too smart to make this sort of mistake.  As a matter of fact, so am I.  I have to deduct 4 points right there.
Have You Been Triggered Today?
 

Offline gman4925

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #19 on: October 08, 2013, 02:42:23 pm »
Favourite part
 

Offline marshallh

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #20 on: October 08, 2013, 02:55:32 pm »
A+ great video. The probe head is nuts.

Got a board here not quite as thick but about 180-200mils or so (16 layers): yes they actually run 8mil mechanical drills through this aspect ratio pcb:

Verilog tips
BGA soldering intro

11:37 <@ktemkin> c4757p: marshall has transcended communications media
11:37 <@ktemkin> He speaks protocols directly.
 

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #21 on: October 08, 2013, 03:15:45 pm »
Favourite part

Did you watch after the credits?
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #22 on: October 08, 2013, 03:37:24 pm »
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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #23 on: October 08, 2013, 03:39:28 pm »
I found this Talk about Fabrication by a guy who works in a FAB.    Really interesting.

It's an hour long, and oh so worth it!


The guy got xylene and phosgene mixed up 19:48.  Dave is too smart to make this sort of mistake.  As a matter of fact, so am I.  I have to deduct 4 points right there.
He got a whole bunch of other things mixed up as well. Like the order of processes, the way the implanter works and a bunch of other things. He doesnt work in a fab. He talked to people that does and he genuinely is i terested, but he's confused and mixed things up. That stuff is very comp,ex and it takes months before you start understanding the flow.
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Offline elCap

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #24 on: October 08, 2013, 03:54:04 pm »
Thanks Dave and Vincent! That was a great mailbag, bring out some good memories.

I have used those Picoprobes a lot, measuring on wafers consisting mainly of passive structures. I had a big rack of all kinds of test gear, among other Agilent 4294A LCR meter an lock-in amp Perkin Elmer/EG&G 7280, and "home made" stuff. I especially remember when using the LCR meter I had problems with noise and had to make all cables as short as possible and also cut the Picoprobes down. It was easy with the correct tools, good microscope and sharp knife.
That's over 10 years ago now.. wonder what happen to all the test gear, would be nice to have some of it now.

And according to my experience silicone wafers are not that brittle. They will not just break without force, lifting them up is no problem. I used to cut them by hand. Use a diamond glass cutter to make a small mark/scratch that follow the crystal orientation (indicated by a flat end or a small cut out on the wafer).  Then tap on it gently and it will break in a perfect straight line.. if you are not unlucky to get some second grade wafer with undefined crystal orientation; silicone flying all over.
- NEVER handle wafers without wearing safety glasses, silicone is super sharp -

And probe cards.. almost has nightmare from them..  we used old probe stations that failed from time to time, resulting in all kind of problems, wafers flying, stacking many wafers on top of each other at unload (scratch!), and had the chuck lifted too high crashing in to the probe card! Fortunately the probe cards we used were not that complex so we could fix them in-house.
And all was just for R&D so just to tell the PhD dude; sorry, no results today, maybe tomorrow.

The foil put over the mask (over the black ring) is called pellicle. One other aspect of is also to protect the mask.

Wish I could send in some photo masks. They are a little bigger than 6inch..

 

Offline poorchava

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #25 on: October 08, 2013, 05:09:46 pm »
As for attaching die to the leadframe: quite often the die is being soldered to the leadframe. And that solder is almost pure lead (like 89% or something IIRC). And those are RoHS parts. It's just that there's an exemption in RoHS for die attach :).
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Offline SArepairman

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #26 on: October 08, 2013, 05:32:14 pm »
Favourite part


with only the hood on he looks like Lawrence of Arabia
 

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #27 on: October 08, 2013, 07:03:35 pm »
Wafers are cut whit a mechanical saw? is that real?
 

Offline vk2hmc

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #28 on: October 08, 2013, 07:19:17 pm »
Vincent - Thanks for sending the m o s t  a w e s o m e s t  mailbag yet!
Dave - now that is something we don't see every day!
I am off to watch it for the 4th time now ;)

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Offline nack

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #29 on: October 08, 2013, 08:23:52 pm »
Awesome episode!
 

Offline Razor512

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #30 on: October 08, 2013, 09:37:41 pm »
When can we expect the cost and size to come down to a point where we can do a low volume fab at home?

@free_electron, even with those cost, don't you find it insane how high the cost is for flash memory?
for example, a company will make a 64GB SDXC card and then charge an arm and a leg price of $42


(you could just imagine CEO's laughing all the way to the bank when due to a lack of competition, they can charge prices like this for a product that likely has an extremely high yield and a low overall manufacturing cost).
 

Offline pe4mwt

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #31 on: October 08, 2013, 09:39:50 pm »
Nice video, I wear those suits to work everyday, only mine is blue, and in our factory the socks are just that: socks. We wear normal ESD shoes over them. No zipper and no pink stuff either ;). But hey, we don't produce chips, we only produce the 30 to 130 million euros costing lithography machines the chip manufacturers are using to expose the chips.

If you think those 300 mm wafers are big just wait until the 450 mm technology is ready. They are working on that now all around the world. I don't think I am going to carry those wafers, 25 in a row, in one foup. Curious how they are going to solve that. The automatic fabs will probably need even better tracks along the roof for carrying those heavy foups.

Vincent is actually a dutch guy living and working in the US. And yes he wrote some interesting books. I have one of those over here, really nice. If you'd seen all his equipment in his garage then you know even Dave would be jealous. At least I am...

Thanks for the video Dave and Vincent thanks for sending Dave all that nice stuff!
« Last Edit: October 08, 2013, 09:41:37 pm by pe4mwt »
 

Offline nack

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #32 on: October 08, 2013, 09:41:06 pm »
@Razor512
Expensive? Just because it's tiny doesn't mean it should be cheap! Have you really watched the videos of Dave and lithography in general?

« Last Edit: October 08, 2013, 09:53:19 pm by nack »
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #33 on: October 08, 2013, 09:42:46 pm »
Wafers are cut whit a mechanical saw? is that real?
Yes. They use a carbide blade coated with diamond dust.

http://americas.micross.com/products-services/die-wafer-services/wafer-sawing.stml

The wafer is not very hard to saw. So the carbide is not really needed. Its just that carbide is very hard so they can make a very thin blade that will not wobble. You want the cut to be a sfine as possible as it means you can put dies closer and thus more per wafer which brings the cost per chip down.
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Offline Razor512

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #34 on: October 08, 2013, 09:46:00 pm »
Why are the wafers round instead of square?  wouldn't it be more efficient to have then in a square shape so that more complete dies can be placed in the same area, thus better utilizing the same surface area? (couldn't they somehow use a square compartment when making the silicon ingots? )

and @nack I have watched a few videos, and can see where some of the fixed cost come from, but it is hard to figure out where the rest of the cost comes from.
« Last Edit: October 08, 2013, 09:53:45 pm by Razor512 »
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #35 on: October 08, 2013, 10:04:57 pm »
When can we expect the cost and size to come down to a point where we can do a low volume fab at home?

@free_electron, even with those cost, don't you find it insane how high the cost is for flash memory?
for example, a company will make a 64GB SDXC card and then charge an arm and a leg price of $42


(you could just imagine CEO's laughing all the way to the bank when due to a lack of competition, they can charge prices like this for a product that likely has an extremely high yield and a low overall manufacturing cost).
Not really. Remeber that you 64 gig card has 4 to 8 chips in it... The waferfab has to amortized on it. The development cost of the flash chip is practicaly zilch as it is a repetitive structure and those are created by specialised software. We have special software where you tell i want an array this wide, that tall and split in sectors of that large and this software goes off and creates the entire layout. So thats not the problem. It's the cost of the 45nM waferfab , and all the process equipment
Lithography is hell at such small structures. The mask image is being pre-distorted. A straight line on the wafer is not a straight line. Here is why:

Lets say you want two lines , each 45nanometer wide, running parallel at a distance of 45nanaometer from each other (remeber we run at 18 nanometer these days !)
You will expose the photolayer with ultraviolet light . Ultraviolet light has a wavelength of 400nanometer downto 10 nanometer... Making uv at 10nanometer is very very difficult. You need to excite some special gas mixes using a magnetron to get that stuff. Besides, the photomask material is sensitive in only a narrow band. For printed circuit boards this is 320 nanometer.
For chips we have resists that are sensitive to deep-uv. Around 150 to 100 nanometer.
So how do you create such small structures if the wavelength of the light is larger ? Its like cutting a line with a knife that is wider than the cut ! Solution : you cut sideways (under an angle)
This is accomplished by pre distorting the mask at an interval of the wavelength used. I'm trying to find a picture of such a mask... Ive seen em on the internet but i can't find it right now. They have a special name for this technique.
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Offline 6thimage

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #36 on: October 08, 2013, 10:06:55 pm »
Why are the wafers round instead of square?  wouldn't it be more efficient to have then in a square shape so that more complete dies can be placed in the same area, thus better utilizing the same surface area? (couldn't they somehow use a square compartment when making the silicon ingots? )

Silicon wafers need to have the same crystal orientation, referred to as things like 100 and 110, so a 'batch' of silicon wafers is created by heating up a pot of silicon, then a single crystal is placed into the pot and slowly pulled away. As it is pulled away it is rotated so that it increases in size, to produce a cylinder, this cylinder is then cut to produce the individual wafers - hence why you can't get square wafers. Wikipedia has quite a good page on it http://en.wikipedia.org/wiki/Wafer_(electronic).
 

Offline nack

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #37 on: October 08, 2013, 10:07:31 pm »
Why are the wafers round instead of square?  wouldn't it be more efficient to have then in a square shape so that more complete dies can be placed in the same area, thus better utilizing the same surface area? (couldn't they somehow use a square compartment when making the silicon ingots? )

and @nack I have watched a few videos, and can see where some of the fixed cost come from, but it is hard to figure out where the rest of the cost comes from.

Wafers are round due to their production process:
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #38 on: October 08, 2013, 10:14:05 pm »
Why are the wafers round instead of square?  wouldn't it be more efficient to have then in a square shape so that more complete dies can be placed in the same area, thus better utilizing the same surface area? (couldn't they somehow use a square compartment when making the silicon ingots? )

and @nack I have watched a few videos, and can see where some of the fixed cost come from, but it is hard to figure out where the rest of the cost comes from.
There is multiple reasons for that.
First is the pulling of the ingot.
They start with a seed crystal, no larger than a pea, of which the exact crystal orientation is known.
This is mounted on a rod and spun around slowly in a vat containing pure liquid silicon.
As they pull this upward , silicon atoms will stick to the seed crystal and they will orient themselves in the same cristalline structure.

Remeber that this whole silicon i got is 1 massive crystal without a single defect !

So the ingot is round by itself due to the growth process.
Trimming the edges of the circle doesnt make sense. You spent a lot of money to create a slice of hyper pure crystal and you are going to cut off 1/3 and throw that away. Let's use it.

Two: square wafers would have sharp corners. Bump a corner and shatter the wafer. Eveen cracking a stine fragment off the tip of a corner would create silicon dust everywhere ... Dust is your enemy.
No problem with a round wafer. It wont snag...

Three
Many reactions aredone using plasma. To mix the chemicals in the plasma very evenly you need to stir it... How do you stir a cloud of ionized very reactive gas ? With a magnetic field. Plasma reacts to magnetic field. So we have multiphase coils around the reactor chamber creating a spinning as wel as a lateral moving magnetic field. That makes a uniform mixture of the reacting agents giving a uniform process across the wafer.

Spin something and ... It becomes circular... Square reactors would be very hard to get stuff in the corners.... Circular reactors dont have corners.

There is reason to all the madness going on in this industry. It is fascinating to look at all the trickery involved in getting this to work at all !
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Offline Winston

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #39 on: October 09, 2013, 01:39:22 am »
I think I've posted this here somewhere before, but it's especially appropriate for this subject:

IC Die Photography

http://diephotos.blogspot.com/
 

Offline algorath

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #40 on: October 09, 2013, 02:52:11 am »
awesome stuff. are there any factories/test facilities like this in china/taiwan/korea? or are they just on the manufacturing site of things?
can you give us a factory tour some time freeelectron or is that shit highly classified? ^^
 

Offline vsq

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #41 on: October 09, 2013, 02:58:17 am »
I think I've posted this here somewhere before, but it's especially appropriate for this subject:

IC Die Photography

http://diephotos.blogspot.com/

Beautiful! Simply awesome! Thanks!
 

Offline walshms

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #42 on: October 09, 2013, 02:59:12 am »
The mask image is being pre-distorted. A straight line on the wafer is not a straight line. Here is why:

Lets say you want two lines , each 45nanometer wide, running parallel at a distance of 45nanaometer from each other (remeber we run at 18 nanometer these days !)
You will expose the photolayer with ultraviolet light . Ultraviolet light has a wavelength of 400nanometer downto 10 nanometer... Making uv at 10nanometer is very very difficult. You need to excite some special gas mixes using a magnetron to get that stuff. Besides, the photomask material is sensitive in only a narrow band. For printed circuit boards this is 320 nanometer.
For chips we have resists that are sensitive to deep-uv. Around 150 to 100 nanometer.
So how do you create such small structures if the wavelength of the light is larger ? Its like cutting a line with a knife that is wider than the cut ! Solution : you cut sideways (under an angle)
This is accomplished by pre distorting the mask at an interval of the wavelength used. I'm trying to find a picture of such a mask... Ive seen em on the internet but i can't find it right now. They have a special name for this technique.

I think I can help you here, Vincent.  I remember learning about this a while ago.

You're operating beyond the diffraction limits, so the masks are made to take advantage of interference; using the wave-like character of light, the masks are designed such that the resulting image is the one you actually want.  There's simply no way that you could make 18nm structures with 320nm light unless you took advantage of interference.  If you examine the masks themselves, you'd find that the image on them doesn't really look like the image that gets laid down on the photoresist.

It's really pretty amazing that we (the species) have been able to figure all of this out.
 

Offline KerryW

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #43 on: October 09, 2013, 03:04:01 am »
I worked in the industry back in the 90's making equipment to pull the dies from the completed wafers.  I worked for a company called Laurier, mostly on their DS3000 machines.

Some wafer testers marked bad die with ink dots, but most of them generated a map with a status for each die. 
The machine had an anvil with a plastic disc at the top with holes in it for 1 or more needles to poke through and holes for vacuum.  It had an arm with a collet with a vacuum hole in it.  An XY stage moved the wafer around and a video camera sat over the anvil.  Another XY stage and camera were on the output, which normally held a number of waffle packs or gel packs.
We would read the map, locate the test dies (the ones that were different), then move to the first pickable die.  Align to the camera, pull a vacuum to seat the die on the anvil, bring the collet to the die and lower it, bring the needle up to pull the die from the membrane, then raise the arm and move to the output and place the die in the next available pocket of the appropriate waffle pack.

Die sizes ranged from ~1" sq to 7 mils (178 microns).  For one project, we had to pick 10 mil (254 micron) dies, but we had to read a 4 digit serial number printed on the die before picking it.

The machines cost $150K to $250K, and could pick and place up to 2000 die per hour.
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Offline TiN

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #44 on: October 09, 2013, 03:35:15 am »
Great stuff, thanks Dave and Vincent! It's always amazing to see how the magic happens.
Also those nanometer probes, I guess, you cannot even breathe on it, or it will bend  :-DD :scared:

I had a question tho, is there any widely available solvent or chemical which can be used to remove/dissolve package epoxy of usual chip packages? I like taking photos of electronic gear, and tried couple ways to get die shots, but either shatter die or it gets badly damaged when trying remove epoxy mechanically. I have some dead modern CPUs and GPUs, which might be interesting to look at (lots actually, even some latest multi-billion transistor count chips) :)

Best one so far is nvidia geforce4 Ti4200 GPU die shot, which i got off it's BGA package by heating it and cracking open.
Pity it's covered with metal mask in front, so cannot see inner layers beauty.



« Last Edit: October 09, 2013, 03:37:19 am by TiN »
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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #45 on: October 09, 2013, 03:35:32 am »
awesome stuff. are there any factories/test facilities like this in china/taiwan/korea? or are they just on the manufacturing site of things?
can you give us a factory tour some time freeelectron or is that shit highly classified? ^^
Plenty. TSMC is Taiwan. UMC too. Korea has massive fabs from Samsung, Hynix , and others.

But you are not going to get in. It's not so much that stuff is classified ( some of it is. forget taking pictures , let alone taking a smartphone or cellphone inside ) but the problem is that us sack of bones and meat bags are walking dust generators...
If they could, wafer fabs would be completely void of human presence.

@walshms. that's : interference lithography. that is the term that eluded me. It's been so long since i've been on that side of the entire semiconductor world... i've forgotten half of it..

it is like i described. even thought the knife blade itself is too wide, by putting it under 45 degrees you can make a cut smaller than the width of the knife. in the lithography process they use two light bundles , 90 degrees apart and 45 degrees offset from the plane. so if the plane is horizontal , one is shining left to right under a 145 degree angle, the other shines right to left under a 45 degree angle. Where the wavelength interferes with each other you get a standing wave ( i think. it's like the famous double slit experiment. http://en.wikipedia.org/wiki/Double-slit_experiment )
in the peaks you have light , so you are exposing the photoresist. In the valley there is absence of light so no exposure.

Instead of slits they use complex patterns the make the light beams coming from opposite directions interfere with each other and create the correct shadowed areas in the form of the wanted structure. Totally batshit crazy stuff.
ASML is the big name there.

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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #46 on: October 09, 2013, 03:41:27 am »
I had a question tho, is there any widely available solvent

Fuming nitric acid. But that is VERY dangerous stuff. And you need to heat it... which makes it even more dangerous.
That is how it is done in the industry. solvents don't work. The chip casing material is not soluble.

https://www.sumibe.co.jp/english/product/it-materials/epoxy/sumikon-eme/index.html

That is what is used for chip bodies. Sumitomo is by far the largest manufacturer of that stuff.
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Offline TheWelly888

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #47 on: October 09, 2013, 03:42:20 am »
Most Awesome Mailbag - Thanks Vincent!

You can do anything with the right attitude and a hammer.
 

Offline synapsis

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #48 on: October 09, 2013, 03:59:24 am »
Back in the 80's I grew up with a friend whose mom worked at Burr Brown. She brought home a bare wafer and some dies once. She kept the dies in a sugar bowl so they wouldn't get lost. ;) The wafer was tiny (size of my hand maybe), the wafers in the video look huge.

What happens to wafers that don't meet spec? Do they get recycled or are they used to level the breakroom table?
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #49 on: October 09, 2013, 04:11:51 am »
Back in the 80's I grew up with a friend whose mom worked at Burr Brown. She brought home a bare wafer and some dies once. She kept the dies in a sugar bowl so they wouldn't get lost. ;) The wafer was tiny (size of my hand maybe), the wafers in the video look huge.

What happens to wafers that don't meet spec? Do they get recycled or are they used to level the breakroom table?
bare wafers are immediately thrown back in the puddle of liquid silicon...
proces wafers are checked at each and every step. if a step fails you simply 'undo the step' be removing it.
let's say there was an etching problem with the nitride.. simply strip the photoresist completely and etch all nitride off. then apply a new layer. That is why we have those teststructures. each and every step is carefully monitored. Each layer can be 'undone'. so then the wafer is simply ran 1 step backward and it gets a redo. they call those rework lots. ( a lot is a FOUP carrying 25 wafers are a traveller boxing holding 2 'boats' each holding 25 wafers. )

Scrapped (broken) wafers are sent back to the silicon wafer maker. They recycle them into new ones. Silicon is 100% recyclable.

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Offline maros

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #50 on: October 09, 2013, 04:25:48 am »
If someone's courious about how pure silicon rods are made should take a look at Czochralski process invented by Polish scientist Jan Czochralski.
 


Offline DavidDLC

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #52 on: October 09, 2013, 07:34:55 am »
 

Offline DavidDLC

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #53 on: October 09, 2013, 07:40:41 am »
How do they design the chip ? Do they use a CAD software ? Like equivalent Altium or Zuken or similar to create PCBs ?

David.
 

Offline zoomtronic

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #54 on: October 09, 2013, 07:56:11 am »
Excellent video, I watch some of Your videos, because some are more interesting than others to me. I do electronics as a hobby, more programming lately. Also link to "Indistinguishable From Magic: Manufacturing Modern Computer Chips" are excellent way to figure out how production of modern day chips are going on.
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Offline tized

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #55 on: October 09, 2013, 08:01:04 am »
That video brings back memories...
My first steps in the industry were as a test development engineer, writing the test programs for the testers.
The company I worked for back then had several testers for engineering. The "cheap" ones, that only did digital, cost $500k. The more expensive ones, with mixed-signal capabilities, cost $4M (Teradyne Tigers). Each tester had a handler, which is the robot that gets trays of units to test and runs them on the test.
For each product there is a TIU (Tester Interface Unit), which are like the probecard (called SIU sometimes) Dave showed but bigger! A TIU would cost anything from $20k to $40k depending on the components you have on it and complexity. Of course you had to have several TIUs for each product; one for each tester and some spares to avoid downtime if one gets broken (and they often do). Each TIU has a test-socket, or several test-sockets for small components, like the ones in the video. The locker on the sockets (the top part) can come off and the handler will have a jig to match the socket, that can pick units up and place them on the TIU.
Now, the socket sits attached to the TIU with the pogo pins against the pads on one side, with the handler pushing hundreds to thousands of units with its manipulators, imagine the wear and tear on those boards and sockets.  At one time we had lots of weird problems with one of the testers. The technician from the vendor opens up the test head and blows pressurized air in it, out flies metal bits as if it were a CNC machine. On another occasion a handler lost its calibration in mid-run and tried to place unit through the TIU, I'll leave the damage assessment as an exercise.         

Hey, first post! *waves hand at everyone*

TiZed
 

Offline zoomtronic

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #56 on: October 09, 2013, 08:02:50 am »
I also found video on veritasium channel on YT
simple but very clear explanation of transistor working process.
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Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #57 on: October 09, 2013, 08:22:58 am »
How do they design the chip ? Do they use a CAD software ? Like equivalent Altium or Zuken or similar to create PCBs ?

David.
very similar. we have Schematic capture software. Typically Cadence Virtuoso or Mentor Pyxis. There is also Silvaco.
You have simple parts liek resistors and diodes and transistors. the symbols are the same , but the attached data is of a toally different calibre. layout geometry, layer thicknesses, parasitics ... it's all attached to the symbol.

Simulation is typically Mentor's Eldo or Cadence Ultrasim. Don't compare these tools with Multisim or LTspice. This is a completely different world. These simulators DO work ! The reason is that we do have accurate models. we know exactly how our transistors and other elements on the chip behave. There is no approximation or the classical trick of slapping in voltage to current converters and other 4 terminal elements like in 'little spices'. Engines like ELDO and UltraSim can simulate an entire chip with millions of transistors at transistor level , including all the parasitics injected in the layout of the chip. These tools are customized for each chip maker. The Eldo version that we use is not the same as the Eldo used by Maxim or Linear ! The simulation libraries are tuned for our process chemistries. you need to tell the simulator i am using BicMos 9 from manufacturer xyz for this design, or i am doing cmos x nanometer form that guy there.

These simulators only run on huge compute farms. A typical simulation cluster can have hundreds of processors all tackling the same design. Top level simulations can run multiple days.

Just like you have PCB layout tools there are IC layout Tools. Cadence Opus for example. there are p-cell generators and libraries just like in normal pcb. we just have more layers ... 50 to 60 layers for an average chip.
you place parts from library and wire em up according to the schematic.

Digital cruft is fully automatic. Cell placers create row and column distributions and autoroute the interconnects. parasitics are extracted and buffers are injected in nodes with lots of load.

This software is so expensive it cannot be bought. It is licensed for 1 year. The schematic capture tools are essentially free. anything else is paid per second the software runs and per processor core it claims. A single runtime licence costs multiple millions of dollars per year.

Key software makers in this field are Cadence, Mentor, Silvaco , Magma , Ansys and some others. All this stuff runs on bug iron ( used to be Sun Solaris on workstations) but is now mainly done on standard windows PC's using VNC connecting to the compute farm. The farm is a mix cluster of Sun and RHEL (Red hat enterprise linux) The tools are only supported on very carefully selected installations. you can't just take any linux and plonk that stuff on there. If you run into trouble the tool makers will tell you to go to hell. They use a particular build of the OS and do their testing on that install. If you want to use any other install they give no warranty it will work as designed...

There is a windows based IC design tool from a company called Tanner-EDA
 
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Offline tized

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #58 on: October 09, 2013, 08:30:32 am »
How do they design the chip ? Do they use a CAD software ? Like equivalent Altium or Zuken or similar to create PCBs ?

David.

EDA tools are used for the design of chips. Search for Cadence and Synopsis to have an over view of some of the major software vendors in that area.
Basically on one side you have the layout engineers who design the actual transistor level. They create a library of gates, latches and other basic components in a similar way to PCBs for a specific production process. On the other side there are the design engineers who functionally describe the chip logic in high level languages (Verilog and VHDL). In the middle you have the back-end engineers who take the design and "synthesize" using the process libraries in to gates and transistor, doing the blocks placement and routing. That's the over simplified version of the flow as there is much more to it: Architecture, Micro-Architecture, verification, static-timing analysis, DRC, emulation. And that's just the pre-silicon side...  :o
 

Offline open loop

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #59 on: October 09, 2013, 08:33:31 am »
Really enjoyed this video, It reminded me of a few things.

The photo on page 851 in "the art of electronics" second edition... Looks like a couple of engineers looking at a massive (5m by 5m) printout of the wafer mask. Would be interesting to see if these are still done today.

The test head reminds me of the skill that was required to make the early core memory modules. Where tiny ferrite beads were woven into copper wire by hand. I am very lucky to have core memory module myself.

I did spend a few days of my childhood breaking into old ICs to see the "silicon chip" I used a bench vice and blunt chisels - well they were blunt after I broke into a few ICs. If you want to easily photograph a chip then an old 27 series EEPROM may be interesting but it would only be memory cells. I also seem to remember that the early microprocessor chips had an EEPROM version and was windowed, got a couple of these and they may be worth looking into.


Anyway great video
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #60 on: October 09, 2013, 08:39:26 am »
Careful with moores law. That law is often misinterpreted !

Moores law says that every 12 to 14 months the number of transistors on a chip doubles.
nothing more...

it does not say 'that the chip needs to stay the same size !

There have been long periods where the transistors themselves would not shrink. we kept running 0.5 micron for 5 to 7 years ... the chips just became larger and larger. So moores law remained valid.
Then we switched to 250 nanometer. Did that violate moores law ? no the design still had x amount of transistors, you could simply put them on a smaller area.

Moores law essentially tells us one thing : desings are doubling in complexity every year and a half or so.
we are now at a few million transistors to turn blink an led...A typical remote control that reads a keypad and blink the Ir led used to be made with simple logic. a shiftregister and some timers. now we use 32 bit cpus with tons of code in flash eprom , adc to do the capsense  and some remotes even have color lcd's now... a far step from the first remote that used and LC tuned oscillator to transmit a few frequencies. the buttons on the remote changed the frequency. that's all...
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Offline M. András

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #61 on: October 09, 2013, 08:40:41 am »
just out of curiosity. there was a mentioning of led manufacturers, how many of the led company's have their own fab?. (<-it was a debate question from a sparky when they installed new fixtures in our warehouse and again goddam neon lights..) and how many of the ic company's have?. other lesser intresting question how much do they use from the gold bond wires lets say for a tqfp 208 package for the whole wafer? what other materials do they use for bond wires? like for those insanly high current fets etc
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #62 on: October 09, 2013, 08:41:36 am »

The photo on page 851 in "the art of electronics" second edition... Looks like a couple of engineers looking at a massive (5m by 5m) printout of the wafer mask. Would be interesting to see if these are still done today.

yes they are. the entire chip is plotted so you can scribble space allocation on there as the design goes. you can use a pen and draw what blocks you wan twhere. ideal for team meetings.
indivdual blocks may be plotted in detail to scribble remarks of how the layout needs tweaking
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Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #63 on: October 09, 2013, 08:42:13 am »
What happened to your finger at 10:50?

Wasn't just the finger:


Oh wow.  What happened?
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Offline Kempy

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #64 on: October 09, 2013, 09:48:55 am »
Great stuff, thanks Dave and Vincent! It's always amazing to see how the magic happens.
Also those nanometer probes, I guess, you cannot even breathe on it, or it will bend  :-DD :scared:

I had a question tho, is there any widely available solvent or chemical which can be used to remove/dissolve package epoxy of usual chip packages? I like taking photos of electronic gear, and tried couple ways to get die shots, but either shatter die or it gets badly damaged when trying remove epoxy mechanically. I have some dead modern CPUs and GPUs, which might be interesting to look at (lots actually, even some latest multi-billion transistor count chips) :)

Best one so far is nvidia geforce4 Ti4200 GPU die shot, which i got off it's BGA package by heating it and cracking open.
Pity it's covered with metal mask in front, so cannot see inner layers beauty.

Here is a video of how to de-cap chips at home (you do need a cnc mill however)
 

Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #65 on: October 09, 2013, 01:08:22 pm »
Great stuff, thanks Dave and Vincent! It's always amazing to see how the magic happens.
Also those nanometer probes, I guess, you cannot even breathe on it, or it will bend  :-DD :scared:

I had a question tho, is there any widely available solvent or chemical which can be used to remove/dissolve package epoxy of usual chip packages? I like taking photos of electronic gear, and tried couple ways to get die shots, but either shatter die or it gets badly damaged when trying remove epoxy mechanically. I have some dead modern CPUs and GPUs, which might be interesting to look at (lots actually, even some latest multi-billion transistor count chips) :)

Best one so far is nvidia geforce4 Ti4200 GPU die shot, which i got off it's BGA package by heating it and cracking open.
Pity it's covered with metal mask in front, so cannot see inner layers beauty.

Here is a video of how to de-cap chips at home (you do need a cnc mill however)


Why would you de-cap a chip?
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Offline jp430bb

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #66 on: October 09, 2013, 01:18:43 pm »
One guy decapped some microcontrollers to try and read out the mask-programmed firmware on them. 

Another reason would be to get the die size and pictures of the overall layout of the die, like how many cores and SRAM blocks are on a CPU. 
« Last Edit: October 09, 2013, 01:20:15 pm by jp430bb »
 

Offline jp430bb

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #67 on: October 09, 2013, 01:26:22 pm »
Back in the 80's I grew up with a friend whose mom worked at Burr Brown. She brought home a bare wafer and some dies once. She kept the dies in a sugar bowl so they wouldn't get lost. ;) The wafer was tiny (size of my hand maybe), the wafers in the video look huge.

What happens to wafers that don't meet spec? Do they get recycled or are they used to level the breakroom table?
bare wafers are immediately thrown back in the puddle of liquid silicon...
proces wafers are checked at each and every step. if a step fails you simply 'undo the step' be removing it.
let's say there was an etching problem with the nitride.. simply strip the photoresist completely and etch all nitride off. then apply a new layer. That is why we have those teststructures. each and every step is carefully monitored. Each layer can be 'undone'. so then the wafer is simply ran 1 step backward and it gets a redo. they call those rework lots. ( a lot is a FOUP carrying 25 wafers are a traveller boxing holding 2 'boats' each holding 25 wafers. )

Scrapped (broken) wafers are sent back to the silicon wafer maker. They recycle them into new ones. Silicon is 100% recyclable.

Once wafers have had metal layers deposited, silicon wafer makers won't want them back.  Copper, in particular, is poison for silicon wafers in the front-end (early) process steps. 
 

Offline elCap

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #68 on: October 09, 2013, 01:46:22 pm »
@walshms. that's : interference lithography. that is the term that eluded me. It's been so long since i've been on that side of the entire semiconductor world... i've forgotten half of it..

it is like i described. even thought the knife blade itself is too wide, by putting it under 45 degrees you can make a cut smaller than the width of the knife. in the lithography process they use two light bundles , 90 degrees apart and 45 degrees offset from the plane. so if the plane is horizontal , one is shining left to right under a 145 degree angle, the other shines right to left under a 45 degree angle. Where the wavelength interferes with each other you get a standing wave ( i think. it's like the famous double slit experiment. http://en.wikipedia.org/wiki/Double-slit_experiment )
in the peaks you have light , so you are exposing the photoresist. In the valley there is absence of light so no exposure.

Instead of slits they use complex patterns the make the light beams coming from opposite directions interfere with each other and create the correct shadowed areas in the form of the wanted structure. Totally batshit crazy stuff.
ASML is the big name there.
As for photomasks, I think the Phase shift mask (PSM), which uses interference, is quite common these days. Then there are other mask types like half tone, gray tone and so on. For binary mask the optical proximity correction technique is probably mandatory for high performance mask. For anyone interested, Wikipedia is a good starting point http://en.wikipedia.org/wiki/Photomask

Other "fun facts" about photomask: Mask substrates are made of quartz for the optical and thermal properties. Photomasks for semiconductor are normally 4 times bigger than the intended chip size. But for displays (LCD, plasma, ...) the photomasks are 1:1, making the masks for the biggest TV huge, heavy and expensive.
For making the photomask there are two main techniques; laser and e-beam. Semiconductor masks use both, display masks only laser.

Someone mentioned invar as a material with low thermal expansion. Another material used in semiconductor industries is Zerodur, thermal expansion close to zero. Quite cool stuff. But even with quartz, invar and Zerodur the temperature control for exposing systems has to be very good, within a 1000 of a degree. (e.g. 23.000 +/-0.001 C)
 

Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #69 on: October 09, 2013, 01:51:04 pm »
One guy decapped some microcontrollers to try and read out the mask-programmed firmware on them. 

Another reason would be to get the die size and pictures of the overall layout of the die, like how many cores and SRAM blocks are on a CPU.

Ok I just reread my question and realized I worded it very badly.  I meant to ask what de-lidding is (I'm new at this).
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Offline jp430bb

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #70 on: October 09, 2013, 02:13:32 pm »
@walshms. that's : interference lithography. that is the term that eluded me. It's been so long since i've been on that side of the entire semiconductor world... i've forgotten half of it..

it is like i described. even thought the knife blade itself is too wide, by putting it under 45 degrees you can make a cut smaller than the width of the knife. in the lithography process they use two light bundles , 90 degrees apart and 45 degrees offset from the plane. so if the plane is horizontal , one is shining left to right under a 145 degree angle, the other shines right to left under a 45 degree angle. Where the wavelength interferes with each other you get a standing wave ( i think. it's like the famous double slit experiment. http://en.wikipedia.org/wiki/Double-slit_experiment )
in the peaks you have light , so you are exposing the photoresist. In the valley there is absence of light so no exposure.

Instead of slits they use complex patterns the make the light beams coming from opposite directions interfere with each other and create the correct shadowed areas in the form of the wanted structure. Totally batshit crazy stuff.
ASML is the big name there.
As for photomasks, I think the Phase shift mask (PSM), which uses interference, is quite common these days. Then there are other mask types like half tone, gray tone and so on. For binary mask the optical proximity correction technique is probably mandatory for high performance mask. For anyone interested, Wikipedia is a good starting point http://en.wikipedia.org/wiki/Photomask

Other "fun facts" about photomask: Mask substrates are made of quartz for the optical and thermal properties. Photomasks for semiconductor are normally 4 times bigger than the intended chip size. But for displays (LCD, plasma, ...) the photomasks are 1:1, making the masks for the biggest TV huge, heavy and expensive.
For making the photomask there are two main techniques; laser and e-beam. Semiconductor masks use both, display masks only laser.

Someone mentioned invar as a material with low thermal expansion. Another material used in semiconductor industries is Zerodur, thermal expansion close to zero. Quite cool stuff. But even with quartz, invar and Zerodur the temperature control for exposing systems has to be very good, within a 1000 of a degree. (e.g. 23.000 +/-0.001 C)

Fun fact about silicon and coefficient of thermal expansion: at liquid nitrogen temperature, silicon's CTE is close to zero.  That makes LN2-cooled silicon popular for mirrors for high-power x-ray beams. 

 

Offline Razor512

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #71 on: October 09, 2013, 10:11:56 pm »
If a company is going to charge over a million dollars a year for software, won't companies designing these IC's just pirate the software, or weigh the cost of purchasing a license to the software, to the cost of just allocating a few of their programmers to try and crack the software?

At least until they charge a reasonable price, eg $100 for lifetime use of per version of the software, or if it needs frequent updating, then $30 a month or something?
 

Offline quarros

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #72 on: October 09, 2013, 10:23:15 pm »
If a company is going to charge over a million dollars a year for software, won't companies designing these IC's just pirate the software, or weigh the cost of purchasing a license to the software, to the cost of just allocating a few of their programmers to try and crack the software?

At least until they charge a reasonable price, eg $100 for lifetime use of per version of the software, or if it needs frequent updating, then $30 a month or something?

You do realize what kind of a colossal lawsuit would ensue after a thing like that?  :palm:
If you have a market that has very few players, than practically no secret can be held for long.
 

Offline tized

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #73 on: October 09, 2013, 10:56:54 pm »
If a company is going to charge over a million dollars a year for software, won't companies designing these IC's just pirate the software, or weigh the cost of purchasing a license to the software, to the cost of just allocating a few of their programmers to try and crack the software?

At least until they charge a reasonable price, eg $100 for lifetime use of per version of the software, or if it needs frequent updating, then $30 a month or something?

A. The software licenses are still small change relative to the cost of the FABs and engineers.
B. Those are all tape-out proven software suits, meaning several products have been successfully taped-out using that software. With each tape-out costing millions of dollars, no one will take a risk with cracked/hacked software.
B. Smaller business don't pay millions but tens to hundreds of thousands of dollars a year for just for a few licenses. The licensing schemes are gradual.
C.  When a company does get to the millions of dollars a year area, the licenses include training vouchers for the staff, every bug report gets seriously addressed and you might even get on site support people.

As the saying goes "You get what you paid for".
 

Offline quarros

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #74 on: October 09, 2013, 11:01:11 pm »
A. The software licenses are still small change relative to the cost of the FABs and engineers.
B. Those are all tape-out proven software suits, meaning several products have been successfully taped-out using that software. With each tape-out costing millions of dollars, no one will take a risk with cracked/hacked software.
B. Smaller business don't pay millions but tens to hundreds of thousands of dollars a year for just for a few licenses. The licensing schemes are gradual.
C.  When a company does get to the millions of dollars a year area, the licenses include training vouchers for the staff, every bug report gets seriously addressed and you might even get on site support people.

As the saying goes "You get what you paid for".

Additionally you can get the software specifically tailored to your own fab needs!
 

Offline senso

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #75 on: October 09, 2013, 11:24:58 pm »
Remenber that software like that is NOT like the arduino IDE, its just a little bit more advanced, with lots of code(and maths to simulate everything accurately)..
You are paying for a software that you can trust.
 

Offline moemoe

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #76 on: October 09, 2013, 11:35:29 pm »
https://github.com/maugsburger/
Breadboard Adapters featured in EEVBlog #573 on Tindie
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #77 on: October 10, 2013, 02:21:38 am »
that software is so expensive simply because there are only a few users in the world. They sell maybe a few hundred to a thousand licences... Developing that stuff is super expensive.
And you have programmers on duty. If we find a problem it gets tackled immediately.

Pirating is out of the question. At a certain point you need to hand off the design to a factory so it can be produced... the moment they read your data you would get caught. You can bet your money that stuff calls 'home'...

these licences are shared. there is all sorts of payment plans. per minute of runtime , per design , per number of users... you can pay weekly, monthly , half yearly and so. on.

you can turn on and of licences as you want. if work is slowing down and you don't need 6 simulation licences and can make do with 4 for a while you turn those unused 2 to non active for a couple of months. later you can reactivate them.

you also pay for special usage like sharing between sites. typically a licence is bound by geographical area. If we have available time and want to give people form france access to our farm you pay for that.

And a million dollars is only for 1 licence... Large silicon makers have a few hundred licences...
and then there is customization of the tools... you do not want to know what companies like IBM and Intel are paying for their custom build...

But all that stuff is irrelevant. This is top notch quality software. it has to work. If it produces output and a maskset is made to make a chip... a 18nm maskset ( those quartz plates with the pattern on em to expose the layers... there can be up to 50 different plates needed to make 1 chip . the collection of masks is called the maskset ) runs in the order of 10 to 12 million $ ...

If that software produces a mistake in the mask ... someone is going to have to 'eat' that... and it has happened !
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Offline Zbig

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #78 on: October 10, 2013, 02:37:02 am »
[..]
Someone mentioned invar as a material with low thermal expansion. Another material used in semiconductor industries is Zerodur, thermal expansion close to zero. Quite cool stuff. [..]

Yes, but it can also be a lukewarm or hot stuff and it still doesn't care! How cool is that! ;)

« Last Edit: October 10, 2013, 04:12:59 am by Zbig »
 

Offline Sionyn

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #79 on: October 10, 2013, 06:54:47 am »
awesome free electron and dave should take a trip round your foundry
eecs guy
 

Offline Monkeh

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #80 on: October 10, 2013, 06:55:47 am »
At least until they charge a reasonable price, eg $100 for lifetime use of per version of the software, or if it needs frequent updating, then $30 a month or something?

What on earth are you smoking?

$100 for lifetime use? $30 a month? How are the programmers going to get paid? There are not millions of users of this sort of software.
 

Offline mamalala

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #81 on: October 10, 2013, 07:17:42 am »
Pirating is out of the question. At a certain point you need to hand off the design to a factory so it can be produced... the moment they read your data you would get caught. You can bet your money that stuff calls 'home'...

While pretty much unrelated, the CadSoft folks deserve some credit for how they implemented their protection for Eagle. You can crack the software rather easily. However, they are very quick to blacklist such cracks. The result is that only the cracked version can open the files made with it. Everyone else gets a subtle error message.... No need for calling home stuff in this instance.

But yes, i agree, it would be rather silly to try and use any illegal copy of such a sophisticated software like the ones used to make wafer "layouts". The risk is simply too high compared to the cost of everything else.

Greetings,

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Offline marshallh

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #82 on: October 10, 2013, 07:18:55 am »
Found a picture of Altera's 20nm serdes characterization jig, with similar BGA socket seen in the video.

Verilog tips
BGA soldering intro

11:37 <@ktemkin> c4757p: marshall has transcended communications media
11:37 <@ktemkin> He speaks protocols directly.
 

Offline RupertGo

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #83 on: October 10, 2013, 10:46:40 am »
That is a truly awesome mailbag - and video.

I've been on a couple of fab tours, but they're much rarer than they used to be. Companies are also much more leery about handing out wafers, so I'm most impressed that you got that consignment; I used to be able to get stuff for demos and talks just by asking for them from Intel, but now even their own marketing and PR lot can't get hold of them - in general. You can pick up wafers on eBay from time to time, but I'm never quite sure where they come from and they don't seem to come with much information. Best freebie I ever had was when I visited Rockwell in the glory days of dial-up modems; they gave me and the rest of the journos a wafer full of DSPs with a clock mounted in the middle. Got shattered in the office when some damn fools were chucking a ball about.

Although cameras are very restricted on fab tours, here's one of my favourite pictures from one of Intel's Israeli fabs - http://www.flickr.com/photos/onaliencinema/83541192/#. Got into a lot of trouble on that one as I obtained (entirely legitimately) a yield graph with real numbers on it. No matter that it was for an obsolete process from years previously: you have never seen an entire company lose its sense of humour as quickly as when we printed that. That and the questions we asked about the new fab being built on what was, even by Israeli standards, land that still belonged to the Palestinians with the paperwork to prove it. But that, as they say, is a whole 'nother story. When one company provides a few percent of a country's GDP...

One of the tours I did was when copper was just being introduced, and the internal procedures to make sure you didn't get cross-contamination were insane. As they had to be; if your line gets poisoned the costs (as has been said) are horrendous, and it really doesn't take much.

A thing not in the mailbag but that impressed me when I saw it is a diamond heatsink. Diamond has good thermal conductivity, and there are tests you can do on working chips to characterise the operational parameters of transistors that involve scanning the circuitry with a laser. How do you do that on a running chip that's dissipating maybe 100 watts? You can't just run up a bare die - so, diamond heatsink. It's surprisingly cheap, I was told, especially by fab standards, maybe a couple of thousand dollars, as industrial diamond technology is much cheaper than the (entirely artificial) jewellery market. But how cool (sorry) is that...

 

Offline TNb

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #84 on: October 10, 2013, 12:16:27 pm »
I'm quite surprised by this big circle testing cartridge Dave showed in vid, but still - are you 100% sure that wiring is hand made?
I mean, the possibility of human-related error in this is soooooooo ungodly high, it's seems very unlikely it is done by human. Just imagine if you did all that wiring and then something doesn't work the way it needs, you will lose another month or two finding out where is the problem...
Does anybody know more about this stuff? Is it really something like 400 hand-welded pins? O_O
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #85 on: October 10, 2013, 01:29:36 pm »
Yes. fully handmade.

The way they build these things is using a split vision system. they have the actual pattern at right scale of where the needles need to go. They use a UV curable resin.
The needles are ready made and the tip bent as well as the tail spot-welded on. So they just need to pick one depending on the current and the layer they are working on. there is only 6 or 7 different ones.

they apply a bit of resin , clamp the needle in a micromanipulator, position it correctly. At this point the tail of the needle already sits in the resin. they expose it to uv for a few seconds, the resin hardens and the needle is set.
Then the sleeve is slid over the bare wire , cut to length and the wire is soldered to the correct dot on the interface board. another dab of resin and a shot of UV sets that. Next needle.

When all is done they put a jig over the assembly and then fill that with the black resin you see around the needles. the whole thing then goes in a vacuum chamber to pull out any air bubbles in the black resin. Once that has hardened the fixture is ready.

We have (had ?) people in house that can do quickie prototypes of these. By the time the first prototype chips come out of the fab we have one of these for testing. once we go in production then the adapters get ordered from a subcontractor. I've seen them build these ( simpler ones for 44 pin devices ) in 1994 when i was working in the fab.
I donlt know if they still build them in house.. probably not.
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Offline elCap

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #86 on: October 10, 2013, 01:53:40 pm »
[..]
Someone mentioned invar as a material with low thermal expansion. Another material used in semiconductor industries is Zerodur, thermal expansion close to zero. Quite cool stuff. [..]

Yes, but it can also be a lukewarm or hot stuff and it still doesn't care! How cool is that! ;)
And it can even be the same piece of Zerodur! Hot in one end and cool in the other, still don't care much.


As for semicon software:
There are actually free sw available. A few examples: http://www.staticfreesoft.com/index.html , http://www.peardrop.co.uk/glade/
But they are probably not used to make an Intel i7 processor.. more for testing, education, and simple chips.
Then there are a few nice viewers available for free, for instance EBV viewer by Nippon Control Systems (http://www.nippon-control-system.co.jp/en/index.html) I lost the download page, they have no link to it on their webpage so have to contact them. It can even plot gerbers.
« Last Edit: October 10, 2013, 01:56:38 pm by elCap »
 

Offline Goophy629

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #87 on: October 10, 2013, 03:39:51 pm »
wondering how the messy circuit is actually "printed" on the the flat disk then cut into pieces sold for hundreds bucks like a computer cpu |O

awesome video indeed

any high quality pictures this time? :-+
 

Offline EvilGeniusSkis

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #88 on: October 10, 2013, 04:48:28 pm »
Great stuff, thanks Dave and Vincent! It's always amazing to see how the magic happens.
Also those nanometer probes, I guess, you cannot even breathe on it, or it will bend  :-DD :scared:

I had a question tho, is there any widely available solvent or chemical which can be used to remove/dissolve package epoxy of usual chip packages? I like taking photos of electronic gear, and tried couple ways to get die shots, but either shatter die or it gets badly damaged when trying remove epoxy mechanically. I have some dead modern CPUs and GPUs, which might be interesting to look at (lots actually, even some latest multi-billion transistor count chips) :)

Best one so far is nvidia geforce4 Ti4200 GPU die shot, which i got off it's BGA package by heating it and cracking open.
Pity it's covered with metal mask in front, so cannot see inner layers beauty.

take a propane torch to the IC until the black plastic turns white. it will then be extremely brittle.
here's a video:
 

Offline eripaha

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #89 on: October 10, 2013, 06:16:50 pm »
Its wonderful to see this stuff explained. I dont think i would have ever even known about this stuff if dave did not make a video about these.
 

Offline Stonent

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #90 on: October 10, 2013, 08:56:36 pm »
The larger the government, the smaller the citizen.
 

Offline Stonent

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #91 on: October 10, 2013, 09:19:18 pm »
If a company is going to charge over a million dollars a year for software, won't companies designing these IC's just pirate the software, or weigh the cost of purchasing a license to the software, to the cost of just allocating a few of their programmers to try and crack the software?

At least until they charge a reasonable price, eg $100 for lifetime use of per version of the software, or if it needs frequent updating, then $30 a month or something?

You do realize what kind of a colossal lawsuit would ensue after a thing like that?  :palm:
If you have a market that has very few players, than practically no secret can be held for long.

Also you basically can't pirate software like that you typically have a license key server that validates each copy or in some cases a dongle with and encrypted code on it. I have seen lost dongles cost 5 figures to be replaced on some programs (z max)

Also when I worked at a company that made laser eye surgery equipment they had all sorts of strange financing options so that new doctors could afford high end equipment. So one plan would be that at the end of every month the laser would call home and upload how many surgeries have been done and basically the doctor would have to give 75% of the cost of profit back as payment and have to buy custom packed surgery kits from our company for X months or years until it is paid for. Etc.

So yeah he may be driving an s class Mercedes but it is leased and he is living on peanut butter sandwiches until that's paid for.

Again same with high end software. They can charge per use, per hour, per minute.

« Last Edit: October 10, 2013, 09:31:12 pm by Stonent »
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Offline SArepairman

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #92 on: October 10, 2013, 10:02:13 pm »
is it really that hard to crack?

can someone upload a copy?  :box:
 

Offline tized

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #93 on: October 10, 2013, 10:26:13 pm »
is it really that hard to crack?

can someone upload a copy?  :box:

Not really, they use the flexlm licensing manager which has been cracked many times before. Probably, if looking in the right corners of the Internet, you could find that software, as students use it to learn the tools of the trade. But no company, self-respecting or otherwise, will dare to use pirated software, this is a very IP sensitive industry.
It would be very entertaining to see someone trying to submit GDS files to TSMC from a cracked Cadence suit. Just tell me before so I can prepare the popcorn...
 

Offline elgonzo

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #94 on: October 11, 2013, 12:58:19 am »
@free_electron and all the others, thanks for the insights into the "secret world" of chip production.  :-+
I haven't seen Dave's video yet, but after seeing Dave's bunny suit dance :-DD i decided to watch Dave's mailbag video as my today's evening prime time programme  :clap:
« Last Edit: October 11, 2013, 01:06:10 am by elgonzo »
 

Offline kphannan

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #95 on: October 11, 2013, 01:12:13 am »
Great mailbag.  I never worked in fab, but got to dabble a bit in college.  Design work was done on Apollo workstations then paper tape to lithography..... Boy those were the days.
 

Offline brabus

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #96 on: October 11, 2013, 01:17:32 am »
REALLY COOL Mailbag, I watched the video never shutting my eyes. :-+

is it really that hard to crack?

can someone upload a copy?  :box:

I don't understand what's the deal with cracking such a software.

Let me explain the point with an example from my job.
I am using a very particular software, used in the automotive industry, to deal with xCU datasets.
It is sold with pretty expensive licenses, but... there is no crack at all! No serial code, no passwords, nothing at all.

You can just install it on your desktop PC and work with it.

What's the point?
Well... On the very first time you try to use some reworked files (flashing them into the ECU of someone's car, in exchange of little money), someone will eventually know that you used that cracked software.
It's like farting in a elevator, except for the fact that you make a very loud and clear noise all over the world.
You would be immediately identified, and you would not only be sued and lose (all your) money, but also marked forever with the sign of dishonesty. You are OUT of business, forever.

Some "worlds" (e.g. automotive, silicon, racing, power, ...) are VERY small, everyone knows everyone, so it's pretty impossible to obtain any benefit from a cracked software.

It's like stealing the Cullinan diamond and then sell it on ebay with your name, address, personal photo and GPS position of your house, waiting with your pants down. ;D

http://en.wikipedia.org/wiki/Cullinan_Diamond
« Last Edit: October 11, 2013, 01:24:41 am by brabus »
 

Offline just_fib_it

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #97 on: October 11, 2013, 03:55:04 am »
Wafers are cut whit a mechanical saw? is that real?

As free_electron said, mechanical sawing is one way of dicing. However, laser dicing offers thinner cuts and therefore less wasted wafer space. Where I work we mostly make very small microcontrollers (think tens of thousands of dies on a wafer), so hundreds of cuts are needed in both directions. Even with a very thin saw blade the losses with mechanical sawing would add up quickly.
 

Offline elgonzo

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #98 on: October 11, 2013, 04:04:41 am »
image of a tester : http://www.teradyne.com/pressRoom/images/UltraFLEX-HD.tif (warning ; 43 megabyte file ! )
that testhead holds 1 chip under test ! if you ook inbetween the operator's arms you see the large plumbing fixtures that pipe liquid nitrogen into the head.. the chip is actually cycled , cold ( -30 degrees , ambient , 25 and hot (125) )

Vincent, do you know by chance why the head unit of the machine is rotatable around an horizontal axis?

The upside-down logo on the lower part of the front panel of the rotating unit indicates that it is 'normal' for the unit to operate in 180 degree orientation. My guess would be to either support two different chip designs alternately/subsequently without requiring down-time for swapping the test head, or to double throughput by using two test heads simultaneously.

 

Offline elgonzo

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #99 on: October 11, 2013, 04:13:00 am »
Wafers are cut whit a mechanical saw? is that real?

As free_electron said, mechanical sawing is one way of dicing. However, laser dicing offers thinner cuts and therefore less wasted wafer space. Where I work we mostly make very small microcontrollers (think tens of thousands of dies on a wafer), so hundreds of cuts are needed in both directions. Even with a very thin saw blade the losses with mechanical sawing would add up quickly.

And not to forget: Stealth dicing - laser cutting wafers from within. That sound so strange that it is hard to believe. But it is actually true .
 

Offline tized

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #100 on: October 11, 2013, 05:52:26 am »
image of a tester : http://www.teradyne.com/pressRoom/images/UltraFLEX-HD.tif (warning ; 43 megabyte file ! )
that testhead holds 1 chip under test ! if you ook inbetween the operator's arms you see the large plumbing fixtures that pipe liquid nitrogen into the head.. the chip is actually cycled , cold ( -30 degrees , ambient , 25 and hot (125) )

Vincent, do you know by chance why the head unit of the machine is rotatable around an horizontal axis?

The upside-down logo on the lower part of the front panel of the rotating unit indicates that it is 'normal' for the unit to operate in 180 degree orientation. My guess would be to either support two different chip designs alternately/subsequently without requiring down-time for swapping the test head, or to double throughput by using two test heads simultaneously.

The test head will normally be docket to a handler, a machine that feeds the tester units for testing. Different handlers have different docking configurations, so the test head sits on a manipulators that enable it to dock in any configuration. At a placed I worked we had two kinds of handlers; one where the docking was horizontal and the test head would simply "slip" under it. The other handler had vertical docking, so the test head had to be rotated by 90 degrees and then attached.

Some tester can have two test heads, but as far as I know it's a rare configuration. 

For different products you don't have to replace the test head, but just the "Tester Interface Unit" (TIU), which is a bit like the probecard that was shown in the video. Replacing the TIU is a breeze, just pop one off and put the other one on.
 

Offline algorath

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #101 on: October 11, 2013, 03:21:06 pm »
here´s another interesting vid from 2005 from micronas in freiburg, germany

 

Offline amyk

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #102 on: October 12, 2013, 12:29:31 am »
Probably, if looking in the right corners of the Internet, you could find that software, as students use it to learn the tools of the trade. But no company, self-respecting or otherwise, will dare to use pirated software, this is a very IP sensitive industry.
I've looked through some Chinese IC design forums... I can't read the language but Google Translate gives back rather interesting conversations and links to even more interesting stuff for download.

"What goes on in China, stays in China"...? :scared:
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #103 on: October 12, 2013, 02:02:19 am »
Here is the front-end for the Micronas movie ( Micronas is a finnish company owned by Nokia that bought ITT intermetall from Germany )

These are very good movies. it gives a clear view of what goes on. If you watched Daves video first you will instantly recognize the stuff i sent him.


« Last Edit: October 12, 2013, 05:57:44 am by free_electron »
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Offline A Hellene

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #104 on: October 12, 2013, 05:36:15 am »
Vincent (aka 'free_electron'),
You da man!

Thank you, very much, for your efforts.
You have my full respect, by dear fellow man.


-George
« Last Edit: October 12, 2013, 05:38:04 am by A Hellene »
Hi! This is George; and I am three and a half years old!
(This was one of my latest realisations, now in my early fifties!...)
 

Offline Dave

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #105 on: October 12, 2013, 07:04:03 am »
This was the most interesting mailbag ever. I was glued to my computer screen for the entire 40 minutes. Thanks for providing the goodies, free_electron! :D

Good job on the macro shots, Dave. I know how difficult it can be to get a good macro shot with a camera, let alone a video camera. :-+
<fellbuendel> it's arduino, you're not supposed to know anything about what you're doing
<fellbuendel> if you knew, you wouldn't be using it
 

Offline hikariuk

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #106 on: October 13, 2013, 01:57:50 am »
Favourite part

Did you watch after the credits?

Yes, and I agreed with you entirely :)
I write software.  I'd far rather be doing something else.
 

Offline bitwelder

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #107 on: October 13, 2013, 02:51:22 am »
Awesome mailbag!
Thanks Dave & Vincent
 

Offline MetraCollector

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #108 on: October 13, 2013, 03:36:17 am »
Very similar DIB board topology to ONSemi boards. I sometimes solder generic boards to prototype it and then belgian ONSemi do the layout and fabricate it.
Sometimes it is very difficult to (de)solder these 16layer 5mm thick fuckers. ;D Weller WECP20 and 450°C isn't enough. |O
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #109 on: October 13, 2013, 10:15:14 am »
IS Hubert De Keyser still there ? That was their board guy when i started there. (back in the days it was called Mietec -> Alcatel microelectronics -> ST for 1 day -> AMIs -> on semi
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Offline kcozens

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #110 on: October 13, 2013, 11:10:58 am »
Thank you Dave, and Vincent, for an amazing video and interesting bits of kit. I was able to see the video in HD so I was amazed at the tiny size of some of those probes. I'd hate to be the one who wires up that probe card. I wonder how you would go about testing the probe card to ensure that the wiring was correct.

That multi-layer PCB isn't that impressive to me. A few years back I did some consulting for an elecctronics company that had their own PCB manufacturing division. I was shown a board in the shape of an H (or capital I) they had made that had 100 (one hundred) layers. I don't remember its exact dimension. It was around 3" side to side, and around 1/4" to 1/2" thick, AFAICR. The whole assembly formed a transformer. Now that was an impressive assembly.
« Last Edit: October 13, 2013, 11:15:48 am by kcozens »
 

Offline samc

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #111 on: October 13, 2013, 11:27:08 am »
Fascinating video -- thank you Vincent and Dave!

I've been curious about the silicon fab process, so seeing some of the gear is a treat.

Thank you!
 

Offline 99tito99

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #112 on: October 14, 2013, 03:06:46 pm »
Hi Dave:  Looked at your flickr photos of this beast and you are right, it is down-right pornographic.  Things like this should be shielded from young children and the faint of heart.  I have to go now I'm getting palpitated.  Cheers, Mark * * *
 

Offline glicos

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #113 on: October 14, 2013, 10:52:43 pm »
I'm quite surprised by this big circle testing cartridge Dave showed in vid, but still - are you 100% sure that wiring is hand made?
I mean, the possibility of human-related error in this is soooooooo ungodly high, it's seems very unlikely it is done by human. Just imagine if you did all that wiring and then something doesn't work the way it needs, you will lose another month or two finding out where is the problem...
Does anybody know more about this stuff? Is it really something like 400 hand-welded pins? O_O

Yes TNb, it's all handwired. The probecard posted by dave is just one type. This is categorized as "Cantiliver Probe Cards" and the oldest type of probecard. Wait and see MEMS based probe card etc.

As of now, im still connected with probe card manufacturer here in the philippines. Loved to post videos and picture of every stage of probecard manufacturing but need permission from our company.
 

Offline ohmineer

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #114 on: October 15, 2013, 05:15:41 am »
Thanks to Dave and Vincent for such an educational video.
I did a course on microelectronics some years ago and had the opportunity to visit a clean room. Obviously, we weren't allowed to enter inside but we saw through the windows how the scientists were working. By that time, I also was impressed about the funny clothing that Dave is wearing in the video.

This video from Intel is quite illustrative too,


 
 

Offline amyk

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #115 on: October 16, 2013, 11:02:31 pm »
Try to guess what Dave is saying in these...






:-DD
 

Online EEVblog

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #116 on: October 16, 2013, 11:18:58 pm »
Screen captures of failed youtube Aussie captioning could get their own website!
YoutubeTranslateFails.com  ;D
 

Offline mamalala

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #117 on: October 17, 2013, 05:39:21 am »
They probablay have an army of chinese locked up in the basement who do the translations ;-D At least it sure reads like chinglish...

Greetings,

Chris
 

Offline senso

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #118 on: October 17, 2013, 05:55:05 am »
Sily kid sounds like silicone
wife is wafer
But its funnier un-corrected.
 

Offline MetraCollector

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #119 on: October 18, 2013, 10:15:02 pm »
IS Hubert De Keyser still there ? That was their board guy when i started there. (back in the days it was called Mietec -> Alcatel microelectronics -> ST for 1 day -> AMIs -> on semi
I forgot to reply ! ;D
I looked in the directory now and Hubert is still there ! However I have never seen him in the email conversation yet.
 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #120 on: October 19, 2013, 01:30:44 am »
IS Hubert De Keyser still there ? That was their board guy when i started there. (back in the days it was called Mietec -> Alcatel microelectronics -> ST for 1 day -> AMIs -> on semi
I forgot to reply ! ;D
I looked in the directory now and Hubert is still there ! However I have never seen him in the email conversation yet.
SO you are in the Brno site then ? i was there for a few weeks in the late 1990's to help set up the lab. The guys running the design centre then were Aarnout Wieers and Jacques Bertin.
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Offline shk1d29

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #121 on: October 19, 2013, 01:51:42 am »
Hey Dave, have you tried looking for hidden images on the dies/wafers using a microscope? A time consuming task for sure.

Something like:
http://www.wired.com/gadgetlab/2011/04/gallery-silicon-art/


Cheers!
 

Offline ShamilaBW

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #122 on: October 20, 2013, 08:08:34 pm »
Thanks Vincent & Dave!!!  :clap:
 

Offline Kirill

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #123 on: October 21, 2013, 07:53:39 pm »
Why would you de-cap a chip?
e.g. to reverse engineer, like it was done with mifare classic: https://www.usenix.org/legacy/events/sec08/tech/full_papers/nohl/nohl_html/index.html
You generally don't need to decap RFID chips at all for they are just bare dies glued onto 2 metal pads inside a tag. Mifare is not an exception - you can just cut most of the tags with a scalpel and you get all the internal stuff fully accessible. Sometimes the tags are made of thick paper and it is even simplier than that. 
« Last Edit: October 21, 2013, 07:55:22 pm by Kirill »
 

Offline moemoe

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #124 on: October 30, 2013, 07:03:43 pm »
You generally don't need to decap RFID chips at all for they are just bare dies glued onto 2 metal pads inside a tag. Mifare is not an exception - you can just cut most of the tags with a scalpel and you get all the internal stuff fully accessible. Sometimes the tags are made of thick paper and it is even simplier than that.
Did you read the arcticle? I bet you didn't.

It is about reverse engineering the logic circuits inside/on the die and reverse engineer their poor crypto.
https://github.com/maugsburger/
Breadboard Adapters featured in EEVBlog #573 on Tindie
 

Offline bronson

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #125 on: February 19, 2014, 04:53:44 pm »
How do they slip the tiny kapton sleeves over the even tinier wires? That looks long and really fiddly.

Apply a little vacuum to one end maybe? Any sort of heat shrink action? Alcohol lubricant that evaporates?
 

Offline EvilGeniusSkis

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #126 on: November 24, 2014, 04:29:19 pm »
to me it looks like the probe card would not be very difficult to solder, just tedious.

also why wasn't @freeelectron on skype to help dave explain things?

what about taking a second look at some of the small things with your tagarno microscope dave?
 

Offline JBaczuk

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #127 on: February 25, 2015, 02:21:53 pm »
Does anyone know of a good source for the type of pogo pins used in that BGA adapter?  I found some on sparkfun, but they are $1 per pin!  Also on ebay, but comes from China so it takes almost a month to get to the states.  Thanks!
 

Offline aqarwaen

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #128 on: June 23, 2019, 01:14:06 am »
found this video..

 

Offline free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #129 on: June 29, 2019, 11:51:33 pm »
cool find. !
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