EEVblog #648 - Mailbag

[robrenz]

Most excellent Mailbag Monday    Love the knife, the only thing to top that would be to use a Binford 6100 chainsaw to open the packages a la Tim the Tool Man. (Home improvement/ tool time)

[WarSim]

About the core memory.

I watched core planes being made on a field day from school.

Where was that? Almost all production of core stores went to South East Asia in the very early days, as part of the first wave of moving production to cheap labour countries. It wasn't just about hourly costs, though. This work had a bad effect of people's eyesight, and in places with poor worker protection, they just tossed out and replaced the assembly line workers every couple of years. Not a very noble part of the history of electronics.

I think at the very end they were able to automate the assembly of these things. They certainly pushed up the density a lot. Early 70s core stores were far smaller than early 60s ones. As you said, core continued for a long time in high reliability and radiation sensitive applications. Early DRAM just couldn't match the robustness of core stores, although its density and speed quickly took the lead.

Yes commercial core memory was sent out of country.  The poster mentioned aerospace and military.  These industry stayed at home almost until it was replaced.  I say almost because a political game sent procurement out of country just before the replacement was finalized. 

Thank you for the"almost all qualifier".  I am glad to see that some people realize that commercial/industrial are not the only electronics industries. 

[djacobow]

Regarding the destructive reads: of course, reads from DRAM are destructive, too. Every read needs to be followed by a write of the same data. It's all handled transparently by the chip, bit it does have to happen.

[coppice]

Regarding the destructive reads: of course, reads from DRAM are destructive, too. Every read needs to be followed by a write of the same data. It's all handled transparently by the chip, bit it does have to happen.

That's not true of either SRAM or DRAM. SRAM just stores without any need to refresh the memory cells at all. DRAM needs refreshing, but its to overcome leakage. It is not to put back data destroyed during a read.

[djacobow]

That's not true of either SRAM or DRAM. SRAM just stores without any need to refresh the memory cells at all. DRAM needs refreshing, but its to overcome leakage. It is not to put back data destroyed during a read.

No, it IS true of DRAM. DRAM bits are capacitors. When a row is selected, the charge on the capacitors is sent to sense amps for reading. In the process, the charge is partially depleted. As part of the read cycle, the cell read must also refreshed. This can happen during the same row selection as the read. Essentially, the sense amp determines the state of the cells and then transistors on columns turn on to push the voltages back up in the appropriate columns.

This is independent of the bulk refresh cycle periodically applied to the whole DRAM.

Step "7" in the operation section here describes badly how this works:
http://en.wikipedia.org/wiki/Dynamic_random-access_memory

Slide 4 of this deck from some Stanford EE class also describes it:
http://www-inst.eecs.berkeley.edu/~cs150/fa04/Lecture/lec16.ppt

[SeanB]

Dram read refreshes all the cells in the selected row using the read amplifiers to refresh the level to a level that stores a bit. Thus a read is going to refresh, and connecting the read amplifier does remove charge from the cell, you just have to do it soon enough that it is reliably readable as to state. Refresh can either be on chip with an internal counter that free runs when the chip is not selected, or via an external controller that handles the refresh to keep the chip alive.

IIRC the old Z80 had a built in DRAM refresh circuit that generated memory reads when the bus was idle, and this went in a 128bit cycle to refresh the DRAM transparently.

[max_torque]

Stumbled on this magnetic core "shield" for the popular Arduino platform, and the page also has a good simple explanation of the physics behind it ;-)

http://www.corememoryshield.com/report.html

[electronics man]

Was that magnetic memory modern at the time?

[jolshefsky]

Ha—August 30, 1970 is my birthdate! What an odd thing to see appear on a YouTube video!

[DrJoe]

Was that the serial number on the silver label under the bale of the Chinese DVM - 000000106?
 (5:40 in the video). First day of production?

[iloveelectronics]

Was that the serial number on the silver label under the bale of the Chinese DVM - 000000106?
 (5:40 in the video). First day of production?

The "CMC" logo is the China Metrology Certification. I believe the number following it is just a certification number, not the serial number for the unit. I can't find any info about the CMC mark in English, only some in Chinese:
http://baike.baidu.com/view/2331156.htm
http://baike.baidu.com/view/1032852.htm

[coppice]

No, it IS true of DRAM. DRAM bits are capacitors. When a row is selected, the charge on the capacitors is sent to sense amps for reading. In the process, the charge is partially depleted. As part of the read cycle, the cell read must also refreshed. This can happen during the same row selection as the read. Essentially, the sense amp determines the state of the cells and then transistors on columns turn on to push the voltages back up in the appropriate columns.

This is independent of the bulk refresh cycle periodically applied to the whole DRAM.

Step "7" in the operation section here describes badly how this works:
http://en.wikipedia.org/wiki/Dynamic_random-access_memory

Slide 4 of this deck from some Stanford EE class also describes it:
http://www-inst.eecs.berkeley.edu/~cs150/fa04/Lecture/lec16.ppt
[/quote]

Read those two steps carefully. They agree with what I said. The cell's contents are never lost at any point in the read cycle. If the refresh step at the end of the cycle were skipped the cells would still be readable a number of times before the cell's contents were lost. This is fundamentally different from reading core stores, or something more modern like FRAM. These don't weaken the cell's state during a read, they completely destroy it. With these memories a read cycle is inherently longer than a write cycle, as a user level read operation is actually a read cycle followed by a write cycle.

[wholder]

Here's a project I did a few years back that creates a simple, one bit magnetic core memory.  I intended to scale it up, but have yet to get time to do that.  In any case, I think the circuits I worked out are fairly simple to understand in case anyone else want to dink around with core men:

  https://sites.google.com/site/wayneholder/one-bit-ferrite-core-memory

Wayne

[chickenHeadKnob]

Was that magnetic memory modern at the time?

Not really. The concept had been known for decades. Once semiconductor memory became readily available in sufficient quantities and sizes it quickly displaced magnetic core memory in all but very niche applications. The space shuttle apparently used magnetic core memory.

By 1970 the end of the line could be seen for core memory. Younger people today forget that Intel started out as semi-conductor DRAM.+SRAM core replacement company, not microprocessors. Mainframes were still being shipped with core but everyone could see semi-conductor memory was going to take over. I think that replacement market was something like 90% of intel's bottom line in the early-mid seventies.

[coppice]

By 1970 the end of the line could be seen for core memory. Younger people today forget that Intel started out as semi-conductor DRAM.+SRAM core replacement company, not microprocessors. Mainframes were still being shipped with core but everyone could see semi-conductor memory was going to take over. I think that replacement market was something like 90% of intel's bottom line in the early-mid seventies.

Intel didn't invent DRAM, but the Intel 1103 was definitely the first successful DRAM device. It kinda sucked at first, but after a few revisions is settled down to be an affordable reliable memory. At that point the core memory coffin started to creak shut.

[djacobow]

Read those two steps carefully. They agree with what I said. The cell's contents are never lost at any point in the read cycle. If the refresh step at the end of the cycle were skipped the cells would still be readable a number of times before the cell's contents were lost. This is fundamentally different from reading core stores, or something more modern like FRAM. These don't weaken the cell's state during a read, they completely destroy it. With these memories a read cycle is inherently longer than a write cycle, as a user level read operation is actually a read cycle followed by a write cycle.

I am not seeing any real disagreement here in how a DRAM read works. You seem to be making a semantic point that is  important to you, but the fact is, if DRAMs did not refresh as part of read cycle, they would not work properly and you could not build a working computer with them. That is the same as for core. Whether this happens on the 1st read of a location or the 100th doesn't really matter.

Bulk refreshes come how often? Maybe every 50-100ms? In that time, an individual memory location could be read thousands if not millions of times. If there were no refresh as part of the read, you'd soon get the wrong answer.

[FrankBuss]

And recently TI kind of re-invented magnetic core memory on a chip:

http://www.ti.com/fram

With 8 MHz it is much faster than the old core memory, and it has 10^15 write cycles lifetime, which means 4 years writing all the time with max speed. Would be an interesting project to verify this.

I wonder what other obsolete concepts could be used in a modern way. NASA's 460 GHz vacuum channel transistor looks cool, a vacuum tube on a chip:

http://hexus.net/tech/news/industry/71493-nasa-scientists-created-460ghz-vacuum-tubes/

[coppice]

Read those two steps carefully. They agree with what I said. The cell's contents are never lost at any point in the read cycle. If the refresh step at the end of the cycle were skipped the cells would still be readable a number of times before the cell's contents were lost. This is fundamentally different from reading core stores, or something more modern like FRAM. These don't weaken the cell's state during a read, they completely destroy it. With these memories a read cycle is inherently longer than a write cycle, as a user level read operation is actually a read cycle followed by a write cycle.

I am not seeing any real disagreement here in how a DRAM read works. You seem to be making a semantic point that is  important to you, but the fact is, if DRAMs did not refresh as part of read cycle, they would not work properly and you could not build a working computer with them. That is the same as for core. Whether this happens on the 1st read of a location or the 100th doesn't really matter.

Bulk refreshes come how often? Maybe every 50-100ms? In that time, an individual memory location could be read thousands if not millions of times. If there were no refresh as part of the read, you'd soon get the wrong answer.

So, you don't see a material difference between:

• a device which will store indefinitely with the power off, but can only be read by totally obliterating its contents.
• a device that leaks all day, leaks a bit worse when you try to read it, and can't store for more than 100ms or so with the power off

There are both opportunities and pitfalls in that difference. Its very relevant now, as core and FRAM behave in almost identical ways.

[djacobow]

So, you don't see a material difference between:

• a device which will store indefinitely with the power off, but can only be read by totally obliterating its contents.
• a device that leaks all day, leaks a bit worse when you try to read it, and can't store for more than 100ms or so with the power off

There are both opportunities and pitfalls in that difference. Its very relevant now, as core and FRAM behave in almost identical ways.

Of course I see a material difference. I was just reacting to Dave's being so excited by the fact the core had destructive reads and it was necessary to engineer around that, whereas for DRAM reads are also destructive and you have to engineer around that, too. The reality is that the technologies both have their quirks, admittedly, different quirks, but both  can be made to work (obviously) and there is some similarity.

Core, as you point out, retains its state when powered down, requires no power when not being read or written and is impervious to soft errors, but it requires a somewhat weird two-stage read cycle. I think core was still in use on the Space Shuttle when it was retired. It's neat stuff.

[Kadah]

I twitted this last night, but likely got missed so I'll post it here instead.

I've got a (pair actually, I plan to keep one) 16k 16bit word core memory board that I've been meaning to send in for months, but work as been too busy to package it up. The units were made by Ampex and came from the early NASA space shuttle program during the Space Lab project with ESA and would have been used in the Mitra 125 ground computers. They're unused spares and technically new old stock.

Dave, if you want it and willing to hold off making a video on core mem, I'll get the puppy shipped off in the next week.

[gflater]

Anyone know what Siemens computer that core module goes to?  Quick count looks like the word size is around 60-64bits and some parity?

Couldn't find much on the web about Siemens' mainframe offerings from the era.

Doing more research I am not sure if it belonged to a Siemens computer or not, the board is branded Siemag, the notes on the board were in german. Siemag is still active in metallurgic industries. This might have been one of their old side businesses.
I don't know what kind of computer it came from for sure. I found the board in a closet on my old job, if I recall correctly, some 20 odd years ago. The company was moving and I think this was going to get tossed together with a whole pile of old electronics.

Would be cool if Dave could hook it up to a micro controller and have it store and read back something.

[coppice]

I twitted this last night, but likely got missed so I'll post it here instead.

I've got a (pair actually, I plan to keep one) 16k 16bit word core memory board that I've been meaning to send in for months, but work as been too busy to package it up. The units were made by Ampex and came from the early NASA space shuttle program during the Space Lab project with ESA and would have been used in the Mitra 125 ground computers. They're unused spares and technically new old stock.

Dave, if you want it and willing to hold off making a video on core mem, I'll get the puppy shipped off in the next week.

https://www.dropbox.com/s/pxw7ktkok5atoqc/IMG_20140326_170124.jpg

Are the brown strips on that board a mezzanine power bus? I haven't seen one of those in quite a few years.

[rrmm]

[Doing more research I am not sure if it belonged to a Siemens computer or not, the board is branded Siemag, the notes on the board were in german. Siemag is still active in metallurgic industries. This might have been one of their old side businesses.
I don't know what kind of computer it came from for sure. I found the board in a closet on my old job, if I recall correctly, some 20 odd years ago. The company was moving and I think this was going to get tossed together with a whole pile of old electronics.

The only other reference to it I could find was this: http://www.ebay.ca/itm/Vintage-Core-Memory-Cartridge-70s-SIEMAG-Collectible-/121276238805

The storage doesn't seem very big nor the cores very dense (given the vintage).  Perhaps it's from an industrial PLC of some sort. 

Interesting find in anycase!

EDIT: looks like it might be from a Philips computer maybe P1000?

[AReResearch]

On the wifi radio:
Looks like the 11th and 21st traces of the ribbon cable have broken again after the repair.
The hole in the 12th had already been noticed.

Either someone has mistreated the unit or there is a serious mechanical design flaw.
Shouldn't be too hard to fix.

[BlinkY]

If it's possible to read and write to the fascinating Magnetic Core Memory module, I'm suggesting "EEVblog" and then frame the whole module for the future.
I'm assuming it will fit? 8 bytes for each letter, 8 x 7 = 56 bits.