EEVblog #683 - Rigol DS1000Z & DS2000 Oscilloscope Jitter Problems

[Bud]

not sure if there's a mention of it in the PLL datasheet, but there power delivered by the output diff pair could depend on the vco core power, too, provided the emitter current source is configured for 11mA.
The bottom line is that this clock source shall remain in the PLL purgatory, neither dead, nor alive, in a kinderscope coffin.

If that is the case, that is another evidence that they have no idea what they are doing. Cranking up the output power at the expense of PLL not locking anymore is stupid.

[Bud]

The owner was anxious to start using his scope, so it's back together now.  I couldn't think of anything further that should be done.

I still have my PLL board available to try as the replacement for the moronic 1054Z ADC clock , but since you are not the scope owner I guess this is not happening. Thank you very much for the testing you have done.   

[phenol]

ok, so it's bad, but consistently so.
 

[orin]

The owner was anxious to start using his scope, so it's back together now.  I couldn't think of anything further that should be done.

I still have my PLL board available to try as the replacement for the moronic 1054Z ADC clock , but since you are not the scope owner I guess this is not happening. Thank you very much for the testing you have done.   

I'd be interested to know what happens if you programmed your PLL board with the VCO core power and output power settings that Rigol are using...

[MarkL]

not sure if there's a mention of it in the PLL datasheet, but there power delivered by the output diff pair could depend on the vco core power, too, provided the emitter current source is configured for 11mA.
The bottom line is that this clock source shall remain in the PLL purgatory, neither dead, nor alive, in a kinderscope coffin.

That's an interesting point on the core power.

I hadn't noticed before you said so, but the PLL output dropped from 1.60Vpp (+8.09dBm) in the beta (measured on a different DS1054Z) to 0.85Vpp (+2.58dBm) in the new release.  This is below the minimum required by the ADC of 1.5Vpp.  It could be something wrong with this specific DS1054Z, but that seems less likely than being related to the core power change.

Perhaps this is why Rigol is reluctant to lower the core power any further.  The ADC could stop working.


Side note:

Don't go by the before/after amplitude values on the screen shots in my post #995.  I had someone else doing the probing and looking now I think they had one side of the diff probe lifted.  The spectrum envelope, however, is correct.  My bad for not supervising this more carefully.  The later shots in #1025 are correct in amplitude.

Damn Rigol for not being able to go back in firmware revs.  I'd want to re-measure some of those values if I could.

[Bud]

Yes, it could also be possible to try locking the PLL by paralleling a additional capacitor across one of the loop filter components as i suggested earlier.

[edavid]

I'm having a lot of trouble understanding how the PLL can function if it's not locked.  Why is the output frequency even close to correct?

Also, why are the loop filter component values important?  With a fixed input, I would think only a tiny lock range would be needed, and almost any loop filter would do.  Is it the VCO band switching that causes problems?

[MarkL]

The owner was anxious to start using his scope, so it's back together now.  I couldn't think of anything further that should be done.

I still have my PLL board available to try as the replacement for the moronic 1054Z ADC clock , but since you are not the scope owner I guess this is not happening. Thank you very much for the testing you have done.   

If not already apparent, I've enjoyed this investigation and I would try your board in an instant, but the opportunity isn't presenting itself this time.

I thought the idea to try Rigol's parameters and loop filter on your board sounded like an interesting experiment.  I would do it if you wanted to send me the board, but unfortunately I'm in the same position as you without a DS1054Z patient.

[tggzzz]

I'm having a lot of trouble understanding how the PLL can function if it's not locked.  Why is the output frequency even close to correct?

To oversimplify, the oscillator in the loop will be a voltage controlled oscillator. When locked that voltage will be (almost) constant. When not locked that control voltage is varying so the frequency is varying.

It is questionable whether a simple RC oscillator would be more or less stable (and useful) than the VCO in an unlocked PLL.

[Bud]

@edavid

Pick up any book on PLL design and you will see it is quite a complicated area. Look at the formulas for loop filter calculation and that will give you an idea on relationships between design parameters. You will probably get tired fairly soon trying to wrap your head around it. I do not think anyone here, since this is a consumer thread, can explain in layman terms. I also do not think that many circuit designers would go into the trouble of learning the theory of integrated PLLs in depth. For them there are reference designs and simulators available. Do-it-yourself may instead of using the part manufacturer simulation tool can put you in trouble, which is what we are witnessing here with this Rigol case. Imagine someone trying to pen and paper Maxwel'sl equations instead of using a EM simulator.

PLL stands for Phase Locked Loop, when the VCO via a divider counter and phase frequency detector become phase alligned with an external reference. The PFD will produce pulses of opposite polarity depending on the phase difference and drive the VCO via the loop filter. There are relationship between the parts that make the control loop and VCO and if not properly done, locked condition may not be achieved and PFD will continue trying hard to pulsing positive and negative and that creates spurs and noise.

The bottom line is the 4360-7 chip in Rigol 1054z cannot achieve lock condition as MarkL has confirmed measuring the digital lock detect pin level and that produces the crap in the output, whatever the internal IC processes might be. When it is locked , the output looks as in my screenshots i posted several times and what is given in the Datasheet. Period.

[Bud]

I thought the idea to try Rigol's parameters and loop filter on your board sounded like an interesting experiment.

I may do it when have time. This involves changing 0603 size components in a tight space, since the board layout was not meant for experimenting, i usually get things working from the first try with proper preparation. The pll IC is programmed using an on-board PIC which is also soldered, so i need a fair amount of spare time to do a swap. Will see.

[EEVblog]

The pll IC is programmed using an on-board PIC which is also soldered, so i need a fair amount of spare time to do a swap. Will see.

There is a PIC processor on the 1054Z?

[MarkL]

The pll IC is programmed using an on-board PIC which is also soldered, so i need a fair amount of spare time to do a swap. Will see.

There is a PIC processor on the 1054Z?

No, we're talking about Bud's standalone ADF4360-7 PLL board.

[Bud]

By the way, Dave, your Blog #702, Keysight 3000T,  at 6:50 , ADF4360-7 PLL in it, would be good to check the spectrum how Keysight got it. I guess may be next time you disassemble it.

[tautech]

By the way, Dave, your Blog #702, Keysight 3000T,  at 6:50 , ADF4360-7 PLL in it, would be good to check the spectrum how Keysight got it. I guess may be next time you disassemble it.

+1 

[nuno]

The clock on my 1104Z-S is not "bad" and I need the big measurements' font on the new firmware, but god knows what will happen to the clock with the new firmware, and no going back... oh boy oh boy, what should I do... who doesn't hate not being in control...

Probing a 16mHz crystal on an AVR


25MHz sine from the internal fgen

[MarkL]

By the way, Dave, your Blog #702, Keysight 3000T,  at 6:50 , ADF4360-7 PLL in it, would be good to check the spectrum how Keysight got it. I guess may be next time you disassemble it.

If you'll take an Agilent/Keysight MSOX 3000A also with a ADF4360-7, here it is.

What's your ADF4360-7 board look like close in?

[Bud]

Do you mean close in of the spectrum or picture of the board ?
My spectrum analyzer only has 1kHz minimum RBW, so i cannot resolve that nicely as in your last pic, but i should have a screenshot of  a 20kHz/ and there was no spurs.
If you engage  input attenuator, do the spurs in the last pic change in right proportion?

Also can you check what is on the muxout pin?

[Bud]

MarkL,

The 1MHz span spectrum on your Agilent looks very similar to what my PLL puts out, I have attached a side by side pic, and also blended the two images together, it can be seen they are practically the same.

Also did a close in over 50kHz span, yours was over 30kHz, fairly close span. I used the minimum 1kHz RBW available on my SA. Your Agilent has a better roll off, mine has better (no) spurs close to the carrier. I must say I used a good TCXO oscillator with a low phase noise, I do not count beans when it comes to performance.

[phenol]

The close-in spurs could be a result of noisy Avdd rail or ground bounce. If they are non linear mixer overload products, their level should drop faster than that of the main tone when the frontend step atten is bumped up a step.

[orin]

The close-in spurs could be a result of noisy Avdd rail or ground bounce. If they are non linear mixer overload products, their level should drop faster than that of the main tone when the frontend step atten is bumped up a step.

With input attenuation of 10dB and reference level of -14 dBm for MarkL's plot, I believe what I see.

[aargee]

So all us poor "consumers" with the DS1054z (I'm not speaking about you other Rigol users further up the food chain, you'll have to see if your bang per buck fits here) will have to put up with the notion that behind that 4 Channel panel with all those goodies for US$399, the PLL is not locked and producing spurs and a noise floor in the signal I can't quite see operational evidence of when using the DSO.

It appears we have a PLL IC running as an 'unlocked' oscillator, still trying to push to lock but not quite making it because of poor design choices. Fair enough, Rigol could have put a nice sharp oscillator running off an RC circuit or quartz encrusted cellulose to do the job because that's all it needs to produce the specs the DSO does. Would that be the answer? (No, huh?)

For some reason this is starting to sound like an audiophile thread. If I hear a rattle I'll know the PLL has overheated, jumped off the board and is trying to escape and I'll have to buy a Siglent.     

I'm still waiting to see if there are any issues I should be concerned about with my little 1054. Stand me to be corrected!! 

[orin]

If so they had confused VCO Core Power with Output power, which is a separate setting. Told that 500 times before but let me repeat again - they have no idea what they are doing. But general public in this thread , which should be called consumer blog , not engineering one, seems to feel ok with it. So best of luck to everyone using their "shelf decoration".

not sure if there's a mention of it in the PLL datasheet, but there power delivered by the output diff pair could depend on the vco core power, too, provided the emitter current source is configured for 11mA.
The bottom line is that this clock source shall remain in the PLL purgatory, neither dead, nor alive, in a kinderscope coffin.

On reviewing the data sheet some more, I find it unlikely that the core power would affect the output power.  The VCO core output goes to the output stage, a divide by 2 stage and a multiplexer.  The output stage gets its input either from the VCO core or the divide by 2 stage.  I would expect that the VCO output, divide by 2 input, multiplexer input and output stage inputs are digital and that the output power is only affected by the programmed output power.

[orin]

By the way, Dave, your Blog #702, Keysight 3000T,  at 6:50 , ADF4360-7 PLL in it, would be good to check the spectrum how Keysight got it. I guess may be next time you disassemble it.

If you'll take an Agilent/Keysight MSOX 3000A also with a ADF4360-7, here it is.

What's your ADF4360-7 board look like close in?

I forgot to ask... "And Agilent's loop filter component values are?..."

[Howardlong]

Just been through my junk, and I do have an eval board for this part, I may be mistaken ISTR reading somewhere that the loop filter parts were known but can't find the reference now, if so I'd be happy to set up the board with those parts, and squirt in the appropriate register values.

Edit: found it https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/555/

Also registers settings before/beta/release are here

https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg560788/#msg560788

and here

https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg583676/#msg583676