EEVblog #683 - Rigol DS1000Z & DS2000 Oscilloscope Jitter Problems

[jeroent]

I got my DS1054Z this month. The board version changed from 0.2.3 to 0.1.1 after the firmware update. Isn't this weird?

[tggzzz]

I'm still waiting to see if there are any issues I should be concerned about with my little 1054. Stand me to be corrected!! 

I thinnk we've all got the message that you and your applications won't notice the suboptimal design. Good; I'm happy for you.

But please don't assume that other people don't have different applications and can't afford to be so tolerant or measurement errors.

[H.O]

Hi,

I thinnk we've all got the message that you and your applications won't notice the suboptimal design.

Out of curiosity, with the latest firmware, has anyone been able to come with an application and measurment WITH the scope that actually shows the scope NOT living up to its published specifications due to this suboptimal design?

[DanielS]

Out of curiosity, with the latest firmware, has anyone been able to come with an application and measurment WITH the scope that actually shows the scope NOT living up to its published specifications due to this suboptimal design?

I think the main complaint about the "suboptimal design" is that people are weary of implicitly trusting a PLL that fails to lock.

Most people want to use their instruments without worrying about them suddenly deciding to go considerably out of calibration. Without a PLL lock to confirm that the PLL is operating at its intended frequency, you never know for certain short of hooking up a spectrum analyzer to the PLL or feeding a known waveform through the scope and checking the FFT for drift/jitter-induced spurs.

[phenol]

There u go:
"Done the upgrade to my hacked DS2072A (ie 2302A :0) )  FW now reads 03.03.sp1 HW 2.0
AC trigger issue fixed.
5uS Jitter issue not fixed :0( , better , but not fixed."

This comes from user Neddie in the 'Rigol DS1054Z Oscilloscope Jitter Fix Testing ' thread.

[leppie]

There u go:
"Done the upgrade to my hacked DS2072A (ie 2302A :0) )  FW now reads 03.03.sp1 HW 2.0
AC trigger issue fixed.
5uS Jitter issue not fixed :0( , better , but not fixed."

This comes from user Neddie in the 'Rigol DS1054Z Oscilloscope Jitter Fix Testing ' thread.

That's just nonsensical... 

[Neddie]

Sorry , my bad. Jumped the gun a little there.
No 5uS jitter , just a crap sig gen 
Thanks Teneyes for making me check again !!!
Neddie

[MarkL]

If so they had confused VCO Core Power with Output power, which is a separate setting. Told that 500 times before but let me repeat again - they have no idea what they are doing. But general public in this thread , which should be called consumer blog , not engineering one, seems to feel ok with it. So best of luck to everyone using their "shelf decoration".

not sure if there's a mention of it in the PLL datasheet, but there power delivered by the output diff pair could depend on the vco core power, too, provided the emitter current source is configured for 11mA.
The bottom line is that this clock source shall remain in the PLL purgatory, neither dead, nor alive, in a kinderscope coffin.

On reviewing the data sheet some more, I find it unlikely that the core power would affect the output power.  The VCO core output goes to the output stage, a divide by 2 stage and a multiplexer.  The output stage gets its input either from the VCO core or the divide by 2 stage.  I would expect that the VCO output, divide by 2 input, multiplexer input and output stage inputs are digital and that the output power is only affected by the programmed output power.

Ok, well it still remains that the latest DS1054Z I had under test here had an output too low (0.85Vpp) for the ADC clock input (min 1.5Vpp).  But it was still working.  Maybe just barely.

[MarkL]

The close-in spurs could be a result of noisy Avdd rail or ground bounce. If they are non linear mixer overload products, their level should drop faster than that of the main tone when the frontend step atten is bumped up a step.

With input attenuation of 10dB and reference level of -14 dBm for MarkL's plot, I believe what I see.

Several decades of additional attenuation does not change the spectrum.  Trying a passive probe doesn't change it.  A different spectrum analyzer (but with less RBW capability) doesn't change it.

I'm convinced it really looks like that.  FWIW, the two highest spurs move outward from the main carrier as the unit warms up.  The secondary spurs at around 9kHz don't seem to move.

The MUXOUT pin is high, but we don't know how it's programmed.  There's a via on it, so it goes somewhere.  Maybe Agilent is watching for LOCK status.

And I don't know the loop component values.

But I'm game to dig into all this and find out the component values and decode the SPI bus.  I'll try to get to it in the next couple of days.  Then we can compare implementation to the Rigol.

[Howardlong]

Today, I did some experiments with an ADF4360 evaluation board. The board I have (for the ADF4360-9) was from some time ago, so I spent some time firstly checking it worked as is, then converting it to an ADF4360-7 board.

In short, with the parts believed to make up the DS1000Z loop filter, and with the new firmware, the eval board locks solidly. With the old firmware, it does _not_ lock.

Unfortunately this probably brings up more questions than it answers, in that the loop filter parts on the eval board seem to work.


New firmware on Eval board with DS1000Z loop filter parts


Old firmware on Eval board with DS1000Z loop filter parts


Eval board setup


Eval board "lock" LED

Detail of tests

The ADF4360-9 eval board was populated with parts as per the ADF4360-7 eval board BOM/schematics. It was tested at the default 900MHz offered by the ADF4360 software package, and all seemed to work reasonably well. When trying to use the board above about 983MHz, the device unlocked. I adjusted the inductors L1 and L2 as per the datasheet calculation "Choosing the Correct Inductance Value" to 3.3nH (were 3.9nH). The board then worked fine at 1GHz with the software's default settings. Please see attached PDF for the mods made to the eval board, in a semi DaveCAD style.

The software settings were then adjusted to match the newly released firmware register settings.

o Test 1: Default eval board parts, new firmware


New firmware ADF4360-7 register settings


Eval board with default parts (except L1 and L2, see text) and new firmware register settings (10MHz span)

The board's LED was showing "locked" and on a scope the MUXOUT pin was steady high indicating the device is locked according to the digital lock. As the results were promising, the same test was performed with the original firmware register settings.

o Test 2: Default eval board parts, old firmware


Old firmware ADF4360-7 register settings


Eval board with default parts (except L1 and L2, see text) and old firmware regsiter settings (10MHz span)


Eval board with default parts (except L1 and L2, see text) and old firmware regsiter settings (2MHz span)

On this occasion, the lock LED was off indicating there was no lock.

The next tests are duplicating those above but with the default eval board loop filter parts replaced with those believed to be on the DS1000Z.

o Test 3: DS1000Z loop filter parts on eval board, new firmware


Eval board with DS1000Z loop filter parts, and L1 & L2 set as in text, new firmware settings (10MHz span)


Eval board with DS1000Z loop filter parts, and L1 & L2 set as in text, new firmware settings (2MHz span)


This one's for Bud ;-)

With the new firmware and the DS1000Z loop filter parts (and keeping L1+L2 3.3nH) the lock LED came on, and was showing solid on the scope.

o Test 4: DS1000Z loop filter parts on eval board, old firmware


Eval board with DS1000Z loop filter parts, and L1 & L2 set as in text, old firmware settings (10MHz span)


Eval board with DS1000Z loop filter parts, and L1 & L2 set as in text, old firmware settings (2MHz span)


Specially made Bud version ;-)

Part modifications from the default ADF4360-7 eval board schematic/BOM

o L1 & L2 reduced from 3.9nH to 3.3nH as per data sheet for VCO operation at 1GHz.
o Loop filter (Eval board default / DS1000Z)
- R10 8.2k / 909R
- R11 4.3k / 3.65k
- C13 560p / 5.5n
- C14 8.2n / 24n
- C15 270p / 750p

Conclusion

The loop filter parts, as they are understood to be, lock on the eval board. Why they would not lock on the scope itself remains a mystery. It is interesting to note that the old firmware does not present LOCK on the MuXOUT pin. The new firmware does however. The spurs are marginally worse with the DS1000Z filter loop parts. I should note that if L1 and L2 are not right, indications are that the VCO simply goes off into la la land, it's not just a little bit of FMing. Perhaps it's a layout, power or decoupling issue that's modulating the carrier. Sorry I couldn't give a more concrete result, however if those of you brave enough would like to check pin 20 on the ADF4360-7 on their scope, if it is locked it'll be sitting pretty at 3.3V. Note that that won't tell you anything on the old firmware as the lock signal didn't come out on the MUXOUT pin.

[orin]

Howard,

Very nice!

Which spectrum analyzer were you using?  It certainly seems to be doing the job well.

I wonder if something is coupled in through L1 and L2.  They are supposed to be at right angles to each other, but seem to be parallel in the Rigol scopes.

Now I noticed that ADIsimPLL allows you to use a -7 part to generate 2GHz internally and divide down by 2 (either internally or externally) for an output of 1GHz.  Unfortunately, it requires 112 pH (yes pico-Henry) inductors.  I wonder if this could be achieved on the eval board; there is probably too much inductance if the L1 and L2 positions were shorted.  Might shed some light on Rigol using a -7 for 2GHz in the 2000 series scopes.

Orin.

[Howardlong]

I used three spec ans, sometimes you need to question whether what you're seeing is real or is instrument generated, like phase noise for example. As I'm new to the DSA815, I checked it against an Anritsu MT8802A and the old boat anchor HP 8565A, which despite its age still works if you're kind to it. So mostly I used the DSA815 but had the Anritsu double checking the results.

As noted in the conclusion, it seems that if L1 and L2 are a bit wrong value-wise, you won't just get a bit of FMing, it'll be miles off, if it oscillates at all. YMMV, of course, this is just the behaviour I noted. But they do need to be right or it just won't work: the VCO will only pull 20% and these parts determine the VCO's base frequency. When you're talking single digit nH, layout does of course make a difference, although by how much, especially regarding parallel as opposed to orthoganol or linear placement and associated coupling  I don't know.

What seemed strange to me in earlier tests by MarkL was that the jitter viewed on the latest firmware didn't seem to be temperature dependent, which is really what peaked my interest, and to wonder if this really is a loop filter thing or something else.

[pickle9000]

Sounds like some actual component values need to verified around the pll (out of spec / vendor change and so on). Not saying that's the issue but just one of those things that happens during production.   

[phenol]

the spurs in your setup when the pll is unlocked look predictable and are multiples of the pfd freq. The rigol close-in spectrum seems polluted with some sort of noise, which could be uncorrelated to the inner workings of the pll chip itself
what is the dc voltage after the loop filter in post-update rigols?

[Howardlong]

Complete conjecture, but I was also wondering about what difference a multilayer vs wirewound inductor makes on these devices: I used WW throughout, but it's just the kinf of thing that gets "rescoped" in production by well-meaning but misguided souls in an effort to swueeze the last few pennies out of the BOM.

[MarkL]

Complete conjecture, but I was also wondering about what difference a multilayer vs wirewound inductor makes on these devices: I used WW throughout, but it's just the kinf of thing that gets "rescoped" in production by well-meaning but misguided souls in an effort to swueeze the last few pennies out of the BOM.

Wow, awesome bit of testing Howard!

The DS1054Z uses wire-wound inductors for L1 and L2.  You can see them here in Dave's teardown photos:

  https://www.flickr.com/photos/eevblog/15540979722/in/set-72157646442125864

I can confirm they were also wire-wound on the two units I took apart.

The component values for the loop filter that I posted may have inaccuracies since I didn't pop them off the board to measure them.  The resistors are probably right on, but the caps were measured using an LCR meter's "C in parallel with R" mode and shorting out various components to get the equivalent of a single resistor in parallel with the target cap.  It should be pretty close but there's bound to be some error in that.

[MarkL]

For those who can't get enough of ADF4360-7, here's what Agilent has implemented in the MSOX3104A.

Register values:

  30 00 09  (R Latch)
  2f f1 20  (Control)
  00 0f 16  (N Latch, B & A)

The registers select Digital Lock Detect (Active High) on MUXOUT, and as noted previously, it's high.  (Why am I not surprised.)

It's only operating at 625MHz, so it must be feeding a further PLL inside the MegaZoom chipset to get the 5GHz sampling rate.

Below are the loop component values, determined in the same way as I just posted for the Rigol.

Here's Dave's teardown of the X3000A if you want to look at the layout around the PLL, but there's nothing really exciting there:

  https://www.flickr.com/photos/eevblog/sets/72157626755861230/

The X3000T uses the same PLL, but with a different reference oscillator (likely also 10MHz, but that's just a guess).

EDIT: I bumped a probe while removing it and got the error below.  They *are* watching the PLL status!

[Bud]

MarkL, brilliant on the PLL monitoring in Agilent scope! That is the right design, isnt it what i said before, PLLs have to be monitored! Kudos to Agilent, though i am certain they always did that.
I will review your Agilent programming data tonight, thanks a bunch!

Howardlong, truly appreciate that you jumped in, nicely done and documented test case!

You my fellow other readers, make sure you do not miss this nice opportunity to learn about PLLs and proper design, this may save you time in future. Glad that some already picked up a book or datasheet and learned a few things as a result of the contents of this discussion. Hopefully this thread can return to engineering vs consumer mood.

[EEVblog]

EDIT: I bumped a probe while removing it and got the error below.  They *are* watching the PLL status!

That's impressive attention to detail! 

[orin]

Here's Dave's teardown of the X3000A if you want to look at the layout around the PLL, but there's nothing really exciting there:

  https://www.flickr.com/photos/eevblog/sets/72157626755861230/

Actually, it is quite interesting in that there appears to be significant filtering for the V_vco power supply and slightly less for the AV_DD and DV_DD supplies.  I'm assuming the black SMD components are ferrite beads or inductors.

The 51.1 ohm output pullups to V_vco are also separately decoupled in the Agilent design.  Rigol are using a shunt inductor to V_vco instead, so probably no big deal.

[DanielS]

Finally got a confirmation from Allied that my DS1054Z should be arriving at my doorstep by the end of the week... and hours later, one of my clients who had been "promising" to send me a scope for nearly a year also called to confirm my shipping address to send their scope, which I suspect is going to also be a DS1054Z. So I may have two DS1054Z to play/work with in the near-future.

We'll see what sort of pre-update and post-update jitter I will get out of 'em.

[MarkL]

Howard,

Can we see what the CP pin looks like with the Rigol loop filter values / old firmware combo?

Although unlocked, your eval doesn't have the serious FM happening that we've seen on some of the old firmware and beta units.  With the first sideband at -36dB, I'm getting a deviation of 3.1kHz, which translates to a displayed jitter of 20ps pk-pk @5us delay.

The first DS1054Z I looked at had a 50mVpp 100kHz sawtooth happening on the CP pin with the old firmware.  You obviously have the 100kHz modulation; I'm just wondering if examining the CP behavior will provide any clues.  (But your deviation may be too small to see on CP or Vtune).

[phenol]

the dc value of Vtune is of no lesser importance-it should not drop too low and start actually drawing from and pumping current into the varicap pair which actually rectifies the ac voltage present there and creates a dc offset in the midpoint. This could explain the lower bound of the vco tuning voltage/1.25v/.
When tuning down towards this voltage, the Fpfd spurs increase until it's out of lock...at least that's what was happening  with an ADF4106 and a 400MHz vco built with discretes and fairly beefy airwound silver inductors for low phase noise

[Bud]

The loop filter parts, as they are understood to be, lock on the eval board. Why they would not lock on the scope itself remains a mystery

A closer look actually reveals it is actually not that hunky dory. I happened to find a 200kHz span screenshot of my PLL and it can be seen that with Rigol's components on your eval board (left in the below picture) and their new firmware, the PLL noise is quite high - the pedestal is 20dB worse than mine (right) and in fact is at the same level as MarkL measured on his Rigol test scope (middle insert in the attached picture). Yours is definitely better then MarkL's but is a far cry from what it should be. I guess you were lucky to had the PLL locked, possibly because your eval board is of a better quality RF wise, most likely it is a 4-layer board with proper solid ground plane and power plane and better bypassing.

I also posted before that with Rigol components the loop filter's phase margin is just 36 degrees which is below the recommended base line of 45-50 degrees and implies potential instability. Therefore it may not be much surprising that the PLL locks on your eval board and did not on Rigol scope.

[Bud]

For those who can't get enough of ADF4360-7, here's what Agilent has implemented in the MSOX3104A.

Register values:

  30 00 09  (R Latch)
  2f f1 20  (Control)
  00 0f 16  (N Latch, B & A)

OK decoded the values and plugged into the simulator the component values you measured. Guess what, no surprises, all seems to be by the book.

'======================Agilent ===== Rigol ========
Phase margin, degrees:    60           36
Loop bandwidth,kHz:       28.5         6.6
CP current, mA            2.5          0.13
VCO Core Power level,mA   5            15
PFD frequency, MHz:       5            2.5
   
Phase Margin, Charge Pump Current, VCO Core Power all make sense in Agilent's setup and do not in Rigol's setup.
Based on the PLL divider values Agilent seems to be using a 10MHz reference and the highest PFD frequency for the part to minimize noise associated with dividing the output frequency.