EEVblog #683 - Rigol DS1000Z & DS2000 Oscilloscope Jitter Problems

[Bud]

These inputs are being generated by an ADF4360-7 frequency synthesizer, which has as its base clock a 25MHz crystal/resonator/oscillator block (not sure exactly, marked "CETDCJ 25.000").

Is it CETECJ by any chance? Seems there is a manufacturer with this name, possibly in China. There seems nothing special in their oscillators, seems to be a cheap commodity product, so the PLL ripple is not caused by modation of the reference clock. Then if modulation is intentional, it could only be caused by reprogramming the PLL. Can you check for SPI activity on the PLL ? No need for decoding, just to see if the chip is getting written within that 100kHz cycle. Which i still doubt, since the PLL datasheet specifies frequency lock time is 400uS.

EDIT: may also check the power supply pins on the PLL for that modulation pattern

[MarkL]

These inputs are being generated by an ADF4360-7 frequency synthesizer, which has as its base clock a 25MHz crystal/resonator/oscillator block (not sure exactly, marked "CETDCJ 25.000").

Is it CETECJ by any chance? Seems there is a manufacturer with this name, possibly in China. There seems nothing special in their oscillators, seems to be a cheap commodity product, so the PLL ripple is not caused by modation of the reference clock. Then if modulation is intentional, it could only be caused by reprogramming the PLL. Can you check for SPI activity on the PLL ? No need for decoding, just to see if the chip is getting written within that 100kHz cycle. Which i still doubt, since the PLL datasheet specifies frequency lock time is 400uS.

EDIT: may also check the power supply pins on the PLL for that modulation pattern

Just double-checked - it is "CETDCJ".

I thought that too about it being reprogrammed.  All the SPI-related inputs are quiescent.  I can't find any indication of external 100kHz influences.

I've also been around to all the power supply pins looking for 100kHz with a scope.  I'll have a look with the SA if the chip is overly sensitive to that.

[bitbanger]

^ I was about to post last night because it hasn't been mentioned, but my 1074Z is (as you would assume) affected similarly.

[Nonorthogonal]

I thought that too about it being reprogrammed.  All the SPI-related inputs are quiescent.  I can't find any indication of external 100kHz influences.

I've also been around to all the power supply pins looking for 100kHz with a scope.  I'll have a look with the SA if the chip is overly sensitive to that.

This makes me hope that it's an FPGA problem and not in the PLL. I won't RMA this until we know, but it's probably the ADF4360-7 based on the variations people are seeing.

A sufficiently clever FPGA guru could calibrate this one out in a few hours.  How many gates are left in that Xilinx??

[MarkL]

EDIT: may also check the power supply pins on the PLL for that modulation pattern

...
I've also been around to all the power supply pins looking for 100kHz with a scope.  I'll have a look with the SA if the chip is overly sensitive to that.

Ok, according to the SA, all PSP pins are <6mVpp for both 1GHz and 100kHz, except the internal compensation node, Cc.

Cc has a stronger 1GHz component of ~63mVpp.  Since that's an internal node there's not much documentation for it so that might be normal.  There's a decoupling cap on it to ground and the spec says it should be 10nF.  I'm measuring it as 1nF, but that's in-circuit so my reading might be off (but likely not that much).  Squeezing a 100nF next to it with a tweezers (I didn't have a 0402 10nF) doesn't affect anything anyway.

I don't think there's much more I'm going to do with it at this point until we hear from Rigol.  To be fair to them and let them support customers their way, I've also opened up a case through their web site and I've referenced this thread.  If I get anything towards a resolution that didn't also make it here, I'll post back.

I'm just pursuing the 5us jitter problem in the case.

[Bud]

Thank you MarkL for the efforts. So to summarize we think the ADC clock source ADF4360-7 PLL does not operate as it should , i.e it is unable to phase lock to its 25MHz external reference. Possibly may be caused by deficiencies in the PLL loop design or PLL registers programming.

[MarkL]

Thank you MarkL for the efforts. So to summarize we think the ADC clock source ADF4360-7 PLL does not operate as it should , i.e it is unable to phase lock to its 25MHz external reference. Possibly may be caused by deficiencies in the PLL loop design or PLL registers programming.

Yep - I think that sums it up accurately.  And thanks for your help.  It was nice finding someone who's actually worked with this chip.

And that LTC6946 is very impressive! Guess where I'm going to look first for my next PLL design...

[dr.diesel]

Wonder if that same chip is used in the 4000s?

[Nonorthogonal]

Here are Dave's DS2000Z & DS1000Z teardown images of the AD PLL. Looks like there are lots more caps on the DS2000Z...

I like to think that Dave's criticism of Rigol lasering the chips made them stop... which said to us "we took the time away from testing the vendor's PPL filter to just laser off the label".

I'm blown away by the quality and price point of this scope. If only they'd fix this they'd corner the market on cheap oscilloscopes.

[Bud]

Thanks for the pics. Lasering the pll chip was totally unnecessary, anyone who used ADF4360 before would instantly recognize it

 

[jmc2000]

Thanks for the pics. Lasering the pll chip was totally unnecessary, anyone who used ADF4360 before would instantly recognize it

 

Is it possible that the PLL chip is being stretched beyond its spec which is why it was lasered, just like the ADCs in the early Rigols?

[Bud]

Hopefully it was not because they used knock-off chips
 

In the meanwhile, if someone who has a DS1000/2000 series scope that does NOT have 5uS jitter could check the ADF4360 PLL output with a spectrum analyzer (1 or2 GHz) , or just use any low frequency scope to check PLL pin 7 (loop filter ) and compare with what MarkL posted on page 19 and 20 of this thread, that would be great.

If Dave still reads this thread and could do a quick check that would be nice

EDIT: not pin 7, pin 24

[EEVblog]

My test setup was using a Hp 3325 function generator at close to 20 Mhz.  Roughly 5 volts input using x1 (bnc cable) in X1 mode on scope.  Has anyone noticed what happens when you raise the memory depth from the lower values towards 56M points.  ?

Yes, that is normal, because at the bigger memory depths you get a much less wfps update speed.

[David Hess]

Is it possible that the PLL chip is being stretched beyond its spec which is why it was lasered, just like the ADCs in the early Rigols?

I did not see anything in the specifications which would limit its use in this sort of application.  The phase noise when it is operating correctly is not limiting the performance of the DSO.

[Nonorthogonal]

If I'm reading the Rigol manual correctly here's how out-of-spec the jitter is. My scope is essentially useless out +/- 1 us.

[XFDDesign]

Here are Dave's DS2000Z & DS1000Z teardown images of the AD PLL. Looks like there are lots more caps on the DS2000Z...

I like to think that Dave's criticism of Rigol lasering the chips made them stop... which said to us "we took the time away from testing the vendor's PPL filter to just laser off the label".

I'm blown away by the quality and price point of this scope. If only they'd fix this they'd corner the market on cheap oscilloscopes.

For what it's worth, they're missing the required 470ohm resistors in parallel with the tuning inductors in the picture.

That being said, what's the basis for determining this to be a PLL issue? Is the CP output showing something erratic which correlates to this jitter issue?

[David Hess]

If I'm reading the Rigol manual correctly here's how out-of-spec the jitter is. My scope is essentially useless out +/- 1 us.

Timebase accuracy is not the same as jitter.  I was not able to find any sort of jitter specification in the user manual but it should be insignificant out to at least 500us.

[pickle9000]

I would be absolutely shocked if they truly can't reproduce the issue.  They are either still investigating, or unwilling to admit to duplication in fear of being forced to accept responsibility.

I'd say they want to have an answer (a no BS one) and solution at the same time. Coming in with both will help the sell product. I can't really blame them, confidence is a big word in the industry.

[Bud]

For what it's worth, they're missing the required 470ohm resistors in parallel with the tuning inductors in the picture.

That being said, what's the basis for determining this to be a PLL issue? Is the CP output showing something erratic which correlates to this jitter issue?

Per the Datasheet the 470 Ohm resistors required if the inductors are 3.3uH and above. For 1GHz clock the inductors would be smaller than that - see the inductors selection chart in the Datasheet.

The basis for determining the PLL is a suspect is it outputs wideband garbage instead of a single clock frequency into the downstream ADC - see page 19 of this thread. Also the CP pin shows 100kHz ripple which is 10uS period and that correlates to the 10uS jitter cycle in the chart Nonorthogonal posted  above.

[ulix]

Hi everybody,

what I know is: Rigol does know the problem and they found it! There will statement/ update in the near future!
Please keep calm, they are doing their best 
cheers

[XFDDesign]

Per the Datasheet the 470 Ohm resistors required if the inductors are 3.3uH and above. For 1GHz clock the inductors would be smaller than that - see the inductors selection chart in the Datasheet.

The basis for determining the PLL is a suspect is it outputs wideband garbage instead of a single clock frequency into the downstream ADC - see page 19 of this thread. Also the CP pin shows 100kHz ripple which is 10uS period and that correlates to the 10uS jitter cycle in the chart Nonorthogonal posted  above.

Fair enough on the <=3.3nH inductors. The trim I've used has always been larger values.

So, it seems the sample clock *is* spread.  Maybe not on purpose?   It's difficult to unwind if you're trying to get a decent FFT out of the thing.

Below are a couple shots from an SA looking at the ADC (HMCAD1511) CLKP and CLKN inputs with a differential probe.  These inputs are being generated by an ADF4360-7 frequency synthesizer, which has as its base clock a 25MHz crystal/resonator/oscillator block (not sure exactly, marked "CETDCJ 25.000").

I'm noting that the synthesizer output has discrete jumps of 100kHz.  Now where have we seen that number before??

The 5us jitter is pretty bad on this unit.

Still trying to glue all the observations together, but thought I'd post since it's interesting.

(Pardon the screen photos - my screen capture utility is not working...)

Edit:  firmware 4.02.SP3, board vers 0.1.1

Does this "spreading" go away with 0-delay on AC (trigger) coupling? Is there any chance you could measure the passives used for the charge-pump output filter? Looking at page 19 of this thread, they're using the part for a fixed 1.0GHz which I hadn't caught. As long as that's fixed, something else is up. Has anyone determined if the MUXOUT pin is being used? If not, it could be hacked to drive the Open-drain form of Lock-detect. The thing that still has me wondering is "how much" is the amplitude of this 100kHz? Why would this not be an issue with DC coupled mode? I might suggest redesigning the loop filter, but before that, I would probe the Latch Enable pin to see if it's being subject to multiple writes. If it is, that might be where the "spreading" is coming from and it might be DSS.

[David Hess]

Does this "spreading" go away with 0-delay on AC (trigger) coupling?

No and it has nothing to do with AC trigger coupling.  Triggering occurs after the signal is digitized so an unstable sampling clock is irrelevant.  It shows up when the acquisition is delayed from the trigger point or with a long record length where you can see significantly before or after the trigger point.

The same thing happens when an oscilloscope triggers on an edge which occurs at an irregular interval.  The jitter from edge to edge is not seen unless the acquisition is long enough to catch more than one.

Why would this not be an issue with DC coupled mode?

It is an issue with DC coupled triggering.  AC coupled triggering has an unrelated serious problem.

I might suggest redesigning the loop filter, but before that, I would probe the Latch Enable pin to see if it's being subject to multiple writes. If it is, that might be where the "spreading" is coming from and it might be DSS.

MarkL reported that the SPI port is not being used while this is going on which is easy enough to check.  I assume the PLL is being initialized and then left alone.

[XFDDesign]

It is an issue with DC coupled triggering.  AC coupled triggering has an unrelated serious problem.

MarkL reported that the SPI port is not being used while this is going on which is easy enough to check.  I assume the PLL is being initialized and then left alone.

I was under the impression that the whole of this discussion was a hunt to solve the AC trigger coupling oddity which shows jitter at 5,15,...us delay intervals. Has this now forked into multiple other issues?

[David Hess]

It is an issue with DC coupled triggering.  AC coupled triggering has an unrelated serious problem.

MarkL reported that the SPI port is not being used while this is going on which is easy enough to check.  I assume the PLL is being initialized and then left alone.

I was under the impression that the whole of this discussion was a hunt to solve the AC trigger coupling oddity which shows jitter at 5,15,...us delay intervals. Has this now forked into multiple other issues?

Dave identified three problems in his video: AC trigger coupling, jitter at 5us and every 10us after that, and trigger holdoff interacting with dual edge triggering.

The AC triggering coupling problem is completely separate from jitter at 5us and every 10us after that.

[Bud]

Hi everybody,

what I know is: Rigol does know the problem and they found it! There will statement/ update in the near future!
Please keep calm, they are doing their best 
cheers

Sure they do after we pointed out it is the  4360 PLL.