EEVblog #683 - Rigol DS1000Z & DS2000 Oscilloscope Jitter Problems

[motocoder]

Well, you've seen my other thread, so you know I've been doing a lot of testing for them lately

Software version: 00.03.02.03.00
Hardware version: 1.0.2.0.2
FPGA Version:
  SPU: 04.01.02
  WPU: 01.01.03
  CCU: 12.29.00
  MCU: 00.05

Did the new firmware fix the jitter that occurs on the trigger output connector as well?

Can you point me at a post that describes how to check that? I have to run an errand, but I will check for your reply when i get back and can do additional tests as appropriate.

[motocoder]

Did the new firmware fix the jitter that occurs on the trigger output connector as well?

@ motocoder
 In order to check Trigger out jitter; use the 25Mhz Square wave on Chan 1 , with DC triggering
 Then just connect trigger output on back to Channel 2
MOVING TRIGGER POINT TO THE left about 230 nSEC

If you can , also Check the Trigger output , when in the AC coupled Triggering
Thank you very much for testing Motocoder

My Trigger output Jitter pix
ps fast screen capture & postings with Marmad's RUU utility

Screen shots attached. Also notable: the scope locked up while I was scrolling the display to make the trigger visible.

[MarkL]

Thanks MarkL. I can actually see in the board level photos the two loop filter resistors marked 55B and 93A, a search on smt resistor marking resulted in 3.65K and 909 Ohm. And two out of the three capacitors could probably be measured by simply measuring the capacitance from pins CP and Tune to ground. So just one unknown will be left if do not want to disassemble the scope.

I loaded the beta software and it worked for me, although I understand it didn't work for everyone.  Before I loaded it, I captured what Rigol puts into the AD4360-7 registers in the required 3 transactions (in hex):

00 03 E9
40 31 E8
02 71 02

As a quick sanity check this loads R with 250, and 25MHz / 250 = 100kHz.  This is the divisor I was expecting.

The beta loads the following into the registers:

02 00 29
40 31 2C
00 19 02

I haven't decoded it.  From what others are experiencing, it sounds like there's still some instability.  The beta also has some fairly prominent spurs in my 1GHz output, captured on the SA below, as well as some residual modulation or perhaps phase noise.

I accessed the bottom of the board and measured the components in the loop filter and I will post them in a few minutes after I draw a small diagram.  You are right on the values you read.

For kicks before I loaded the beta, I also looked at the 1GHz output with FM demod.  Unsurprisingly, it's a well defined sawtooth.  FM demod once the beta was loaded was very flat.

EDIT: Not that it matters in this situation, but I should probably point out that the FM demod screen shot below is an aliased version of the actual waveform.  The envelope is visually the same, but the frequency is nowhere near the actual 100kHz if you look at the settings.  It's not the first time aliasing has gotten me, and probably not the last either.

[MarkL]

Ok, Bud, here's Rigol's loop filter.  These components were measured at 100kHz on a B&K 886 LCR meter.  The measurements on the capacitors were isolated by shorting the interfering capacitors to ground.  The meter took care of the remaining parallel resistance (R1) in its measurement model, so I think these values are pretty close.  Let me know what you come up with in your modeling.

I haven't put the scope back together yet.  If you need a further test or if you suspect an issue in these component values I can probably throw together a measured Bode phase plot from CP to VTUNE.

It's too bad the beta worked for me.  There's not much for me to troubleshoot.

[Bud]

Thanks MarkL

Let me play with the numbers.

However it did not fix it for you, you still getting garbage out of the PLL. Less garbage but still garbage. I think the PLL is unstable, that would explain why some people think it fixed it, some not. For those who think it fixed it they may have the problem again with variation in temperature or aging.

Can you measure the 25MHz oscillator f ?

Thks!

[Bud]

This is the type of plot what you should be getting at a smaller frequency span

[Bud]

Ok, Bud, here's Rigol's loop filter.  These components were measured at 100kHz on a B&K 886 LCR meter. 

OK, even before you measured the caps I suspected the PLL loop design was deficient, by just knowing the two resistor values. It was no matter what I did, the simulation tool could not come up with a reasonable phase margin. Now when you measured the caps and I plugged them in to the simulator it is the same thing - with this component values the phase margin value is way too low (18 degrees, whereas recommended >45) . By the book that implies potential instability of the loop.

It appears Rigol tried to make a change by increasing the PFD frequency from 100kHz to 2.5MHz (you can now see the 2.5MHz PFD leak in your last SA shots) and doing some other tweaks, it may have worked for their particular test units, but did not work for everyone in the field.

I think there may be a problem with the loop filter component values. If I configure the simulator with the same loop bandwidth but a proper phase margin, it generates totally different values for all 5 components.  I will give it another shot tomorrow, it is already 4am here.

I can also think about other deficiencies in their PLL programming (thank you for capturing the registers programming values). And the last but not least is appears to be an issue with low driving level of the clock from the PLL into the ADC. The ADC datasheet says the minimum requirement is 1.5V p-p (+7.5dBm), the PLL puts out horrible -12dBm right now based on your SA screenshot. When working properly it should be able to pump out about 0dBm, still a far cry from the minimum requirement of +7.5dBm. I have no idea how it was possible to design such a deficient circuit. Anyway, will keep digging.

[MarkL]

I can also think about other deficiencies in their PLL programming (thank you for capturing the registers programming values). And the last but not least is appears to be an issue with low driving level of the clock from the PLL into the ADC. The ADC datasheet says the minimum requirement is 1.5V p-p (+7.5dBm), the PLL puts out horrible -12dBm right now based on your SA screenshot. When working properly it should be able to pump out about 0dBm, still a far cry from the minimum requirement of +7.5dBm. I have no idea how it was possible to design such a deficient circuit. Anyway, will keep digging.

The measurement was done with a Tek P6248 1.7GHz diff probe set on divide by 10, so -11.9dBm is 1.60Vpp.  Within spec, but barely.

Sorry for the confusion.  I had already measured the Vpp into the ADC with a scope so I knew it was ok, and the frequency characteristics were more important at that point.  I should have set the offset on the analyzer so the amplitude would read true.

I will measure the crystal oscillator output when I get the Rigol re-assembled sufficiently.

Thanks for the in-depth analysis on the simulator.  I wonder if there's a single loop filter component in parallel with any of the others that would create an acceptable phase margin.  It would be an easy test to squeeze a resistor or capacitor next to one that's already there.  Unless I can get back to a released version that has the issue, maybe someone else can try it.

[Bud]

Can you measure the 25MHz oscillator f ?

Thks!

... And jitter, if you can

EDIT: Also Rigol in the beta has reconfigured the Lock Detect pin, it was not used before, now they configured digital lock detect on it (active high), so you can check what is going on there.

[MarkL]

Can you measure the 25MHz oscillator f ?

Thks!

... And jitter, if you can

EDIT: Also Rigol in the beta has reconfigured the Lock Detect pin, it was not used before, now they configured digital lock detect on it (active high), so you can check what is going on there.

The Rigol's oscillator comes in at 24.9998740MHz.  The oscillator out is a clean square wave at 3.30Vpp.

The scope I'm using (Agilent MSOX3104) does not have any delay or trigger jitter specs, so the following is in comparison to a couple of different stable crystal oscillators I have.

First, the Rigol's oscillator cycle to cycle jitter is low enough to not be observable.

Second, the best oscillator I have shows a jitter of about +/-3ns @ 100ms as compared to the Rigol's oscillator which is about +/-8ns @ 100ms.  Spot checking many delays along the way shows no cyclical jitter or any weird anomalies.

Third, the spectrum analyzer also shows the tone is extremely clean.

I think I can say with little doubt the issue is not coming from or being exacerbated by the oscillator.

However, the MUXOUT pin is always low.  Hmmm....

[MarkL]

However, the MUXOUT pin is always low.  Hmmm....

And speaking of the MUXOUT pin, here's another weird thing.  In a previous post I reported the MUXOUT pin was always high, however at that time the programming for the pin was DGND, which should have forced it low.

I just double checked the SPI packet decode and it is correct.

I wonder if MUXOUT goes to the processor or somewhere else and it was accidentally being driven high.  I could have also made a mistake and probed the DVdd or LE pin which are both right next to it.

At any rate, there's no question MUXOUT is low now, but I'm bringing this whole thing up because something else could be interfering with the operation of that pin.


Does anyone know what version is in http://gotroot.ca/rigol/DS1000Z-04_01_02_00.7z ?  Is that some hack version or is that a real release?  I see poida_pie tried it but it failed.  Has anyone succeeded?  I'd like to get back to a release before the beta.

[Bud]

However, the MUXOUT pin is always low.  Hmmm....

No surprize here, as i said the PLL still puts out garbage, so it is still unlocked.

That is kind of thing in our scopes we want locked
 

[Teneyes]

Does anyone know what version is in http://gotroot.ca/rigol/DS1000Z-04_01_02_00.7z ?  Is that some hack version or is that a real release? 

By checking a hex dump of the 2 FW files  it looks like the versions are
00.04.01.02.00
and
00.04.02.03.09
 and the nickname is the Sparrow

[MarkL]

Rigol has created updated firmware for the MSO1000Z and DS1000Z series of scopes in immediate response to the issues found by Dave and the EEVBlog community.

[...]

Lastly, if anyone has questions or concerns they want to discuss with us, we are always here. Contact your local Rigol office or distribution partner. Our USA number is 877-4-RIGOL-1. Every DS1000Z bought in the USA is under our 3 year warranty program and Rigol quality is important to us all over the world.

Thanks,

Chris Armstrong
Director of Product Marketing & SW Applications
Rigol Technologies
10200 SW Allen Blvd.  Suite C
Beaverton, OR 97005
office/fax: 877-4-RIGOL-1

Chris, it's time for an update from Rigol.  Quickly putting out a beta for everyone to test was appreciated, but dropping it on us like a bomb and then not participating in the ensuing discussion has not left anyone with a positive impression, to put it mildly.

There's clearly still a problem in the PLL lock.  For some people it's hidden well enough to make the scope usable, but for others it appears to destabilize the PLL even more.  This is the root cause of the jitter issue.

Plus, we now have keypad lockups and no path to re-install the released software if a user chooses to do so.

If Rigol is "always here" and "quality is important", please let us know the plan in light of the latest revelations.

[poida_pie]

MarkL says it very nicely.

As a minimum, easy access to the firmware version for the DS1054Z prior to the beta would be a suitable starting point.

[MarkL]

One more thing on the MUXOUT pin...

During boot there are a few pulses that indicate it's probably working ok as a LOCK signal and nothing is interfering with it.

Yellow is MUXOUT and blue is LE, and this capture is right after the third register write to the 4360 (LE low).  There are 5 positive pulses from the PFD and then nothing further.  So there ya go.  No lock.

[Bud]

On my 194Mhz PLL it functions as it should. I have  a LED connected to it, which goes on when the PLL locks.

[Bud]

Thanks for the in-depth analysis on the simulator.  I wonder if there's a single loop filter component in parallel with any of the others that would create an acceptable phase margin.  It would be an easy test to squeeze a resistor or capacitor next to one that's already there.  Unless I can get back to a released version that has the issue, maybe someone else can try it.

OK here is what can be tried on the original (non-beta) version:

connect a 100nF capacitor across C3

This will increase phase margin from 18 to 50 degrees and dampen loop response overshoot.

Can someone with the original firmware and who has access to the inside of the scope please try and report back.

What to look for: monitor voltage on pin 24 with any low bandwidth scope, expected to change from sawtooth to flat with some high frequency noise on it. If you are fancy then use your spectrum analyzer and loose couple via may be a 10-20pF capacitor to one of the PLL output shoulders (the differential clock line that goes to the ADC). Tune to 1GHz center, 5-10MHz span, capture the screenshot.

Or if you are a poor man then just visually re-check if that fixed the 5uS jitter and may be AC trigger coupling jitter.

Unfortunately on beta that will not work, at least according to the simulator.

[marmad]

Or if you are a poor man then just visually re-check if that fixed the 5uS jitter and may be AC trigger coupling jitter.

I very much doubt the two problems (5uS jitter and AC trigger coupling jitter) are related. The DS2000 suffers from the AC-coupling jitter - but not the 5us jitter.

[rf-loop]

And more problems...


This Rigol individual unit what I tried to use for measure signal generator period jittter, testing  was failed in just  first steps when I try use Rigol DS1074Z   (and this individual unit do not have at all this special "5us" jitter. But have Trigger AC coupling jitter.)

This jitter what I hit is continuously over all delay settings and clearly visible after around 50us delay and its jitter p-p rise until around 100us it is maximum and then if more delay it stay around this jitter p-p level. But also if delay is more, say several ms then there is also this fast jitter but also more and more slow drifting around.


Trigger delay jitter.

I have tried measure signal generator cycle to cycle jitter. (yes not only try, also done but I find that with cheap scope measurement/test is impossible. Test turns to opposite and may ask is this device under test or test equipment itself who is tested?

Here picked up from test some tiny example. This is not fair compare due to fact these are in different price category, so it is not apples to apples.

Both oscilloscopes tested with equal signal (Rigol did not have 50 ohm input so I use external terminator for both scopes. Rigol this model can not use faster than 5ns/div, so I use same with Siglent.
(note also that pictures are same size on your monitor due to same pixel count (800x480) but Siglent have 8" and Rigol 7" TFT.)

So, signal period time 300us (no matteer, it do it with all delay settings but under 100us delay, less and less and with some 10-30us delay it go so small that difficult to see with eyes). 
Looked next rising edge fron trigger position. (300us delay)
Both scopes DC coupled, Trigger DC coupled and trig mode rising edge middle of signal vertical (0V).  Trigger mode normal.

With example  100us delay 20ppm jitter.... With this individual DS1000Z scope can not  measure even very crap class function generator signal period jitter. 

There is really something wrong and badly.

Note If you look noise that Rigol is under 1/3 BW compared to this Siglent. More BW more noise. This is Basic fundamental - normally.


Rigol show original signal first so that it can imagine what is going on. Then next pictures zoomed to horizontal center (300us delay)



Lot of jitter. Now if you do not have other scope etc ypu may think that signal generator have this over 2ns jitter over one period.  This is cheap and totally  unusable for this work.


Lets take other tool...   


This is acceptable.  Siglent have good quality true digital side trigger engine.


And more for some imagine about performance...  delay rised to 10ms.
(now we can also see it really slows scope waveform update rate (and trigger freq counter)  because delay force scope waiting, every turn it need wait next trig + 10ms delay. Waveform update rate drops of course. (for this I turn it to dots and long persistence so that can see last capture(s), bright dots, and then persistence (old  traces)...



What I can say  - least I can say: "Not bad".

But with DS1000Z characterizing DUT period jitter. Can not do at all due to  its own really terrible delay jitter.

What is this whole  jitter hassle.
 
There is trigger AC coupling totally bad jitter, there is "5us" delay jitter (but this my unit do not have it with any detactaable level), there is this other kind of trigger delay jitter...  if Rigol do not know but oscilloscopes are time domain analyze tools... time domain need be as good as possible and trigger stability is one of most important thing in oscilloscope.  Now it looks like cosmetic signal make-up  is more important than Basic oscilloscope Fundamentals. 

Do we now get individual FW patches for every individual scopes... or is it more wise to call back all bad units and change/fix HW so that all can use same FW. Rigol need think what is price for reputation.

[Bud]

After looking at the programming values (thanks MarkL) and checking against the datasheets and common sense, I think this is what may have happened: the PLL loop filter was designed using a different chip, and later the design was used for ADF4360-7.

What makes me think so is one of the programmed parameters called Core Power Level was set to the value of 15mA in both original and beta firmware. The issue with this is per ADF4360-7 datasheet it should be 5mA. I found several references on ADI web site where they say the recommended value should be used because all of the datasheet parameters were characterized using the recommended value. They also say that the simulator will be incorrect if Core Power Level is set to any other value. So why Rigol used 15mA instead of 5mA.

ADF4360-7 is a 0.75 to 1.8GHz chip which is adequate for the 1000 series scopes. I checked other ADF4360 series ICs and sure enough ADF4360-2 which is a 2GHz chip is specified for 15mA Core Power Level. That chip may have been used in 2GSa scopes. So this may be a coincidence but appears the loop filter designed for ADF4360-2 was used for ADF4360-7. Also the 15mA setting was probably transferred over to 4360-7, too. That may have resulted in a poor PLL loop response.

That is what I think, not necessarily what in reality may have happened. But it makes sense. I plugged in the loop filter component values that MarkL measured to a ADF4360-2 simulation and it worked fairly well, phase margin was 40 degrees vs 18 degrees on ADF4360-7, and loop response was smooth with little overshoot.

[Bud]

I very much doubt the two problems (5uS jitter and AC trigger coupling jitter) are related. The DS2000 suffers from the AC-coupling jitter - but not the 5us jitter.

Well no one measured clock on DS2000 yet - it may also have problems, albeit not that pronounced.

[Bud]

I think what has to be done first is the ADC clock (ADF4360-7 PLL)  fixed. There may be cascading problems because of the garbage clock - if you look at the downstream Hittite ADC datasheet, there is another PLL in it that supposed to lock to the ADC clock, and then output of that internal PLL goes out and may be used by the downstream FPGA. Garbage in-garbage out. I think we should focus on the 4360 PLL before going any further.

[Bud]

Here is information for Rigol

- see if you guys want to ask yourself why 15mA Core Power Level was used for 4360-7. In case no one knows the answer , you should change it to 5mA per the IC manufacturer recommendation and retest/redesign/resimulate the loop filter.

- second thing to ask yourself is what was the reason to use the lowest charge Pump Current of 0.31mA. You may want to pump it up to the full 2.5mA to improve loop stability - the simulator shows phase margin increase from 18 to 39 degrees by just making this change. This can be tried now with the original DS1000 firmware - this alone may get the PLL to lock and have a solution for the scopes in the field. Still , a new loop filter should be designed for the new scopes.

- the beta firmware appears to be a fail and should be reversed, at least its PLL part which made the problem worse. The PLL loop filter used in the scopes in the field did not seem to be designed for 2.5MHz PFD.

UPDATE:

- the R counter latch data  in beta is incorrect. You forget to set the VCO calibration Band Select bits. The VCO may be freewheeling at a wrong frequency to begin with.

beta : 02 00 29
should be: 22 00 29

[Vtech]

I've tried to replicate results that rf-loop had but it seems that my unit doesn't have this "long delay jitter problem". It also doesn't have "5us jitter problem". Only "AC trigger coupling problem" is present.

Scope is MSO1074Z-S.
FW: 00.04.01.SP2
Board: 2.1.1

I don't see any jitter even at 10ms delay (1MHz test signal comes from HP fun. gen.). At ridiculous 1 second delay there is some 40ns jitter but I think this is acceptable since it is 0.04 ppm!!