i've got a display like the one that was totally smashed:
it's a panaplex plasma display, 320x256 pixels - very nice bright orange with a long persistence
the interface is synchronous, 1 bit: hsync, vsync, pixel clock, data and a active low chip enable
if i remember correctly the pixel clock is ~ 12.5MHz
the timing is very critical: if the pixel clock is not perfect it will show garbage / overdrive the pixels; if the hsync / vsync timing is off by 1 tick then it will not display a thing
i think i lost the fpga code to drive it, if anyone needs it, i'll measure the timing again