Gosh, this episode is lighting up memory lane like Las Vegas. See below; PIC processors had a hardware bug in design 1997 and earlier.
This doesn't qualify for 1K project, but I can't wait another 1024 episodes for the 2K opportunity.
In 1997, I built a remote I/O device (two 0-10V analog in, two 0-10V analog out, 8 DS1820 temp sensors, a few digital I/O) around the PIC16C73, which was a monster compared to the very popular PIC16F84. 2kWord and 192 bytes memory, ADC, PWM and even an UART.
On the UART, I had something called EXOline (similar to Modbus) protocol over RS-485, which had up to 240+ bytes packets, so those had to be decoded in-flight (none of that buffering rubbish).
Then the 1-wire protocol, which held the individual 8 device addresses in memory (64bytes). Oh, and I2C (EEPROM with calibration data) and SPI (don't remember for what) interfaces of course, bit banged.
I had to optimize all this quite significantly for, a) not enough stack levels, b) to get under the 2kWord boundary, and c) the 192 bytes available. I recall I had 1 bit free RAM (of course marked "future use") and something like 50 words of program memory left.
But the kicker on that was that I found a hardware bug, and I could point them to exactly what happened and a software work around for chips already in the field. MicroChip engineering was extremely grateful and granted me "volume price for life" and a batch of 100pc 16C73 as a token of appreciation. They let me know later that the bug was fixed and rolled out during 1998.
I also find it remarkable that I and my team found exactly the same problem (UART and Timer interrupt on same clock cycle) in the early 8031 (of (C)1980 design, fixed in (C)1982). The difference was that Intel insisted on that the problem didn't exist and it never existed, even when presented with proof. Just a coincidence that one of us noticed the (C)1980 on the SDK evaluation board and went to exchange it with a (C)1982 and problem gone.
MicroChip clearly wins over Intel in terms of servicing their engineering customers.
What was the bug? If there were two interrupts (I think it was Timer and UART) on the same clock cycle, only one return address would be pushed on the stack, but both interrupt routines would be called.
Software workaround? I don't recall the details of that, but it ended up consuming one stack level (big deal, since we only have 7 stack entries, for both ISR and CALL).