Rigol DS1052E nasty surprise!

[A Hellene]

Thank you, Saturation!

Working on-and-off on this costs me time because it disrupts my concentration... Hopefully, I'll have some more time to spend on it during the weekend, in order to make the schematics of the analog section, which, being in the signal path, could always be a major contributor to the overall signal noise.

By the way, this is an updated mainboard map populated with all the semiconductors with the exception of the discrete transistors, FETs and diodes; but there are still some points that need more investigation like the actual need for the Regulator #4 and the role of Regulator #5.

Code: [Select]


              Mainboard PCB, Top view:
             (rectangular units in cm)
------------------------------------

    0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6
                                                  ___     
 0  _______________________                      |   |   
 1  |      |            [4]                  _   |   |   
 2  | [1]  |            | |_________________| |__|   |__ 
 3  |  E   |     A     A|aa           (h) i  k      o  @|
 4  |%     |   B C   B C|    [5]    g     j    l   m  n |
 5  |%[2]  |_D_____D____|             f                 |
 6  |%[3]    F D L  K        b   d        @             |
 7  |%      F  I          (b)b  c     e      [6]     p  |
 8  \@      F  F H  F     (b)b               [7] q     @|
 9   \____G__G_J_______@________________________________|
                                                         

------------------------------------------------------------------------------------------------------------------
|     PCB components & peripherals:      |                            Power source(s):                           |
|                                        |-----------------------------------------------------------------------|
|                                        | -5V0  |+1V25#1|+1V25#2| +2V50 | +3V4  | +5V0a | +5V0d | +15V0 | +3V3#2|
|----------------------------------------+-------+-------+-------+-------+-------+-------+-------+-------+-------|
| @ : Mounting holes                     |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   |
| % : Power connector                    |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   |
|[*]: Numbered voltage regulator         |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   |
|----------------------------------------+-------+-------+-------+-------+-------+-------+-------+-------|-------|
| A : AD8510 (Low input bias Op-Amp)     |   Y   |       |       |       |       |   Y   |       |       |       |
| B : AD8370 (Variable Gain Amp)         |       |       |       |       |       |   Y   |       |       |       |
| C : LMH6552 (Differential Amp)         |   Y   |       |       |       |       |   Y   |       |       |       |
| D : 74AHC595 (8-bit shift reg)         |       |       |       |       |       |   Y   |       |       |       |
| E : TLC272 (Dual Op-Amps)              |   Y   |       |       |       |       |   Y   |       |       |       |
| F : TLC274 (Quad Op-Amps)              |   Y   |       |       |       |       |   Y   |       |       |       |
| G : 74HC4051 (Single 8-Ch mux/demux)   |   Y   |       |       |       |       |   Y   |       |       |       |
| H : 74HC4053 (Tripple 2-Ch mux/demux)  |   Y   |       |       |       |       |   Y   |       |       |       |
| I : AD5660 (16-bit DAC)                |       |       |       |       |       |   Y   |       |       |       |
| J : EL1881 (Sync. separator)           |       |       |       |       |       |   Y   |       |       |       |
| K : ADCMP562 (Dual PECL comparators)   |   Y   |       |       |       |   Y   |   Y   |       |       |       |
| L : LMH6574 (4 to 1 video multiplexer) |   Y   |       |       |       |   Y   |       |       |       |       |
| a : 74LVC2G17 (Dual Schmitt-trigger)   |       |       |       |       |       |       |       |       |   Y   |
| b : AD9288 (Dual 8-bit ADC)            |       |       |       |       |   Y   |       |       |       |       |
| c : EP3C5F256C8N (Cyclone III FPGA)    |       |       |   Y   |   Y   |   Y   |       |       |       |       |
| d : LCMXO256C (Lattice LUT)            |       |       |       |       |   Y   |       |       |       |       |
| e : IS61LPS25636A (Issi SRAM)          |       |       |       |       |   Y   |       |       |       |       |
| f : 74AHC04 (100MHz oscillator)        |       |       |       |       |       |       |   Y   |       |       |
| g : UPS051 (LCD controller)            |       |       |       |       |   Y   |       |   Y   |       |       |
|(h): THS7316 (3-Ch video amplifier)     |       |       |       |       |       |       |   Y   |       |       |
| i : TCM809 (3.08V Reset Monitor)       |       |       |       |       |   Y   |       |       |       |       |
| j : TL072C (Dual OpAmp)                |   Y   |       |       |       |       |       |       |   Y   |       |
| k : FM24CL04 (Ramtron FRAM)            |       |       |       |       |   Y   |       |       |       |       |
| l : ADSP-BF531 (BlackFin)              |       |   Y   |       |       |   Y   |       |       |       |       |
| m : H57V1262GTR (Hynix SDRAM)          |       |       |       |       |   Y   |       |       |       |       |
| n : S29GL064N90 (Spansion FLASH)       |       |       |       |       |   Y   |       |       |       |       |
| o : CEM4435A (20m? P-Ch MOSFET)        |       |       |       |       |       |       |   Y   |       |       |
| p : ISP1362 (USB controller)           |       |       |       |       |       |       |   Y   |       |       |
| q : ADM202E (RS232 interface)          |       |       |       |       |       |       |   Y   |       |       |
|----------------------------------------+-------+-------+-------+-------+-------+-------+-------+-------+-------|
|     TM056KDH02 (LCD module)            |       |       |       |       |       |       |   Y   |   Y   |       |
|----------------------------------------+-------+-------+-------+-------+-------+ ------+-------+-------+-------|
|     Keypad PCB                         |       |       |       |       |   Y   |       |       |       |       |
------------------------------------------------------------------------------------------------------------------

(*) mounted on the Bottom Layer.
TCM809 reset supervisor directly resets the DSP, the USB and the LCD controllers and probably the FPGA,
as well as the DS1000D series Active Logic Head.


    Power connector:
--------------------------
    ________________
    | 1| -GND-     |
    | 2| (+15V)    |
    | 3| (+6V4)    |
    | 4| (+6V4)    |
    | 5| -GND-     |
    | 6| (+3V4)    |
    | 7| (+3V4)    |
    | 8| -GND-     |
    | 9| (-12V)    |
    |10| (50Hz_In) |
    |11| (/LCD_Bl) |
    |12| -GND-     |
    ----------------

===========================================================



Power distribution:
-----------------------------------



            PSU PCB voltage outputs:
        --------------------------------

    PSU (+6V4):
-----------------
- Regulator #1
- Regulator #2


    PSU (+3V4):
-----------------
- Regulator #6
- Regulator #7
- Keypad PCB
- ADCMP562 (Dual PECL comparators)
- LMH6574 (4 to 1 video multiplexer)
- AD9288 (Dual 8-bit ADC)
- EP3C5F256C8N (Cyclone III FPGA) I/O
- LCMXO256C (Lattice LUT) I/O
- IS61LPS25636A (Issi SRAM)
- UPS051 (LCD controller)
- TCM809 (3.08V Reset Monitor)
- FM24CL04 (Ramtron FRAM)
- ADSP-BF531 (BlackFin) I/O
- H57V1262GTR (Hynix SDRAM)
- S29GL064N90 (Spansion FLASH)


    PSU (-12V):
-----------------
- Regulator #3
- Cooling fan


    PSU (+15V):
-----------------
- LCD module (TM056KDH02), through a 100? (01A) resistor
- TL072C (Dual Op-Amp)



            Mainboard voltage regulators:
        -------------------------------------

  Regulator #1: (+5V0d)
------------------------
Type:    NCP1117
Case:    SOT-223
Output:  5.01V
Bias:    39A+85A (249?+750?)
Marking: 1117B
Powers: 
- Regulator #5
- TM056KDH02 (LCD module)
- Front USB(+), through CEM4435A MOSFET
- 74AHC04 (100MHz oscillator)
- UPS051 (LCD controller)
- THS7316 (3-Ch video amplifier)
- ISP1362 (USB controller)
- ADM202E (RS232 interface)


  Regulator #2: (+5V0a)
------------------------
Type:    NCP1117
Case:    SOT-223
Output:  5.01V
Bias:    39A+85A (249?+750?)
Marking: 1117B
Powers: 
- Regulator #4
- AD8510 (Low input bias Op-Amp)
- AD8370 (Variable Gain Amp)
- LMH6552 (Differential Amp)
- 74AHC595 (8-bit shift reg)
- TLC272 (Dual Op-Amps)
- TLC274 (Quad Op-Amps)
- 74HC4051 (Single 8-Ch mux/demux)
- 74HC4053 (Tripple 2-Ch mux/demux)
- AD5660 (16-bit DAC)
- EL1881 (Sync. separator)
- ADCMP562 (Dual PECL comparators)


  Regulator #3 (-5V0):
------------------------
Type:    L7905CV
Case:    TO220
Output:  -5.0V
Bias:    None
Marking: L7905CV
Powers: 
- AD8510 (Low input bias Op-Amp)
- LMH6552 (Differential Amp)
- TLC272 (Dual Op-Amps)
- TLC274 (Quad Op-Amps)
- 74HC4051 (Single 8-Ch mux/demux)
- 74HC4053 (Tripple 2-Ch mux/demux)
- ADCMP562 (Dual PECL comparators)
- LMH6574 (4 to 1 video multiplexer)
- TL072C (Dual OpAmp)


  Regulator #4: (3V3#2)
------------------------
Type:    LP5951MF-3.3
Case:    SOT23-5
Output:  3.3V
Bias:    None
Marking: LKHB
Powers: 
- 74LVC2G17 (Dual Schmitt-trigger)


  Regulator #5: (+2V50)
------------------------
Type:    NCP1117
Case:    SOT-223
Output:  2.50V
Bias:    39A+39A (249?+249?)
Marking: 1117B
Powers: 
- EP3C5F256C8N (Cyclone III FPGA)


  Regulator #6: (+1V25#1)
------------------------
Type:    NCP1117
Case:    SOT-223
Output:  1.25V
Bias:    Adj pin to GND
Marking: 1117B
Powers: 
- ADSP-BF531 (BlackFin) core


  Regulator #7: (+1V25#2)
------------------------
Type:    NCP1117
Case:    SOT-223
Output:  1.25V
Bias:    Adj pin to GND
Marking: 1117B
Powers: 
- EP3C5F256C8N (Cyclone III FPGA) core



-George



[EDIT, 2011.06.21]: Mainboard PCB map update.

[saturation]

A Hellene, thanks for taking time to share your discoveries.  If you find differences between your PCB and the detailed hi-resolution images Dave has on his original tear down, please feel free to compare and contrast.  It would be interesting to see any revisions.

[A Hellene]

I will tear my credentials up!
All of them!!!

Having dismantled the DS1052E in order to figure it out, I connected the PSU, the LCD and the Keypad PCBs to the mainboard to take some live readings, in this non-trivial task of repairing this sort of a black box. Well, I realise that this kind of repair is probably next to impossible, due to the lack of any schematics or any kind of service documentation. But not everyone is an easy quitter, especially not someone who loves to play with his toys!

I dismantled the problematic DS1052E to trace down the source of the instrument's excessive noise. After having taken some readings, I decided to power it up for further investigation of its noise issue.
Well, here is something not so commonly encountered, even in the Internet Era:


Noise levels of the DS1052E dismantled!

Please, compare the noise levels of the device in this state, to the original noise levels posted at the first message of this thread:


Noise 5: Ch1 probe on the probe calibration output.

It is obvious that the noise level of the dismantled DS1052E is less than half in amplitude of the properly assembled unit noise level!

This can be partially explained, since the noise generated by the switching PSU is further away from the ADC and the Analog sections of the oscilloscope's mainboard, and in a different orientation (polarization).



Operating DS1052E dismantled!

In the picture above, it can be seen that the oscilloscope operates outside its metal shielding (its Faraday Cage), in front of a non-trivial in EMI emission terms LCD monitor, and it has its Analog Front-End wide open(!). It can also be seen the current shunt resistors directly connected to the PSU output, as well as the non-EMI protected workspace.

I think it is time for me to have a drink, to clear my mind up!


-George

[kkontak]

George,

since your problem seems to be noise related rather than some other fault, I would suggest to try some noise rejection technics.

1. Put some ferrites on the cabling harness, specifically the cable coming out of the PSU PCB. You can use the ferrites from old ATX PSUs.
2. Proper cleaning (with alcohol, brush and patient) of suspect PCBs.
3. Additional shielding with copper/aluminium foils, adhesive or not.(Yes it's ugly but if it works...)

Finally you could try to swap the AC plug into another wall socket or turn it 180 degrees to reverse N an L, if you have also 50Hz noise.

Kyriakos
Another Greek fellow.

[A Hellene]

Hello Kyriakos,

Welcome to the forum!


About my DS1052E issues, I am afraid that noise is only the symptom of the problem.

For example, in the first page of this thread there are a few screenshots of Channel 1 and Channel 2 readings, taken using a 100MΩ x100 probe: A residual noise problem alone should not distort the specific waveforms (see: "8. Ch1 x100," "9. Ch1 x100," "8. Ch2 x100" and "9. Ch2 x100". The strange thing about these screenshots is that, though the x100 probe was properly compensated using the 1.0KHz/3.0Vpp probe compensator connector, it seemed to be under-compensated when reading the 1.0MHz/5.0Vpp test signal. Noise alone, cannot do that...

Anyway, I would like to thank you for the recommendations to help reduce the PSU noise!


-George

[saturation]

Great work Hellene.  Would be good to see how the noise mitigation assists, as kkontak suggested, since removing it from its case helped a bit.

[A Hellene]

I could try to bypass the switching PSU by supplying the unit with pure, regulated DC; applying all the partial supplies at the same time will be a challenge, though.

However, my suspicion is that there will not be any major improvement, since I am almost convinced that the noise is a symptom; not the actual problem... But I think that I should let this interesting experiment speak for itself.


-George

[Zero999]

Hero,

If you open the link of the LCD module datasheet in my first message, you will see that the backlight is consisted of 14 LEDs that are connected in seven parallel arrays of two LEDs in series each (thus, 6.4V=2*3.4V).

In the PSU schematics I drew, the backlight connector is supplied by the 6.40V rail through a high-side P-Ch MOSFET switch in series to a 100?H inductor of 0.3? and a 5.1? current limiting resistor.

So, the LCD baclight is not actually powered directly by the 6.4V rail but by a proper current source.

Thanks, I missed that.

[A Hellene]

After a week and a half of on-and-off play, with the invaluable help of the magnifying glass and the continuity tester, I have managed to draw the 1052's schematics of the the whole analog section, hoping to see some kind of inconsistency in order to blame the PCB. But the schematics drawn make a perfect scene to me, so the PCB must probably he healthy. Naturally, I cannot know whether a blind/buried via/trace in this 6-layered board is functioning properly, because that was my suspicion in the first place. Of course, it could always be a latched-up (SCR) or leaky P-N junction issue to give me that ~100MHz self-oscillation noise readout symptom...

Anyway, I think I have found something that does not make sense to me. It is a weird voltage reading of -2.50V at the third output of the third 274 op-amp that drives the non inverting input B (pin 12) of the ADCMP562 (dual high speed PECL comparator). That weird voltage of -2.50V is also reflected at the test point TP105.

The bias of the specific op-amp is -18.5mV at the inverting input, +3.1mV at the non inverting input and according to its biasing components it should have a DC gain of 3.00V/V. Well, I think that this is clearly a fault, even if the scope seems to be functioning properly (excluding the increased noise issue, documented at the previous pages of that thread).

I guess that I will additionally have to program a sniffer to log and analyse the serial communications of the analog section, in order to find out whether that voltage is actually produced by the DAC or not; which I highly doubt, since the DAC cannot go below 0V and the visible driving and biasing components of the op-amp do not allow a negative voltage output.

My only objection to all this is that my day has only twenty four hours...


-George

[A Hellene]

It has been some time since I have resolved the issue mentioned above and I have not updated the thread, because these days I have visitors at home and my spare time has almost been vanished!

The specific voltage reading at the test point TP105 mentioned in the previous message is perfectly healthy. Due to a minor mistake in copying the schematics I have drawn, it seemed to be impossible for the specific op-amp to produce a negative voltage; but I was wrong. The voltage present at the TP105 is the second trigger level, used in slope triggering mode only; it was constantly negative because slope triggering mode was inactive during my initial tests. When I sniffed, read and analysed the digital communications of the analog section, the specific signal was present and healthy! Sorry about the false alarm...

Anyway, these are the schematics of the DS1052E HW58 (2011.03 batch) Channel 1 analog front-end I have drawn:



Please, note that the values of the chip capacitors are estimated (meaning read on board and recalculated), since they have no markings and were measured while in circuit. I will update the schematics when I find the time needed to measure the critical components properly, removing them from the PCB.


-George


[EDIT]: Schematics corrected and re-uploaded.
[EDIT 2]: The specific schematic sheet above has minor errors. For corrected and updated schematics look here.

[scrat]

Wow, amazing work...
But, the original problem? Still unsolved, right?

[A Hellene]

Thank you!

As for the original problem, unfortunately it is still there waiting to be resolved...


-George

[saturation]

KUDOS, Hellene, superb work.  I suspected how the inputs work but its good to see the real layout.  Look forward to your further discoveries and follow this thread closely.

Wow, amazing work...
But, the original problem? Still unsolved, right?

[scrat]

I was just looking at the schematic...
Maybe it's just me not understanding much of analogue...The AD8510 is spec'ed for a GBWP of 8MHz, and even for a very low gain it doesn't guarantee the needed bandwidth (100MHz), apart from being perhaps unstable. So how does it work, there?

[A Hellene]

Thank you, saturation.

I guess that the next step after repairing the hardware issues of the scope would be the decompilation of the firmware and the recompilation of a better one without restrictions and full of additional functionality!

Alright, I am just kidding! Everyone is free to be dreaming!
But I think that now it is my turn to thank you, for your encouraging attitude!
_____


scrat,

In the schematics it can be clearly seen that the under test signal has a separate DC path through the AD8510 amplifier via the 4.7M resistor and a separate AC path through the 330pF capacitor directly to the JFET input stage.

Signal splitting into its DC and AC components is the most popular topology for this kind of test equipment. See the links here.
_____


-George

[scrat]

Thanks! Although I'm not an expert, that capacitor was right there "speaking" by itself.
I can justify myself with the excuse the image is difficult to be seen on my lapop screen, where I see only a portion at a time

Good luck for the FW!

[A Hellene]

No worries, scrat! Neither I consider myself to be an expert in any department, despite what people say.

According to my personal cultivation, «? ». It is literally translated into "I am always learning as I am getting old" and meaning that I will always be learning as long as I live.

This wise apothegm belongs to Socrates, one of the greatest teachers of critical thinking the world has ever known.


-George



[EDIT]: The unreadable characters were a famous Classical Greek adage:
"Girasko Aei Didaskomenos" in Greeklish until our kind host, Dave, fixes the Greek characters support!

[A Hellene]

Oh, no!
My cover is blown...

[A Hellene]

Ah, I see! You are talking about the Nespresso & falling pianos commercial George Clooney!


I am afraid that this is another George Clooney, an even more better looking one than the previous one in the commercial, who does not believe in the Abrahamic delusions or in commercials; but I like espresso!
Sorry, wrong person...


-George

[A Hellene]

Thank you, my friend!


-George

[seattle]

Anyway, these are the schematics of the DS1052E HW58 (2011.03 batch) Channel 1 analog front-end I have drawn:

Oh man, some tedious and spectacular work!

What is the purpose of the varactor after the AD8370? Looks like this is a bandwidth limiting cap depending on the signal on HA595.QA pin.

Do you know is this the signal they use to hobble a 100 MHz scope into a 50 MHz scope, or is this doing the normal UI-selectable BW limit function?

[A Hellene]

Thank you, seattle.

The varicap (BBY65: <2.7pF @ Vr=4V7 and >29.5pF @ Vr=0V3 at 1MHz) limits the bandwidth to 20MHz when this option is enabled.

When the 20MHz limit is disabled the varicap is reverse biased, with 595.QA being at 5.0V and TP108 (generated by the AD5660 DAC) being negative. When the limit is enabled the varicap is biased forward(!) with 595.QA at 0.0V and TP108 positive (though I have measured the TP108 values I have not yet register them in order to provide some accurate figures). In the first case varicap's capacitance becomes <2.7pf and in the second case it changes to almost infinite, shunting the two 150pF in-series physical capacitors.

It is trivial to calculate the corner frequency response of the AD8370 amplifier, by its output impedance (95 Ohm differential) and the total parallel capacitance applied.

Regarding your second query, no! That filter, though it can be used in a more linear mode, is bistable (on/off) in Rigol. The firmware is responsible for the overall bandwidth of the device; thus you can purchase a 50MHz DS1052E and turn it to a 100MHz DS1102E or even a 150MHz DS1152E instrument, just by modifying a configuration string. Or turn a DS1102E to a DS1052E!


-George

[rf-loop]

Maybe you are interest about this: (reading also whole this topick is good "homework", better done homeworks - understand more.

With all "goods and bads" this whole topick is good to read if want working with Rigol.

https://www.eevblog.com/forum/index.php?topic=30.225

and forum user JimBeam shared (thank you) picture about Rigol front end amplifier filtering:
( I do not know if it is right. This time I do not work with Rigols and I can not check. I have handle (more than only some) Rigols but not anymore becouse this company customer care policy. (also this small display but with this can live as scope is USD300)

[A Hellene]

Thank you for that link, rf-loop!


-George

[tinhead]

When the 20MHz limit is disabled the varicap is reverse biased, with 595.QA being at 5.0V and TP108 (generated by the AD5660 DAC) being negative. When the limit is enabled the varicap is biased forward(!) with 595.QA at 0.0V and TP108 positive (though I have measured the TP108 values I have not yet register them in order to provide some accurate figures). In the first case varicap's capacitance becomes <2.7pf and in the second case it changes to almost infinite, shunting the two 150pF in-series physical capacitors.

It is trivial to calculate the corner frequency response of the AD8370 amplifier, by its output impedance (95 Ohm differential) and the total parallel capacitance applied.

right, almost exact the same on Hantek, the diff is the applied voltage :
2.2 reverse biased or 2.7 forward biased, thus 20/220Mhz switching.

More important is what behind the LMH6552, no idea how Rigol is exactly using 5 ADC ICs,
meaning how they will be switched together. On HanTekway is bit easier, as there are only 4 ICs (so 8 ADCs),
series resistor of 33Ohm, some multilayer par. capacitance + let say half pF from relais and then
4 ADCs per one series resistor. Knowing the ADC capacitance (2pF) and the fact they diff. driven
HanTekway does have estimated 16pF (ADCs) + 5pF (par.) on 33 series resistance = 229MHz -3db bw.

I think Rigol have one series resistor per 5 ADCs, so 5 x 2pF x 2 + 5pF and with 33Ohm series resistor
this give us 192MHz -3db bw.

*these 5pF par. capacitance might be a bit higher calculated than the real one, estimated 5cm trace on multilayer
with GND on bottom will be somethign about 2.5pF, but we don't know how they routed. AÓn the other side reials
and these resistor networks does have some cap. too, so i would say worst case 5pF par. capacitance.