1-bit Oscillator (Was: Pulse-density modulation)

[dmlandrum]

I'm trying to find some detailed theory on pulse-density modulation, otherwise known as Sony SDS. This is a variation of PWM, that uses a one-bit signal (varying pulse widths) to encode arbitrary signals which can then be converted to analog using a low-pass filter as an averaging function. I'm curious if there's any math that describes the theory of operation, pulse frequency limits (how many pulses are needed to accurately describe a wavelength of a waveform at some frequency - like Nyquist limits) and so on. So far, a Google search has turned up very little.

That last line means I already found the Wikipedia entry and found it lacking.

Thanks for the help!

[am2pgs]

I think PDM is nothing more than 1-bit conversion of the analogue signal  (delta sigma). The usual sampling theory applies.

The frequency of the oversampling relative to the signal frequency dictates the resolution of the digital representation or the quantization error.

Look up the relationship between the oversampling ratio in delta sigma conversion and RMS noise / quantization error. 

BTW, did you mean Sony DSD?

[dmlandrum]

Ah, yes! DSD, not SDS. Too many TLAs!

Okay, I'm pretty sure I see what you're getting at. So instead of thinking in terms of 1-bit at 2.8Mhz, I can divide that by 16 (or 24) and get an equivalent sampling rate for PCM, which is more what I'm used to. In the case of DSD, it works out to approximately 100kHz at 24 bits, which is where I would expect a high-end audio format to be (DVD-Audio is 24 bit and 96kHz). Thanks!

I have a strange idea for a 1-bit oscillator for a drone synth, and it works more or less with PDM theory. Hopefully, it'll work. I'm going to prototype it tonight.

[dmlandrum]

Upon further reflection, I think I'm still missing the point in my reply above. I think I'll seek out some of what you told me to, to see if it clears it up. Either way, I'm fairly confident I can still get a prototype of this oscillator working before too long, even if it doesn't work that well.

[am2pgs]

I think you have got the general idea.

Simply sampling a signal using an n-bit quantiser multiple times and averaging will give you better resolution. Say if you had a 1-bit quantiser and you needed to have an 8-bit resolution. In theory you would need to oversample your signal 2^(2*7) 16384 times and average the result. You will then get 8-bit resolution in theory.

To improve this (i.e. get better resolution with less oversampling, in PDM (delta-sigma) an error feedback is emplyed.This is called noise shaping the quantization so that most of the error is shifted to higher frequncies which can be removed by filtering.  In PDM the signal is sampled with a 1-bit quantizer many times(oversampled) inside a feedback loop, in each iteration, the previous quantisation error is subtracted from the input.

In DSD I beleive the 44.1 kHz signal is oversampled 64 times and it is supposed to be equivalent to 20 bit? Can't remember off the top of my head how the effective resolution is calculated in delta sigma converters. I suggest you look that up. 

[am2pgs]

Can't remember off the top of my head how the effective resolution is calculated in delta sigma converters. I suggest you look that up. 

See this link which could be useful http://www.maxim-ic.com/app-notes/index.mvp/id/1870

Note: as mentioned in the link in delta-sigma coverters for each 4x oversampling, there is a 6 dB increase in SNR. For 64x oversampling in DSD for example, this is 16*6 = 96 dB. In other words an increase in resolution of 16 bits.

[dmlandrum]

Thank you very much for the help.

I just discovered that the "trick" I came up with to make this 1-bit oscillator isn't going to work, since it doesn't ever vary the duty cycle of the pulses.

My idea was to use a high-frequency clock (a 40106 running up to 500kHz in my prototype, since that was the first capacitor I grabbed) and divide it down using a counter chip (a 4040). Each of these outputs would then be fed into a 4051 running as a demux to quickly switch between the different frequencies of incoming square waves.

I think you can probably see where the problem is. The RMS voltage of a pulse is a function of its duty cycle, not frequency.

This is based on an idea using a DIP-8 switch on the inputs of the demux to determine high or low, and then the output of the demux is a composite signal of the DIP switch settings. The circuit is here: http://www.milkcrate.com.au/_other/sea-moss/#81

What I need is a way to feed the demux with 8 variations of pulse width, not frequency. Any ideas?

Thanks very much again!

EDIT: I changed the topic name to reflect my new line of inquiry.

[am2pgs]

Not sure what you are trying to achieve.

If you want to convert a serial PDM data to a parallel digital data, then you will need something along the lines of a counter which counts the '1's in the stream for n cycles, and latch the result on the output and clear the counter.

But why would you want to do that?

[dmlandrum]

Really, I'm just trying to make an interesting oscillator for a drone synthesizer, one that I haven't yet seen done. Give me a few and I'll post a diagram of the idea.

[scrat]

Can't remember off the top of my head how the effective resolution is calculated in delta sigma converters. I suggest you look that up. 

See this link which could be useful http://www.maxim-ic.com/app-notes/index.mvp/id/1870

Note: as mentioned in the link in delta-sigma coverters for each 4x oversampling, there is a 6 dB increase in SNR. For 64x oversampling in DSD for example, this is 16*6 = 96 dB. In other words an increase in resolution of 16 bits.

64x oversampling will result in log4(64) *6 = 3*6 dB SNR increase, since the noise gets halved (-6dB) at each 4x. The document at the link you posted says to achieve 16bit from a 1-bit conversion an oversampling ratio of 4^15 would be needed.

However, even if I can't find out what a drone synthesizer is , the usual way to use 1 bit to make a DAC is PWM, but your idea of using a set of differently divided clocks should in theory work, provided that the dividers generate the same pulse width (as occurs in common dividers if run off the same clock (the reset pulse has the same width, while the period is different for each dividing value).

[dmlandrum]

Here's the basic idea in some kind of combination schematic/block form. The signal out of the demux (the 4051 is an analog mux/demux, just FYI) would then be sent to a low-pass filter for smoothing.

[dmlandrum]

Oh, and here are some examples of drone synths. Some are better than others.





I think that last one is set up to a sort of FM using 4093 chips as oscillators.

[oPossum]

What I need is a way to feed the demux with 8 variations of pulse width, not frequency. Any ideas?

LM3914 driven by a saw wave.

[dmlandrum]

I suddenly remembered something from one of my digital electronics labs at school. You can AND and OR together signals from a clock divider to get a range of PWM outputs. If you AND a signal at frequency f with a signal at f/2, you get a signal at frequency f/2 with a 25% duty. If you use OR, it's a 75% duty, again at f/2. Doing this with lots of different outputs can potentially create signals of lots of different duty cycles, all at the frequency of the slowest input signal.

It's probably not the most perfect solution, but it achieves my goal of doing this with all CMOS logic chips. I don't know why I have that as an arbitrary goal. Maybe because I don't feel like mucking about with microcontrollers for this one.

[Bored@Work]

Your statements don't match.

You talk about PDM, which doesn not make use of variable duty cycles. But then you come up with variable duty cycles, which is PWM. That does not match.

If you want, you can treat PDM as a special case of PWM, using only two fixed duty cycles, 0% (for a zero) and something > 0%, e.g. 100% (for a 1). But that's it. The key to PDM is the two duty cycles for PDM are fixed (or ignored). That's why counting the zeros and ones (adding / subtracting a fixed value, i.e. looking at the density) is enough for reconstruction. While with PWM the pulse width needs to be considered in reconstruction, this isn't done for PDM.

[am2pgs]

Sorry it's beside the point of this thread, but Scrat, I think you have got your sums wrong regarding the SNR increase. 4^15 oversampling would be correct if Noise Shaping wasn't employed.It says it in the article too. You get the extra SNR gain because of noise shaping (the error feedback) employed in sigma delta converters.

[scrat]

Sorry it's beside the point of this thread, but Scrat, I think you have got your sums wrong regarding the SNR increase. 4^15 oversampling would be correct if Noise Shaping wasn't employed.It says it in the article too. You get the extra SNR gain because of noise shaping (the error feedback) employed in sigma delta converters.

I haven't made the calculation for noise shaping, while it is straightforward for the simple oversampling+filtering case, so I'll base on the article you cited.

For the sigma-delta case, where SNR increases more since noise shaping is applied (practically by feedback), the calculation just becomes log2(64)*9 or log2(64)*15 (1st or 2nd order), as for the article, not 64/4*9 or 64/4*15.
In practice, the curve is linear in log-log scale, as in figure 8 of the article (while you were saying it's linear in semilog scale).

Again, sorry it's quite off topic.

[dmlandrum]

Okay, I was under the impression that PDM worked in a similar way to motor control with PWM, where a particular cycle of your pulse signal has a Vrms = Vm*sqrt(Duty). As you keep changing the width of the pulses, the Vrms changes, and if you smooth this waveform, you get an analog signal encoded by the varying pulse widths where each "point" of your final waveform is equal to the Vrms of the pulse cycle that created that "point."

Clearly, there is something I'm missing. I know this, and it's why I started this thread to begin with.

Now, with PDM, you have a ton of pulses moving by. If you have, say, 1010, you have a square wave of two cycles, but any number of ones and zeroes can be next to each other: 11101110 - this is equivalent to two cycles of a 75% duty cycle pulse. So it seems to me that PDM is almost the same as PWM, the difference being that the frequency of pulses is fixed, rather than the frequency of any particular waveform that results from a train of pulses. I really hope I'm explaining what I'm seeing in my head good enough here.

I really don't know if that makes any sense. It also doesn't look like my oscillator idea is going to work, not just with simple logic chips. My ultimate dream was to design an analog (or sort of hybrid analog/digital) discrete-time modular synthesis "computer" of sorts, where generic function blocks can be configured to accomplish different tasks, like filtering, oscillation of arbitrary waveshapes, and creating control signals. PDM really looks like a way to accomplish this.

[Leo Bodnar]

Does the pulse width signal have to have discrete width?  I.e. are you generating it from a digital source or via some sort of analogue threshold/integrator?

[am2pgs]

Sorry it's beside the point of this thread, but Scrat, I think you have got your sums wrong regarding the SNR increase. 4^15 oversampling would be correct if Noise Shaping wasn't employed.It says it in the article too. You get the extra SNR gain because of noise shaping (the error feedback) employed in sigma delta converters.

In practice, the curve is linear in log-log scale, as in figure 8 of the article (while you were saying it's linear in semilog scale).

Again, sorry it's quite off topic.

oh yes, I see what you mean now, so you do agree about the effect of the noise shaping. My fault for not reading the link I posted properly .

[dmlandrum]

Does the pulse width signal have to have discrete width?  I.e. are you generating it from a digital source or via some sort of analogue threshold/integrator?

Right now, I'm just making square waves with an inverting Schmitt trigger and a feedback resistor with a cap in parallel to ground.

Here's why my original idea won't work:

Let's say I have three signals like this: 10101010, 11001100, 11110000 - I.e. f, f/2, and f/4. If I string them together using the demux, I get this: 101010101100110011110000 and Holy Cow! That might work after all! Amazing how much clearer things become with an example.

Okay, I'll give it a go and see what I get.