A DC power supply for 16-bit ADC

[jahonen]

Also, one should also read Henry Ott's paper, Partitioning and Layout of a Mixed-Signal PCB. He shows that often best way is to keep contiguous ground plane, as any slots will create voltage differences across them. Lowest ground impedance and voltage differentials between different ground points is what you want. At least in EMC tests that has been usually the winning bet

This was a point of confusion for me because there are 100 papers that say do and 100 papers that say don't. It seems like there are some major themes agreed upon, like if you do, then don't run high-speed traces across the gap. One microchip note even said do for delta-sig but don't for SAR. I haven't read the one you referenced (that I can rmember) but I will when I have time. Generally, I have found that the EMC people are the ones that usually screen don't, not sure why. My normal method of dealing with conflicting information in any science is to accept the info with the best supporting evidence. I happen to like this paper:

http://www.nxp.com/documents/application_note/AN10974.pdf

I am not going to pretend to have all the answers on that one.

Maybe I'll elaborate these issues a bit more. Somebody might be interested anyway.

As far EMC is concerned, the main philosophy is to constrain the current loops as small as possible, and minimize high-frequency ground potential differences. Only way to do that, is to build the system on as low impedance ground as possible. Adding slots adds impedance between two parts of the ground plane, thus creating voltage differences between plane points. This will act as a source voltage driving a dipole antenna if there is cables connecting each part of the plane. One needs only µA's of common-mode RF-current into cables to violate the FCC/whatever imposed limits. Thus slots are not recommended. At high frequencies, it is absolutely futile to try isolate just about anything due to fact that inductive and capacitive coupling gets out of hand. It is far better and more practical to establish a controlled path for return currents. Failure to recognize this will lead to EMI failure.

Interesting appnote from NXP. While I don't question that in that case, connecting ground planes directly leads worse ADC performance than direct connection. However, single point direct connection between planes is not good representation what happens if the plane would have been solid all the way. One would need two different boards with otherwise identical setup. At least I understood that connection was only at one point. One connection point creates huge loop (MCU is second loop point). That will certainly affect negatively the performance. BTW, how would one connect the isolated planes together using single point if there are several ADC's on the same board? How that would be handled in a system where there are several of those boards? Each ADC would like to be in the single connection point...

For ordinary two-sided boards, it actually does not matter if you cross plane splits or not, since trace width should be about same than dielectric thickness for the flux coupling (current and return current) to happen. For example, the trace impedance of a 0.2 mm wide track on 1.6 mm dielectric thickness board, yields to trace impedance of 150 ?. That is way too high for logic applications, where the impedance should be something like 50-70 ohms. For standard 4-layer board, trace width of 0.2 mm at top/bottom and reference plane (VCC/GND) in next layer, yields about 75 ohms trace impedance. If course, two sided board can work if you make the board dielectric very thin, but that is mechanically unstable solution. For OP's board buildup, I wouldn't even try to squeeze it to anything less than 4 layers. Life is difficult enough even without the signal integrity and other issues. The main DSP (especially C6000) will rule probably anything less out.

For practical evidence on my side, I have designed a board at work with 16 pieces of 65 MSPS 14-bit ADC's + FPGA & acquisition memories on the same board, and ground structure was just one solid ground plane (or, actually, the board had 8 layers of solid unbroken ground planes, and 16 layers total). Noise level was what one would expect, ±1 LSB.

Another example where I witnessed the success of solid planes were when I rebuilt the Tripath based D-class audio amplifier on a 4-layer PCB. Previous layout was two layer design, with two separate grounds, what Tripath recommended. Main problems were noise and high EMI levels, which even interfered with the radio/TV reception. Original advice was that single point grounding would be used and AGND/DGND would be connected together only at the module. However, I ended up just making a 2nd layer a solid plane on the new layout, and just placed power and small-signal components into grouped sections. Result was that the new layout was not only much more EMI quiet (I could remove almost all common-mode filtering at the inputs) but also audible noise went down hugely. Ever since, I have been very suspicious when someone recommends plane splits. Another myth I have been lately busting is that one should parallel different capacitors for more wideband result, nothing could be farther from the truth when one measures the results with a VNA...

Regards,
Janne

[Chasm]

Another myth I have been lately busting is that one should parallel different capacitors for more wideband result, nothing could be farther from the truth when one measures the results with a VNA...

That would be very interesting, splitting bypass capacitors us often used/recommended in more complicated designs.

[CafeLogic]

Maybe I'll elaborate these issues a bit more. Somebody might be interested anyway.

I am interested, thank you for your input. I am left with one option, do my own testing. Henry Ott suggests a test, I think ill start with that. Ill let you know if I get it all figured out.

[onemilimeter]

For practical evidence on my side, I have designed a board at work with 16 pieces of 65 MSPS 14-bit ADC's + FPGA & acquisition memories on the same board, and ground structure was just one solid ground plane (or, actually, the board had 8 layers of solid unbroken ground planes, and 16 layers total). Noise level was what one would expect, ±1 LSB.

I always wish to design a high-speed ADC circuit. Hope you will help to clear my doubts. The analog input span of a high-speed ADC are usually very small, e.g. 2Vpk-pk. For a 14-bit ADC, 1-LSB represents 2/(2^14)=0.122mV. Would it be difficult to design a noise level lower than 1-LSB? Do you mind to share more about your build (e.g. component selection)?

Thanks.

[RayJones]

Noise is not always your enemy.

Correctly introduced "out of band" noise can help improve the linearity of signals exercising the lowest values.

This is external noise deliberately introduced with the signal, that is later removed by the DSP processing as it is outside the expected filtered bandwidth.

It all depends really on if you need the full nyquist range or not for your application.

We too at work are able to get the magical +-1LSB with a 14 bit device, but better than that due to processing gain of our FIR filter (bandwidth < nyquist) are able to achieve the full 90dB of our 16bit resultant.
This also is on a 8 layer board with acquisition memory and controller.

Pay attention to the recommended grounding pattern, and never run digital signals over the analog input area.

[jahonen]

For practical evidence on my side, I have designed a board at work with 16 pieces of 65 MSPS 14-bit ADC's + FPGA & acquisition memories on the same board, and ground structure was just one solid ground plane (or, actually, the board had 8 layers of solid unbroken ground planes, and 16 layers total). Noise level was what one would expect, ±1 LSB.

I always wish to design a high-speed ADC circuit. Hope you will help to clear my doubts. The analog input span of a high-speed ADC are usually very small, e.g. 2Vpk-pk. For a 14-bit ADC, 1-LSB represents 2/(2^14)=0.122mV. Would it be difficult to design a noise level lower than 1-LSB? Do you mind to share more about your build (e.g. component selection)?

Thanks.

The ADC is TI ADS6142, and it is driven by fully differential opamp (can't remember the part number, but Linear Technology type), which also serves as single-ended to differential converter. That is preceded by VGA instrumentation opamp and some signal conditioning. Note that most high-rate high-resolution ADCs use differential inputs to reduce noise.

BTW, grounding advice in ADS6142 datasheet is quite simple:

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide ( SLWU028 ) for details on layout and grounding.

I think that low-impedance ground system and proper partitioning (parts placement) are the most important things to get all the bits you have paid from the ADC. Not really magical, just some common sense.

Yes, small amount of noise can be advantageous, it allows you to sample signals smaller than 1 LSB, provided that there are no spurious tones there, like RayJones already pointed out. But it depends upon application.

Regards,
Janne

[CafeLogic]

BTW, grounding advice in ADS6142 datasheet is quite simple:

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide ( SLWU028 ) for details on layout and grounding.

Maybe buy they chose to split it. From the EVM user guide listed in your post:

The layout features split analog and digital ground planes; however, similar performance can be had with careful layout using a single ground plane. Users can connect the analog and digital ground planes underneath the EVM by soldering the two exposed tinned strips together.

This is consistent the non-committal line TI tends to take, for example, from the ADS1271 (24bit 105ksps) sheet:

Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter.

I can't remember which one it was but another TI app note said split the ground planes, then when you are done with the design, connect them. I took that as their recommended way to enforce layout discipline. 

I am planning on doing some testing involving the circumstances that I am most interested in. I will publish my results whenever I get around to that. If I ever have to do a 16-layer board (not really qualified for that), I will definitely take your word and use solid planes.

[RayJones]

Our design uses a "split" ground plane that joins beneath the ADC.

I used quotes as in the PCB design it is all the one ground plane, but tracks have been added to cleave the plane into two areas. These tracks do not join under the ADC.
Remember that anything you add to the ground plane removes copper, not retains like on signal layers.

These cuts absolutely prevent stray digital currents passing across the "isolated" analogue ground plane area.

[RayJones]

I should also add that the ADC we use has differential inputs, so the ground is not part of the input signal (30MHz IF).

[CafeLogic]

Our design uses a "split" ground plane that joins beneath the ADC.

I used quotes as in the PCB design it is all the one ground plane, but tracks have been added to cleave the plane into two areas. These tracks do not join under the ADC.
Remember that anything you add to the ground plane removes copper, not retains like on signal layers.

These cuts absolutely prevent stray digital currents passing across the "isolated" analogue ground plane area.

You lost me a little bit. Are you saying you used a solid ground plane but added tracks to a different layer?

[RayJones]

Solid ground plane, with tracks added to provide a psuedo split.

Protel allows you to draw on the power plane layers, but the line drawn result in etched copper.

[CafeLogic]

Solid ground plane, with tracks added to provide a psuedo split.

Protel allows you to draw on the power plane layers, but the line drawn result in etched copper.

Oh I see, thanks.

[RayJones]

We also did the same on the actual power plane, but that was a 100% isolation, no gap under the ADC.

It requires proper use of the design tools to actually make the following work.

You can actually carve away the isolated area and make it part of the GND plane.
You can then stitch the two planes together using vias.

We actually ran our signal layer between these two planes, effectively in a "ground sandwich". I suspect this was overkill, but we got the desired lack of spurious signals and full dynamic range, and have never tried just signals layers above a single ground plane - "if it ain't broke, don't fix it"  .

But as stated, you really are getting into the nitty gritty of Protel to do that.
We were using Protel99SE for this design.

[CafeLogic]

They do it a little different in the newer versions (Altium). The planes are filled polygons for which you can specify a net. They get automatically cutout for non-net objects. You can also draw your own polygon cutouts. If you want a split ground plane, you can either draw two different polygons or you can draw a single polygon and put a polygon cutout in the middle. A track always stands for positive copper on any layer (unless it's not a copper layer, like silkscreen). I didn't realize you were referring to the specifics of your software.

[RayJones]

Yeah I've only just started using Altium of late with simple double sided boards, but I'd be very surprised (annoyed) if drawn "tracks" on a power plane existed as copper.

They have traditionally been a negative layer compared to the rest, as that is how the traditional photo plotter would work.
Best thought of the isolation pads you need around unconnected holes.
It is far far easier (faster and smaller in the gerber file) to define areas where you don't want the copper on the power planes with those machines.
Signal layers, for sure copper = tracks, but power planes have always been treated in a special manner?

Perhaps they have reversed this, I should import the design into Altium and see how much of meal it makes of the power planes....

I know this is not an official support channel, but perhaps our forum host can comment ?

[CafeLogic]

Well, that is what I seem to remember from the videos with "Marty". It certainly could have a different mode with negative layers.

[RayJones]

You can of course these days use polygon pours on a conventional signal layer to achieve the same end effect.
The biggest difference however I could see with that though, by default, is the size of the isolation would be much larger, and actually include a copper land with an annular clearance ring.

We often do polygon pours of GND on top and bottom layers of normal double sided boards to get a better earthy chunk of copper.

[CafeLogic]

I just checked. If you place a line on an internal plane layer, it splits the layer. Sorry I told you wrong.

[CafeLogic]

That's the second time this week I was wrong about something I said on this board. I hate when that happens!

[RayJones]

hey, no problems, don't feel ashamed. Glad I was able to show there are other ways of doing things.

The concepts are closely related, and polygon pours are really handy on normal copper layers.
I don't know if Altium allows you to put one on a power plane, but I suspect the end effect would be a nice hole in the power plane!

[jahonen]

I am planning on doing some testing involving the circumstances that I am most interested in. I will publish my results whenever I get around to that. If I ever have to do a 16-layer board (not really qualified for that), I will definitely take your word and use solid planes.

I thought that as an experiment, I can take a unetched board, and then create two terminated transmission lines into it. Then I could use my R&S FSV7 spectrum analyzer's tracking generator to measure the isolation between two transmission lines as a function of frequency (between 100kHz and 7 GHz).

Of course, there will be some crosstalk due to mutual inductance between transmission lines, but I can always compare it with the situation where I have separated the ground planes of both transmission line structures. That should give pretty much good idea how severe the coupling is due to common ground.

Regards,
Janne

[CafeLogic]

Since I lack the experience and fancy equipment for a test like that, I was thinking I would make two boards and see which one has the least noise.

[jahonen]

Ok, here is a much simpler (I believe just about anyone can repeat this) but still very interesting test. I took a unetched PCB and soldered few wires into it. I don't know for sure how thick the copper was, but I am pretty sure that it is 35 µm. I used then a DC lab power supply in CC mode to feed 10 A across half of the copper plane, while measuring voltage between various points. One can think that points between I1 and I2 represent the digital noisy side, and p5-p7 represents the analog side. Excitation current was fed from point I1 to point I2. Measured voltage differences between points were as follows:

p1-p2: 3.42 mV
p3-p4: 5.643 mV
I1-I2: 10.4 mV
p5-p6: 208 µV
p6-p7: ~0 (less than my Gossen-Metrawatt Energy could reliably measure @ 60 mV range)
p5-p7: 213 µV

DC is theoretically the worst case, since it spreads to larger area compared to higher frequency stuff. High frequency ground current tends to concentrate right under the trace, due to energy minimization principle (the path of least inductance).

Now, we can compare this to ADC resolution. Using a NXP mentioned 12-bit resolution ADC, 1 LSB is 0.8 mV, so the measured voltage drop is about 4 times less than ADC LSB. So I think unless you want to drive ground plane currents of 40A just near your high-resolution ADC, the plane splits are not necessary (at least not for the NXP ARM).

For OP's concern about noise of less than 0.153 mV, and for realistic currents in digital section in addition that ADC's are usually differentially driven (ground reference is even farther from the digital section), the galvanically conducted plane noise is IMO quite insignificant. Reducing ground current to 1 A (even that is quite a lot), all points except in "digital side" in this test setup is much less than 1 LSB. I guess that most problems usually come from fact that digital section ground is not stiff enough (not contiguous plane), thus disrupting the analog side.

Regards,
Janne

[CafeLogic]

That is very interesting. I am guessing you measured on top of the solder lumps instead of on copper? It seems like the drop between I1 and I2 should be 7mV. Which gives me a good idea.

**Forum Math Challenge**
Calculate the exact size of the board from the information given (don't tell us Janne)

I am not sure it is possible, maybe only the proportion of width to height.

But anyway, first of all, thank you for the experiment. It is a really good way to illustrate the reasons behind recommended layout concepts. Your results are exactly consistent with what Henry Ott said which is that splitting the plane is only beneficial if your layout sucks. For example, if there where analog components at p1,p2,p3, or p4. I would also add that this depends on there being only a single return path for current, and having the digital components closest to that return path. However, we don't live an ideal world, and that can be difficult especially when the ADC is half digital/half analog in a single IC.

Of course it is hard to argue against your point given the ideal layout that you have modeled.

[onemilimeter]

Very good posting by jahonen... am really appreciate!