Considering the errors, I would go based on what your fab house can reliably do for trace/space instead of what they specifically recommend in these tables.
I don't actually have the bare board made. I use a CM. In general, I get no feedback from CMs about what design rules are good for low costs, or easier assembly, other than certain things, like they don't want to use panel scoring. They said they have trouble with that. I thought that was used because it made life easier for them. They want to do the tab routing thing. That requires hand work to smooth the edges...
after assembly. They say they are sanding down the edges of the scored boards too. That just seems like a way to blow out chips, but maybe they have conductive sand paper.
Sometimes I think people have no clue at all about static charges. It doesn't matter if you are grounded, or if the table surface is grounded, if you rub fur on a Plexiglas rod, you are going to get a massive electrical buildup. Sandpaper and fiberglass, I'm not sure, but I think it has potential... pun intended.
Nothing will be flagged as long as the trace width is as wide as their minimum or wider.
JLC gives some specs in mm and mils for example, and the mm dimension is slightly smaller due to rounding, and is most likely the "real" spec.
Yeah, the problem is, I don't know who will be building the bare boards, so I don't know their design rules. I'll contact the CM and push a bit. It's pretty definite that I'm going to have to use a BGA, and they are going to want to know about that sooner or later. They've already said this will require x-raying of each board. I suppose that can be done on the panel. They aren't real big.