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"Amps per Unit Trace Width (ATW)"

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gnuarm:
I see "Amps per Unit Trace Width (ATW)" specified in a Xilinx document.  At first I thought it might be referring to something like the unit square, but that doesn't make sense in the context. 

It appears in table 5, page 18. 

In the diagram above, figure 8 on page 17, they use a similar term as the current per mil of trace width and show the same current, 50 mA/mil "Amps Per Mil of Trace Width (APM)".  So I guess someone writing the table got a bit lazy/sloppy?  Or are these different terms?

ug1099-bga-device-design-rules.pdf

I'd give a link, but AMD seems to be too cautious to provide a decent one.  They want you to go through their process.

thm_w:
A mil is a unit of trace width, so they would be the same, just the first one (ATW) is unitless.
They seem to use ATW where the units are mm's.

https://docs.xilinx.com/r/en-US/ug1099-bga-device-design-rules/Power-Delivery-to-the-FPGA

Someone:
Those figures from Xilinx are on the conservative side (as is most of their application/guide material). But calculating trace widths and power impedances are pretty much essential tasks on most FPGA designs, not something I'd be leaving to rules of thumb or pre-canned assumptions.

gnuarm:

--- Quote from: thm_w on January 06, 2023, 09:34:32 pm ---A mil is a unit of trace width, so they would be the same, just the first one (ATW) is unitless.
They seem to use ATW where the units are mm's.

https://docs.xilinx.com/r/en-US/ug1099-bga-device-design-rules/Power-Delivery-to-the-FPGA

--- End quote ---

I think you meant, "where the units are mils".  No?

I found this document hard to read because the writing is terse and a bit confusing.  Most documents describing the land and via dimensions are confusing.  This one says it is important for the board pads to be non-solder mask-defined (NSMD), meaning no solder mask on the pads.  But the numbers they recommend for a 196 pin, 1.0 mm spaced BGA are 19.7 mil for the pad and 20.9 mil for the solder mask opening.  That doesn't leave much for alignment tolerance! 

I don't understand the use of the term "via plating".  How is this different from the via pad diameter?  They have an illustration for via in pad, where the plating is smaller than the pad.  Maybe I'm reading too much into the illustration?

I find it interesting that as PCB features shrink the unit "mil" is becoming a bit coarse.  They show for 1.0 mm ball spacing, a 4 mil space and 3 mil trace between pads.  That leaves an extra 1.7 mils "unused".  Why not spread that around a bit for 3.5 mil traces?  Or, the trace to pad spacing might be more important, so 4.5 mil space and 3 mil trace?  They actually have some errors in converting between inches/mils and mm.  19 mil is not 0.33 mm, not even close! 

If all the numbers are done in mm, 1.0 mm centers and 0.5 mm pad diameter, the trace/space can be 0.1 mm each (3.937007874016 mils).  Why obsess with making things an even mil number?  Is this something a PWB maker's software is going to flag as a "special" capability? 

gnuarm:

--- Quote from: Someone on January 06, 2023, 10:11:31 pm ---Those figures from Xilinx are on the conservative side (as is most of their application/guide material). But calculating trace widths and power impedances are pretty much essential tasks on most FPGA designs, not something I'd be leaving to rules of thumb or pre-canned assumptions.

--- End quote ---

This design is not going to be stressing anything power related.  Max clock speed of 33 MHz and most of the design is low duty cycle being slaved to a CODEC at 48 kHz sample rate.  Half of the BGA I/O won't be used, so no need for vias.  Not on this board.  I'll use the same FPGA on the test fixture, two actually.  There I'll be using most of the I/Os, but lots more room to fan out the routing.  This one will get a lot more exercise.

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